CN101662395A - Method for detecting multiprocessor interconnecting network - Google Patents
Method for detecting multiprocessor interconnecting network Download PDFInfo
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- CN101662395A CN101662395A CN200910108113A CN200910108113A CN101662395A CN 101662395 A CN101662395 A CN 101662395A CN 200910108113 A CN200910108113 A CN 200910108113A CN 200910108113 A CN200910108113 A CN 200910108113A CN 101662395 A CN101662395 A CN 101662395A
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Abstract
The invention mainly relates to multiprocessor computer technology, in particular to a method for detecting an interconnecting network in a multiprocessor server system. The invention discloses a method for detecting a multiprocessor interconnecting network, which comprises the step of: establishing adjacency relation in all processors by mutually transmitting Hello data packages, and the step ofsynchronizing link state data in all the processors for refreshing the self link state data by exchanging link state data packages describing interconnecting network topology. The technical scheme ofthe invention provides a method which has wider applicability and can be applied to the detection of more complex multiprocessor system networks including but not limited to symmetrical multiprocessors, non-equilibrium memory access system structures, full-equilibrium memory organization structures and the like.
Description
Technical field
The present invention relates to multiprocessor computer technology, particularly relate to the method that interference networks detect in the multiprocessor servers system.
Background technology
Computer system with two or more independent processors is called as multicomputer system, connects by transmission channel between the processor, can share also independently to have memory and peripheral hardware.Multiple processor computation system can come out by different architecture Design, but its framework mainly is divided into following three kinds at present: symmetric multiprocessor SMP (Symmetric Multi Processing), nonuniform memory access architecture NUMA (Non Uniform Memory Architectures), abundant balanced memory organization SUMO (Sufficiently Uniform Memory Organization).
Transmission channel between any two processors has constituted the interference networks of multicomputer system.When multicomputer system carries out parallel processing, can manage between the device constantly transport address, data or synchronized packets information throughout by interference networks, make other processor co-ordinations of each processor and this process of execution.
Generally, systematic schematic diagram has been described the interference networks of multicomputer system accurately, but is things of a difficulty by reading the interference networks that schematic diagram obtains system.And in the work of reality, perhaps the transmission channel between certain two processor breaks down, and perhaps the groove position of certain processor is in vacant state, and this brings uncertainty all can for final interference networks.Because above problem needs the interference networks that kind of method can detect multicomputer system fast and accurately.
The patent No. is that the patent of invention of CN200810002268.3 has disclosed the method that is used for the symmetric multiprocessor interconnection, its by one independently controller each processor is appointed as host device processor successively, and send packets to other processors and obtain interference networks between multiprocessor, calculate transmission path by interconnection matrix then.But this method is only applicable to the symmetric multiprocessor system, and this functional communication link by sign fetches the method for the mapping that Makes Path, and can not be applied to the network measuring of more complicated multicomputer system.
Summary of the invention
Because existing multiprocessor interconnecting network detection method can only be confined to detect the interference networks of symmetric multiprocessor, technical problem to be solved by this invention is to provide a kind of applicability more extensive, can be applied to include but not limited to symmetric multiprocessor Symmetric Multi Processing (SMP), nonuniform memory access architecture Non Uniform Memory Architectures (NUMA), the method of the multicomputer system network measuring that abundant balanced memory organization Sufficiently Uniform Memory Organization (SUMO) framework etc. are more complicated.
For addressing the above problem, the invention discloses a kind of multiprocessor interconnecting network detection method, may further comprise the steps:
Set up the step of syntople, the Hello packet that comprises neighbor list by mutual transmission between all processors is set up syntople;
The step of synchronization link status data, each processor is all safeguarded Link State data of describing interconnection network topological structure, and the Link State data that refresh self by exchanging chain line state packet between all processors are to carry out the Link State data synchronization.
Adopt the open multiprocessor interconnecting network detection method of the present invention,, can detect existing effective processor network topological structure of the multicomputer system of various complexity such as SMP, NUMA and SUMO flexibly fast.
Further, said method also comprises:
The Path selection step, Link State data after all processor utilizations synchronously, adopt shortest path first oneself being that root node calculates routing table separately, described routing table comprises the purpose processor that this processor can arrive and arrives the next processor that this purpose processor will be transmitted;
After arbitrary processor receives packet, resolve its purpose processor and search local routing table, with the next processor of decision forwarding.
After adopting above-mentioned Path selection, select the shortest path the mulitpath that the transmission between source processor and target processor may exist, make that transmission speed is the fastest, the operational efficiency of system is the highest.
Description of drawings
Fig. 1 is based on 8 road multicomputer system schematic diagrames of SUMO framework;
Fig. 2 is the network topology structure figure of multicomputer system;
Fig. 3 is the multicomputer system initialization flowchart;
Fig. 4 is the workflow diagram that syntople is set up;
Fig. 5 is the workflow diagram of Link State data sync;
Fig. 6 is the routing topology figure of processor A;
Embodiment
Below in conjunction with accompanying drawing the present invention is described in detail.
The design architecture of multiprocessing computer system is described with 8 road multiprocessor servers systems 100 based on the SUMO framework of the Opteron of AMD chip as shown in Figure 1.Because 3 HT hyperthread buses that the Opteron processor is integrated, each Opteron processor can connect 3 other Opteron processors at most, thus can derive more complicated multicomputer system according to the SUMO framework,
The present multicomputer system of describing with interference networks such as Fig. 2 200 is as the preferred embodiments of the present invention.As shown in Figure 2, node is represented processor, and link between processors is then represented on the limit, and definition processor A is packet inlet in the multiprocessor interconnecting network (can have a plurality of data inlets).Be connected with adjacent processor by the HT bus between the processor, and the routine weight value of adjacent processor equal (being 1), every HT bus of processor all comprises a transmit port and receiving port.
The method that the present invention proposes the multiprocessor interconnecting network detection is achieved as follows:
As shown in Figure 3, system before transmission of data packets between the processor, at first to finish the detection of interference networks, mainly finish: set up syntople (step 301), synchronization link status data (step 302) between the processor by two steps.
Data packets for transmission mainly contains between the processor:
1) Hello packet.Can set up syntople by sending out the Hello packet mutually between the processor, wherein all comprise a neighbor list in each Hello packet.
2) Link State packet (L-S packet).Can be between the processor by sending out the Link State data that the L-S packet is described interconnection network topological structure synchronously mutually.
3) confirm packet.After processor is received the L-S packet, and after finishing the Link State data sync, send and confirm that packet is as replying.
Below will be described in detail these two steps.
As shown in Figure 4, set up syntople by mutual transmission Hello packet between the processor, concrete steps are as follows:
1) each processor periodically sends Hello packet (step 401) to adjacent processor by transmit port, receives Hello packet (step 403) by receiving port simultaneously.
2) in the Hello packet, comprise a neighbor list, when processor receives the Hello packet that adjacent processor is sent, the adjacent processor that then will send this Hello packet is added into (step 405) among the neighbor list of the Hello packet that oneself will send.
3) when " seeing " in the neighbor list in the Hello packet that processor is receiving arrives oneself (step 406), then successfully set up syntople two-way communication (step 408).
4), think that then this syntople sets up failure (step 407) if within a scheduled time, do not receive the Hello packet (step 402) that adjacent processor sends.
After setting up syntople between the processor, each processor is all safeguarded Link State data of describing interconnection network topological structure.The Link State data that processor refreshes self by exchanging chain line state packet (L-S packet) are to reach synchronous purpose.
Fig. 5 has described the workflow of transmit port and receiving port on the single link of processor, and then the flow process of other links is also identical therewith.Its step is as follows:
1) at the transmit port of link, processor sends L-S packet (step 501) to adjacent processor, and the wait acknowledge packet.
2) at the receiving port of link, processor receives (step 503) behind the L-S packet that adjacent processor sends on this link, checks the Link State data data (step 504) of oneself.If do not comprise this link in the Link State data, then add this link (step 505), and transmission affirmation packet is finished (step 502) to show to refresh; If comprised this link in the Link State data, then directly send and confirm packet.
3) processor is received the affirmation packet, then stops to send L-S packet (step 507) to this adjacent processor; As do not receive and confirm then to resend the L-S packet by packet (step 506) through after the scheduled time.
4) refresh the data of oneself if add linking status behind the L-S packet that receives adjacent processor on this link, then the adjacent processor to other links of this processor starts transmission L-S packet (step 508).
5) finish syntople when all processors and set up, then the Link State data of all processors are also just synchronous.
Realize effective transmission of packet between the processor, can also carry out the selection of transmission path, mainly realize by calculating shortest path tree (step 303).Specific implementation is as follows:
After the Link State data of processor were finished synchronously, the Link State data after all processor utilizations synchronously adopted shortest path first oneself being that root node calculates routing table separately.This routing table comprises the purpose processor that this processor can arrive and arrives the next processor that this purpose processor will be transmitted.As being source node with the processor A, the routing topology figure that calculates as shown in Figure 6.
The algorithm of above-mentioned shortest path, the most frequently used is dijkstra's algorithm, still, equally also can adopt and include but not limited to A
*Algorithm, the SPFA algorithm, bellman-ford algorithm, the Floyd-Warshall algorithm, Johnson algorithms etc. are at the algorithm of interior any shortest path, and above-mentioned algorithm all can satisfy goal of the invention.
Data packet transmission (step 304), when the routing table of all processors generations oneself, then packet can be that source node is to other random processor transmission with the packet inlet then.After processor receives packet, resolve its purpose processor and search local routing table, the next processor of transmitting with decision, thus guarantee that packet is with the shortest path processor that achieves the goal.
Be the preferred embodiments of the present invention only below, be not limited to the present invention, for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1, a kind of multiprocessor interconnecting network detection method is characterized in that, may further comprise the steps:
Set up the step of syntople, set up syntople by mutual transmission Hello packet between all processors;
The step of synchronization link status data, the Link State packet by exchange description interconnection network topological structure between all processors refreshes the Link State data of self.
According to the described multiprocessor interconnecting network detection method of claim 1, it is characterized in that 2, the described step of setting up syntople comprises:
2.1) periodically to adjacent processor transmission Hello packet, by receiving port reception Hello packet, wherein, described Hello packet comprises neighbor list to each processor simultaneously by transmit port;
2.2) after each processor receives the Hello packet, the adjacent processor that sends this Hello packet is added among the neighbor list of the Hello packet that oneself will send.
2.3) when neighbor list in the Hello packet that receives of arbitrary processor comprises oneself, then set up the processor of this reception Hello packet and send syntople between the processor of this Hello packet.
3, according to the described multiprocessor interconnecting network detection method of claim 1, it is characterized in that the step of described synchronization link status data comprises:
3.1) each processor sends the Link State packet of describing interconnection network topological structure to adjacent processor;
3.2) after each processor receives the Link State packet that adjacent processor sends on arbitrary link, in oneself Link State data, add the link that does not comprise, and send the affirmation packet to the adjacent processor that sends this Link State packet;
3.3) after each processor receives the affirmation packet that adjacent processor sends on arbitrary link, stop to confirm the adjacent processor transmission Link State packet of packet to this transmissions.
3.4) after each processor adds link and refresh the Link State data, start to the adjacent processor of other links of this processor and to send the Link State packet.
4, according to the described multiprocessor interconnecting network detection method of claim 3, it is characterized in that, described step 3.3) further comprises in: do not receive the affirmation packet as processor, through sending the Link State packet to this adjacent processor again after the scheduled time.
5, according to each described multiprocessor interconnecting network detection method in the claim 1 to 4, it is characterized in that, also comprise the Path selection step, all processors are according to the Link State data computation routing table separately after synchronous, with the path of decision transmission of data packets.
6, according to the described multiprocessor interconnecting network detection method of claim 5, it is characterized in that, described Path selection step comprises: the Link State data after each processor utilization synchronously, adopt shortest path first oneself being that root node calculates the routing table that comprises the purpose processor that this processor can arrive and arrive the next processor that this purpose processor will transmit separately.
7, according to the described multiprocessor interconnecting network detection method of claim 6, it is characterized in that, further comprise: after each processor receives packet, resolve its purpose processor and search local routing table, with the next processor of decision forwarding.
According to the described multiprocessor interconnecting network detection method of claim 6, it is characterized in that 8, described shortest path first is a dijkstra's algorithm.
According to the described multiprocessor interconnecting network detection method of claim 6, it is characterized in that 9, described shortest path first is the A* algorithm.
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| CN200910108113A CN101662395A (en) | 2009-06-23 | 2009-06-23 | Method for detecting multiprocessor interconnecting network |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110347632A (en) * | 2018-04-04 | 2019-10-18 | 杭州海康机器人技术有限公司 | A kind of communication means and device |
| CN116226026A (en) * | 2023-03-06 | 2023-06-06 | 苏州工业园区服务外包职业学院(苏州市服务外包人才培养实训中心) | Asymmetric judging method of multiprocessor interconnection network |
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2009
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110347632A (en) * | 2018-04-04 | 2019-10-18 | 杭州海康机器人技术有限公司 | A kind of communication means and device |
| CN110347632B (en) * | 2018-04-04 | 2022-05-06 | 杭州海康机器人技术有限公司 | Communication method and device |
| CN116226026A (en) * | 2023-03-06 | 2023-06-06 | 苏州工业园区服务外包职业学院(苏州市服务外包人才培养实训中心) | Asymmetric judging method of multiprocessor interconnection network |
| CN116226026B (en) * | 2023-03-06 | 2024-08-13 | 苏州工业园区服务外包职业学院(苏州市服务外包人才培养实训中心) | Asymmetric judging method of multiprocessor interconnection network |
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Application publication date: 20100303 |