CN101656281B - Wafer illumination structure and manufacturing method thereof - Google Patents

Wafer illumination structure and manufacturing method thereof Download PDF

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Publication number
CN101656281B
CN101656281B CN2008101449949A CN200810144994A CN101656281B CN 101656281 B CN101656281 B CN 101656281B CN 2008101449949 A CN2008101449949 A CN 2008101449949A CN 200810144994 A CN200810144994 A CN 200810144994A CN 101656281 B CN101656281 B CN 101656281B
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illumination structure
wafer illumination
deformation layer
deformation
support substrate
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CN101656281A (en
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陶青山
徐子杰
王振奎
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Epistar Corp
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Epistar Corp
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Abstract

The invention discloses a wafer illumination structure and a manufacturing method thereof. The wafer illumination structure comprises a supporting substrate, an anti-deformation layer positioned on the supporting substrate, a bonding layer positioned on the anti-deformation layer and an illumination laminated layer positioned on the anti-deformation layer. The bonding layer connects the anti-deformation layer and the illumination laminated layer. A deformation height, which is generated in a thinning process, of the wafer illumination structure is not about less than 10 times of the thickness of the wafer illumination structure. The deformation height is the height difference from a junction between the lower surface of the wafer illumination structure and one side line to a geometrical central point of the lower surface of the wafer illumination structure; and the thickness is the height difference from the geometrical central point of the lower surface of the wafer illumination structure to the geometrical central point of the upper surface of the wafer illumination structure. The anti-deformation layer can reduce or eliminate the deformation, such as warping, which is generated after the supporting substrate is thinned.

Description

Wafer illumination structure and manufacture method thereof
Technical field
The present invention relates to a kind of ray structure, relate in particular to a kind of wafer illumination structure with an anti-deformation layer.
Background technology
Light-emitting diode (Light-emitting Diode; LED) be a kind of solid semiconductor element, it comprises a p-n junction (p-n junction) at least, and this p-n junction is formed between p type and the n type semiconductor layer.When the bias voltage that on p-n junction, applies to a certain degree, the electronics in the hole in the p type semiconductor layer and the n type semiconductor layer can in conjunction with and the release bright dipping.The zone that this light produces generally is called luminous zone (light-emitting region) again.
The principal character of LED is that size is little, luminous efficiency is high, the life-span is long, reaction is quick, reliability is high and colourity is good, has been widely used on electrical equipment, automobile, signboard and the traffic sign at present.Along with the appearance of all-colour LED, LED replaces traditional lighting apparatus gradually, as fluorescent lamp and white heat bulb.
LCD (Liquid Crystal Display; LCD) be widely used in every electronic product, as screens such as desktop or notebook computer, portable phone, Vehicular guidance system and TVs.In the general design, the light source of LCD is by backlight module (Back Light Unit; BLU) provide, LED then is one of main light source of BLU.When the size of display trend development towards slimming, for the requirement of LED thickness also move towards thinner better.
Summary of the invention
The invention provides a kind of wafer illumination structure, comprise a support substrate; One anti-deformation layer is positioned on the support substrate; One tack coat is positioned on the anti-deformation layer; And a luminous lamination, being positioned on the tack coat, wherein anti-deformation layer can reduce or eliminate support substrate by distortion that thinning produced.
The invention provides a kind of method of making wafer illumination structure, comprising provides a support substrate; Form an anti-deformation layer on support substrate; Form luminous being stacked on the growth substrate; Form a reflector on luminous lamination; Engage reflector and anti-deformation layer by a tack coat; Remove the growth substrate; Form a protective layer on luminous lamination, carry out the thinning support substrate again.Wherein also can between tack coat and luminous lamination, form a reflector, or on luminous lamination and support substrate, form a protective layer.
Description of drawings
Figure 1A is the profile of the wafer illumination structure of demonstration one embodiment of the invention.
Figure 1B～1C is the distortion profile of the wafer illumination structure of demonstration one embodiment of the invention.
Fig. 1 D～1E is the profile of the wafer illumination structure of demonstration one embodiment of the invention.
Fig. 2 A～2B is the profile of the wafer illumination structure of demonstration another embodiment of the present invention.
Fig. 3 is a schematic diagram, shows the wafer illumination structure that utilizes the cutting embodiment of the invention and the schematic diagram of the light-source generation device that the naked core that produces formed.
Fig. 4 is a schematic diagram, shows the wafer illumination structure that utilizes the cutting embodiment of the invention and the schematic diagram of the backlight module that the naked core that produces formed.
Fig. 5 is for showing the flow chart of wafer illumination structure manufacture method of the present invention.
Description of reference numerals
Support substrate 10,20
Intersection 16
Upper surface geometric center point 17
Lower surface geometric center point 18
Anti-deformation layer 11,21
Tack coat 12,22
Luminous lamination 13,23
Reflector 14,24
Protective layer 15,25
First bond course 131,231
Luminescent layer 132,232
Second bond course 133,233
Light-source generation device 3
Light source 31
Power system 32
Control element 33
Backlight module 4
Optical element 41
Thickness h
Deformation height d
The first pad a
The second pad b
Embodiment
Figure 1A is depicted as the part schematic diagram of a wafer illumination structure.Wafer illumination structure 1 comprises a support substrate 10; One anti-deformation layer 11 is positioned on the support substrate 10; One tack coat 12 is positioned on the anti-deformation layer 11; One luminous lamination 13 is positioned on the tack coat 12.Wherein, anti-deformation layer 11 can reduce or eliminate support substrate 10 by distortion that thinning produced.
Support substrate 10 removes the back in order to carry luminous lamination 13 at the growth substrate of luminous lamination 13, and its material can be including but not limited to metal, electrical insulating material, composite material, metal-base composites (Metal Matrix Composite according to product design, characteristic or requirement; MMC), ceramic matric composite (Ceramic Matrix Composite; CMC), silicon (Si), Echothiopate Iodide (IP), zinc selenide (ZnSe), aluminium nitride (AlN), GaAs (GaAs), carborundum (SiC), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), sapphire (Sapphire), zinc selenide (ZnSe), zinc oxide (ZnO), indium phosphide (InP), lithium gallium oxide (LiGaO 2), lithium aluminate (LiAlO 2) or the combination of these materials.Its thickness after by thinning is haply less than about 70 microns, preferably less than about 40 microns, more preferably less than about 20 microns.Thinning is to instigate thickness to reduce, for example at support substrate 10 relatively and away from the surface of luminous lamination 13, make support substrate 10 be reduced to about 40 microns of thickness by lapping mode from 300 microns of general thickness.
Anti-deformation layer 11 has the anti-stress that disappears, and makes support substrate 10 after thinning, and the stress numerical of wafer illumination structure 1 integral body reduces, to reduce or eliminate distortion.The generation of anti-stress of disappearing is to cause owing to the microstructure of anti-deformation layer 11 or the deposition defective of molecule, and for example support substrate 10 is different with the lattice shape of anti-deformation layer 11, forms the lattice dislocation when causing molecular binding, thereby produces the anti-stress that disappears.In addition, in the process of anti-deformation layer 11 deposition, piling up between the molecule can form hole, causes the molecules align dislocation, also can produce the anti-stress that disappears.Shown in Figure 1B, support substrate 10 is an example with the sapphire, and general thickness is approximately 300 microns.Yet for specific purpose, for example heat radiation, support substrate 10 can be by thinning, and the support substrate 10 after the thinning can produce a stress, is a tensile stress for example, makes support substrate 10 distortion warpages become a concavity, produces deformation height d.When known wafer illumination structure did not comprise anti-deformation layer 11, the deformation height d that is produced was bigger, for example was about 200 times an of thickness h of wafer illumination structure, and about 1 centimetre, thereby influence follow-up naked core technology, the yield of for example cutting, splitting and encapsulation etc.Deformation height d is the difference in height of an intersection 16 of the lower surface of wafer illumination structure 1 and side to a lower surface geometric center point 18, and thickness h is the difference in height of a upper surface geometric center point 17 of wafer illumination structure 1 to lower surface geometric center point 18.In the present embodiment, be example with circular wafer, upper surface geometric center point 17 and lower surface geometric center point 18 can be respectively the center of circle of wafer upper and lower surface.In the present embodiment, the anti-stress that disappears of the anti-deformation layer 11 of wafer illumination structure 1 is to be a compression, to reduce deformation height d 10 times to the maximum thickness h that is about wafer illumination structure 1, preferably is about 5 times, goodly be about 0 times, to reduce or eliminate the buckling deformation of support substrate 10.The material of anti-deformation layer 11 for example is GaN, when the chip architecture thickness h is 50 microns, can make deformation height d be no more than 500 microns.Yet support substrate 10 also can produce compression after the thinning, shown in Fig. 1 C, makes support substrate 10 form a convex, decides on its material.At this moment, 11 palpus of anti-deformation layer are selected the material that can produce tensile stress for use, to reduce or eliminate the buckling deformation of support substrate 10.With the present embodiment is example, and the thickness of anti-deformation layer 11 is less than about 30 microns, preferably less than about 10 microns, greater than about 2 microns, more preferably greater than about 3 microns.Anti-deformation layer 11 by chemical vapour deposition technique (CVD), Metalorganic chemical vapor deposition method (MOCVD), vapour phase epitaxy method (VPE), liquid phase epitaxial method (LPE), molecular beam epitaxy (MBE), plasma chemical vapor deposition (PECVD) or other similar fashion be deposited on support substrate 10 on.Its material is including but not limited to aluminium oxide (Al xO y), silicon nitride (SiN x), silica (SiO x), titanium oxide (TiO x), the combination of gallium nitride (GaN) or above-mentioned material.
Tack coat 12 can be metal or nonmetallic materials in order to engage support substrate 10 and luminous lamination 13.If metal material, tack coat 12 can have the function of reflection ray.Its material is including but not limited to polyimides (PI), benzocyclobutene (BCB), cross fluorine cyclobutane (PFCB), epoxy resin (Epoxy), other organic binding materials, indium (In), tin (Sn), aluminium (Al), gold (Au), platinum (Pt), zinc (Zn), silver (Ag), titanium (Ti), plumbous (Pb), palladium (Pd), germanium (Ge), copper (Cu), nickel (Ni), tin gold (AuSn), patina indium (InAg), aurification indium (InAu), beryllium gold (AuBe), germanium gold (AuGe), zinc impregnation gold (AuZn), tin lead (PbSn), the combination of indium palladium (PdIn) or these materials.
Luminous lamination 13 comprises one first bond course 131 at least, is positioned on the tack coat 12; One luminescent layer 132 is positioned on first bond course 131; With one second bond course 133, be positioned on the luminescent layer 132.Wherein, first bond course 131 can be i type, p type or n N-type semiconductor N, second bond course 133 electrically then different with first bond course 131.The structure of luminescent layer 132 can be divided into single heterojunction structure (single heterostructure; SH), double-heterostructure (double heterostructure; DH), bilateral double-heterostructure (double-side double heterostructure; DDH) and multi-layer quantum well (multi-quantum well; MQW) etc., its material is including but not limited to the semiconductor CdZnSe of II-VI family, or III-V family semiconductor, as AlGaInP, AlN, GaN, AlGaN, InGaN, AlInGaN.
Shown in Fig. 1 D, wafer illumination structure 1 also comprises reflector 14, between luminous lamination 13 and the tack coat 12 or between anti-deformation layer 11 and the tack coat 12, can reflect the light that self-luminous lamination 13 penetrates, its material is including but not limited to the combination or the Bragg reflecting layer of indium (In), tin (Sn), aluminium (Al), gold (Au), platinum (Pt), zinc (Zn), silver (Ag), titanium (Ti), tin (Pb), germanium (Ge), copper (Cu), nickel (Ni), beryllium gold (AuBe), germanium gold (AuGe), zinc impregnation gold (AuZn), tin lead (PbSn), these materials.
Wafer illumination structure 1 also comprises one first pad a, is positioned on second bond course 133; With one second pad b, be positioned under the support substrate 10; At this moment, support substrate 10 is preferably a conductor.The first pad a and the second pad b form with support substrate 10 with luminous lamination 13 respectively and electrically connect, and when the first pad a and the second pad b lay respectively at the heteropleural mutually of support substrate 10, wafer illumination structure 1 is a vertical stratification.
Shown in Fig. 1 E, roughening treatment can be done in the surface of second bond course 133, to form non-smooth surface, increases light extraction efficient.One protective layer 15 is formed on the luminous lamination 13, stretches out around the first pad a sidewall and along luminous lamination 13, to protect luminous lamination 13 and other structures under it to avoid making moist or injury such as vibrations, also avoids the short circuit that causes because of routing.The material of protective layer 15 is including but not limited to dielectric material; Su8; benzocyclobutene (BCB); cross fluorine cyclobutane (PFCB); epoxy resin (Epoxy); acrylic resin (Acrylic Resin); cyclic olefin polymer (COC); polymethyl methacrylate (PMMA); polyethylene terephthalate (PET); Merlon (PC); Polyetherimide (Polyetherimide); fluorocarbon polymer (Fluorocarbon Polymer); silica gel (Silicone); glass; aluminium oxide; silica; titanium oxide; SiN X, TiO 2, spin-coating glass (SOG), these materials combination or other transparent materials.
Another embodiment is shown in Fig. 2 A, and a wafer illumination structure 2 comprises a support substrate 20; One anti-deformation layer 21 is positioned on the support substrate 20; One reflector 24 is positioned on the anti-deformation layer 21; One tack coat 22 is positioned on the reflector 24; One luminous lamination 23 is positioned on the reflector 24; With a protective layer 25, be positioned on the luminous lamination 23.Wherein, anti-deformation layer 21 can reduce or eliminate support substrate 20 and be ground the distortion that is produced.
Support substrate 20 removes the back in order to carrying luminous lamination 23 at the growth substrate of luminous lamination 23, and its thickness after by thinning is less than about 70 microns, preferably less than about 40 microns, more preferably less than about 20 microns.Thinning is to instigate thickness to reduce, and for example support substrate 20 is reduced to 40 microns of thickness from 300 microns of general thickness.When thinning support substrate 20, anti-deformation layer 21 has the anti-stress that disappears, and makes support substrate 20 after thinning, and the stress numerical of wafer illumination structure 2 integral body reduces, to reduce or eliminate distortion.With the present embodiment is example, and the thickness of anti-deformation layer 21 is less than about 30 microns, preferably less than about 10 microns, greater than about 2 microns, more preferably greater than about 3 microns.Support substrate 20 after the thinning can produce deformation height, and known wafer illumination structure does not comprise anti-deformation layer 21, and the deformation that is produced is highly bigger, for example is 200 times an of thickness h of wafer illumination structure, about 1 centimetre.Deformation highly is the difference in height of an intersection of the lower surface of wafer illumination structure 2 and side to a lower surface geometric center point, and thickness h is the difference in height of lower surface geometric center point to the upper surface geometric center point of wafer illumination structure 2.In the present embodiment, be example with circular wafer, the upper and lower surface geometric center point can be the center of circle of wafer upper and lower surface.Anti-deformation layer 21 can reduce by 10 times to the maximum thickness h that is about wafer illumination structure 2 of deformation height, preferably is about 5 times, goodly is about 0 times, to reduce or eliminate the buckling deformation of support substrate 20.When for example thickness h was 50 microns, anti-deformation layer 21 can make deformation highly be no more than 500 microns.Tack coat 22 can be metal or nonmetallic materials in order to engage support substrate 20 and luminous lamination 23.The light that self-luminous lamination 23 penetrates can be reflected in reflector 24.Protective layer 25 is formed on the luminous lamination 23; stretch out around the sidewall of the sidewall of the first pad a and the second pad b and along luminous lamination 23 respectively; to protect luminous lamination 23 and other structures under it to avoid making moist or injury such as vibrations, also avoid the short circuit that causes because of routing.
Luminous lamination 23 comprises one first bond course 231, a luminescent layer 232 and one second bond course 233 at least.Luminous lamination 23 etched part first bond courses 231 that expose, at this moment, one first pad a is positioned on second bond course 233, and one second pad b be positioned on the exposed part of first bond course 231, support substrate 20 is preferably insulation, for example is an insulator or is insulating layer coating on the conductor.Shown in Fig. 2 B, roughening treatment can be done in the surface of second bond course 233, to form non-smooth surface, increases light extraction efficient.When the first pad a and the second pad b lay respectively at the same side of support substrate 20, wafer illumination structure 2 is a horizontal structure.
Fig. 3 is for showing a light-source generation device schematic diagram, and this light-source generation device 3 comprises the naked core that the wafer illumination structure among the arbitrary embodiment of cutting the present invention is produced.This light-source generation device 3 can be a lighting device, and for example street lamp, car light or room lighting light source also can be back lights of backlight module in a traffic sign or the flat-panel screens.This light-source generation device 3 comprises a light source 31 that aforementioned naked core forms, power system 32 with supply light source 31 1 electric currents and a control element 343, in order to control power system 32.
Fig. 4 is for showing a backlight module generalized section, and this backlight module 4 comprises the light-source generation device 3 in the previous embodiment, and an optical element 41.Optical element 41 can be handled the light that is sent by light-source generation device 3, to be applied to flat-panel screens, and the light that sends of scattering light source generation device 3 for example.
Fig. 5 shows a kind of flow chart of making the method for wafer illumination structure 1, and wherein comprising provides a support substrate 10; Form an anti-deformation layer 11 on support substrate 10; Form a reflector 14 on anti-deformation layer 11; Form a luminous lamination 13 on a growth substrate; Engage reflector 14 and luminous lamination 13 by a tack coat 12; Remove the growth substrate; Form a protective layer 15 on luminous lamination 13; Carry out thinning support substrate 10 again; Last cut crystal is to form naked core.In addition, reflector 14 also can be formed between luminous lamination 13 and the tack coat 12; After reflector 14 is formed on the luminous lamination 13 at this moment, connect reflector 14 and anti-deformation layers 11 by tack coat 12.After tack coat 12 can be formed on anti-deformation layer 11 and the luminous lamination 13 respectively, rejoin anti-deformation layer 11 and luminous lamination 13.Anti-deformation layer 11 is deposited on the support substrate 10 by chemical vapour deposition technique (CVD), Metalorganic chemical vapor deposition method (MOCVD), vapour phase epitaxy method (VPE), liquid phase epitaxial method (LPE), molecular beam epitaxy (MBE), plasma chemical vapor deposition (PECVD) or other similar fashion; Its material is including but not limited to aluminium oxide (Al xO y), silicon nitride (SiN x), silica (SiO x), titanium oxide (TiO x), the combination of gallium nitride (GaN) or above-mentioned material.The method of thinning support substrate 10 is including but not limited to chemico-mechanical polishing (chemical mechanical polishing; CMP) method or etching.
Only the foregoing description only is illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any those skilled in the art all may be under the situation of know-why of the present invention and spirit, and the foregoing description is made amendment and changed.Therefore the scope of the present invention claim as described is listed.

Claims (17)

1. method that is used to make a wafer illumination structure comprises:
One support substrate is provided;
Form an anti-deformation layer on this support substrate;
One growth substrate is provided;
Form luminous being stacked on this growth substrate;
Form a tack coat between this anti-deformation layer and this luminous lamination;
Carry out a joint technology, engage this luminous lamination and this anti-deformation layer by this tack coat; And
This support substrate of thinning, wherein this wafer illumination structure produces 10 times of a thickness that a deformation highly is this wafer illumination structure to the maximum after thinning, wherein this deformation highly is the difference in height of an intersection of the lower surface of this wafer illumination structure and a side to a lower surface geometric center point, and this thickness is the difference in height of this lower surface geometric center point of this wafer illumination structure to a upper surface geometric center point of this wafer illumination structure.
2. the method for claim 1, wherein the material of this anti-deformation layer is selected self-alumina (AlxOy), silicon nitride (SiNx), silica (SiOx), titanium oxide (TiOx), gallium nitride (GaN), and the group that combination constituted of above-mentioned material.
3. the method for claim 1 wherein forms the method for this anti-deformation layer on this substrate and selects from chemical vapour deposition technique, Metalorganic chemical vapor deposition method, group that vapour phase epitaxy method, liquid phase epitaxial method, molecular beam epitaxy, plasma chemical vapor deposition constituted.
4. the method for claim 1, wherein this anti-deformation layer comprises the deposition defective of microstructure or molecule.
5. the method for claim 1, wherein the thickness of this anti-deformation layer is between 2 microns to 10 microns.
6. the method for claim 1, wherein the method for this support substrate of thinning comprises chemical mechanical polishing method or etching.
7. the method for claim 1, wherein the thickness after this support substrate thinning is less than 40 microns.
8. the method for claim 1 also comprises and forms a reflector between this luminous lamination and this tack coat maybe between this anti-deformation layer and this tack coat.
9. the method for claim 1 engages after this anti-deformation layer and this luminous lamination, also comprises to remove this growth substrate.
10. the method for claim 1 after this support substrate of thinning, also comprises this wafer illumination structure of cutting to form a plurality of naked core ray structures.
11. a wafer illumination structure comprises:
One support substrate;
One anti-deformation layer is positioned on this support substrate;
One tack coat is positioned on this anti-deformation layer; And
One luminous lamination is positioned on this anti-deformation layer, and wherein this tack coat connects this anti-deformation layer and this luminous lamination;
Wherein the deformation that produces through a thinning technology of this wafer illumination structure highly is no more than 10 times an of thickness of this wafer illumination structure, wherein this deformation highly is the difference in height of an intersection of the lower surface of this wafer illumination structure and side to a lower surface geometric center point of ray structure, and this thickness is the difference in height of this lower surface geometric center point of this wafer illumination structure to a upper surface geometric center point of ray structure.
12. wafer illumination structure as claimed in claim 11, wherein the thickness after this support substrate thinning is less than 40 microns.
13. wafer illumination structure as claimed in claim 11, wherein the material of this anti-deformation layer is selected free oxidation aluminium (AlxOy), silicon nitride (SiNx), silica (SiOx), titanium oxide (TiOx), gallium nitride (GaN), and the group that combination constituted of above-mentioned material.
14. wafer illumination structure as claimed in claim 11, wherein the thickness of this anti-deformation layer is between 2 microns to 10 microns.
15. wafer illumination structure as claimed in claim 14, wherein this anti-deformation layer makes this deformation behind this substrate of thinning highly be 5 times of thickness of this wafer illumination structure to the maximum.
16. wafer illumination structure as claimed in claim 11, wherein the material of this tack coat is selected free polyimides, benzocyclobutene, cross the fluorine cyclobutane, epoxy resin, other organic binding materials, indium, tin, aluminium, gold, platinum, zinc, silver, titanium, plumbous, palladium, germanium, copper, nickel, tin gold (AuSn), patina indium (InAg), aurification indium (InAu), beryllium gold (AuBe), germanium gold (AuGe), zinc impregnation gold (AuZn), tin lead (PbSn), indium palladium (PdIn), tin gold (AuSn), patina indium (InAg), aurification indium (InAu), and the group that combination constituted of above-mentioned material.
17. wafer illumination structure as claimed in claim 11 also comprises a reflector, between this luminous lamination and this tack coat or between this anti-deformation layer and this luminous lamination.
CN2008101449949A 2008-08-18 2008-08-18 Wafer illumination structure and manufacturing method thereof Active CN101656281B (en)

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CN101866029B (en) * 2010-06-09 2011-09-21 宁波激智新材料科技有限公司 Deformation-resistant optics reflecting film, liquid crystal display device and LED lighting equipment
JP2012227479A (en) * 2011-04-22 2012-11-15 Sharp Corp Nitride semiconductor element formation wafer and method of manufacturing the same, and nitride semiconductor element and method of manufacturing the same
US9508894B2 (en) * 2013-07-29 2016-11-29 Epistar Corporation Method of selectively transferring semiconductor device

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