CN101640189B - Thin-film transistor array substrate preparation method - Google Patents

Thin-film transistor array substrate preparation method Download PDF

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Publication number
CN101640189B
CN101640189B CN2008101868270A CN200810186827A CN101640189B CN 101640189 B CN101640189 B CN 101640189B CN 2008101868270 A CN2008101868270 A CN 2008101868270A CN 200810186827 A CN200810186827 A CN 200810186827A CN 101640189 B CN101640189 B CN 101640189B
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source
drain
those
polysilicon island
layer
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CN101640189A (en
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萧富元
温佑良
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Chunghwa Picture Tubes Ltd
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Chunghwa Picture Tubes Ltd
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Abstract

A thin-film transistor array substrate preparation method comprises the following steps: using a first halftoning photomask to form a first patterned photoresist layer on polysilicon layer, adopting the first patterned photoresist layer as mask to remove partial polysilicon layer and form a plurality of first polysilicon island-shaped substances, a plurality of second island-shaped substances and a plurality of third island-shaped substances, removing the first patterned photoresist layer above the second island-shaped substances and the third island-shaped substances, performing first groove doping process to inject ions in the second island-shaped substances and the third island-shaped substances and finally removing the first patterned photoresist layer; the first polysilicon island-shaped substances and the second island-shaped substances are located on a periphery region and the third island-shaped substances are located on a array region.

Description

The manufacture method of thin-film transistor array base-plate
The application be the applicant on August 25th, 2006 submit to, application number for " 200610125671.6 ", denomination of invention divides an application for the application for a patent for invention of " manufacture method of thin-film transistor array base-plate ".
Technical field
The present invention is relevant for a kind of manufacture method of active component array base board, and is particularly to a kind of manufacture method of thin-film transistor array base-plate.
Background technology
Because low-temperature polysilicon film transistor (low temperature poly-silicon thin filmtransistor, LTPS TFT) has overcome the problem of electron mobility, and, complementary (complementary) more is provided circuit engineering.Therefore, low-temperature polysilicon film transistor all has great advantage on element downsizing, panel aperture opening ratio, picture quality and resolution.In addition, the design of low-temperature polysilicon film transistor at present not only has drive circuit is integrated in characteristic on glass, and the lifting of its level of integrated system more makes panel have the characteristic of narrow frameization (narrow frame size) and high image quality simultaneously.Moreover low-temperature polysilicon film transistor also has advantages such as low power consumption, low electromagnetic interference, and therefore, the development of its technology and improvement are subjected to paying attention to very widely.The manufacture method of below putting up with two kinds of existing low-temperature polysilicon film transistors describes.
Figure 1A to Fig. 1 E is existing a kind of low-temperature polysilicon film transistor array base palte manufacturing process schematic diagram.Please refer to shown in Figure 1A, the manufacture method of existing low-temperature polysilicon film transistor array base palte comprises the following steps.At first, provide a substrate 110, and substrate 110 have a surrounding zone 110a and an array district 110b.Then, on substrate 110, form a resilient coating (buffer layer) 120.Then, on resilient coating 120, form a plurality of first polysilicon island thing (poly-silicon island) 130a, a plurality of second polysilicon island thing 130b and a plurality of the 3rd polysilicon island thing 130c.Wherein, first and second polysilicon island thing 130a, 130b are disposed on the 110a of surrounding zone, and the 3rd polysilicon island thing 130c is disposed on the array area 110b.On substrate 110, form patterning photoresist layer 210, to cover the first polysilicon island thing 130a.Then, be that mask carries out a channel doping technology (channel doping process) S110 to the second and the 3rd polysilicon island thing 130b, 130c with patterning photoresist layer 210.Then, remove patterning photoresist layer 210.
Please refer to shown in Figure 1B, on substrate 110, form patterning photoresist layer 220b, to cover the part zone of the first polysilicon island thing 130a and the second and the 3rd polysilicon island thing 130b, 130c.Then, with patterning photoresist layer 220b is that mask carries out one second ion implantation technology (ion implantation process) S120b to these the second and the 3rd polysilicon island things 130b, 130c, to form one second source/drain 132b and form one the 3rd source/drain 132c in each second polysilicon island thing 130b in each the 3rd polysilicon island thing 130c.In addition, between each second source/drain 132b, promptly be one second channel region 134b, and between each the 3rd source/drain 132c, promptly be a triple channel district 134c.Then, remove patterning photoresist layer 220b.
Please refer to shown in Fig. 1 C, on resilient coating 120, form a gate insulation layer 140, and cover these first, second and the 3rd polysilicon island thing 130a, 130b, 130c.Then, on gate insulation layer 140, form a plurality of first grid 150a, a plurality of second grid 150b, a plurality of the 3rd grid 150c and a plurality of capacitance electrode 150d.Then, these the second and the 3rd polysilicon island things 130b, 130c are carried out a lightly doped drain ion implantation technology S130, to form a plurality of second lightly doped drain 136b and a plurality of the 3rd lightly doped drain 136c.
Please refer to shown in Fig. 1 D, on substrate 110, form patterning photoresist layer 220a, to cover the second and the 3rd polysilicon island thing 130b, 130c.Then, 130a carries out one first ion implantation technology S120a to these first polysilicon island things, to form a plurality of first source/drain 132a.In addition, between each first source/drain 132a, promptly be one first channel region 134a.Then, remove patterning photoresist layer 220a.
Please refer to shown in Fig. 1 E, on gate insulation layer 140, form one first patterning protective layer 160, and expose the part of part and each the 3rd source/drain 132c of part, each second source/drain 132b of each first source/drain 132a.Then, on the first patterning protective layer 160, form a plurality of first source/drain conductor layer 170a, a plurality of second source/drain conductor layer 170b and a plurality of the 3rd source/drain conductor layer 170c.Wherein, each the first source/drain conductor layer 170a and the first source/drain 132a electrically connect, and each the second source/drain conductor layer 170b and the second source/drain 132a electrically connect.In addition, each the 3rd source/drain conductor layer 170c and the 3rd source/drain 132c electrically connect.
Then, on the first patterning protective layer 160, form one second patterning protective layer 180, and the second patterning protective layer 180 exposes the part of the 3rd source/drain conductor layer 170c.Then, on the second patterning protective layer 180, form a pixel electrode (pixel electrode) 190, and pixel electrode 190 electrically connects with corresponding the 3rd source/drain conductor layer 170c.So far then roughly finish the manufacturing process of existing low-temperature polysilicon film transistor array base palte 100.The manufacture method of below putting up with another kind of existing low-temperature polysilicon film transistor array base palte describes.
Fig. 2 A to Fig. 2 E is the manufacturing process schematic diagram of another existing low-temperature polysilicon film transistor array base palte.Please refer to shown in Fig. 2 A to Fig. 2 B, the content shown in Fig. 2 A to Fig. 2 B is identical with the content shown in Figure 1A to Figure 1B haply.Briefly, on substrate 110, finish resilient coating 120, the first polysilicon island thing 130a, the second polysilicon island thing 130b, the 3rd polysilicon island thing 130c, channel doping technology S110 and the second ion implantation technology S120b in regular turn.
Please refer to shown in Fig. 2 C, on resilient coating 120, form gate insulation layer 140, and cover first, second and the 3rd polysilicon island thing 130a, 130b, 130c.Then, on gate insulation layer 140, form a patterned conductor material layer 150 and a plurality of first grid 150a.This patterned conductor material layer 150 covers the second polysilicon island thing 130b and the 3rd polysilicon island thing 130c.Then, be that mask carries out one first ion implantation technology S120a to the first polysilicon island thing 130a with first grid 150a, to form a plurality of first source/drain 132a.In addition, between each first source/drain 132a, promptly be one first channel region 134a.
Please refer to shown in Fig. 2 D, carry out Patternized technique to form a plurality of second grid 150b, a plurality of the 3rd grid 150c and a plurality of capacitance electrode 150d for patterned metal layer 150.Then, carry out a lightly doped drain ion implantation technology S130 to form a plurality of second lightly doped drain 136b and a plurality of the 3rd lightly doped drain 136c.
Please refer to shown in Fig. 2 E, the content of Fig. 2 E is similar to the content of Fig. 1 E haply.Briefly; after lightly doped drain ion implantation technology S130 is carried out in formation; form the first patterning protective layer 160, the first source/drain conductor layer 170a, the second source/drain conductor layer 170b, the 3rd source/drain conductor layer 170c, the second patterning protective layer 180 and pixel electrode 190 in regular turn, to finish the manufacturing process of this existing low-temperature polysilicon film transistor array base palte 100.
Because drive circuit is integrated on the glass substrate, so the low-temperature polysilicon film transistor array base palte has advantages such as aperture opening ratio height and narrow frameization.But compared to 5 road photomask technologies of general amorphous silicon film transistor (amorphoussilicon TFT, a-Si TFT) array base palte, 9 road photomask technologies of low-temperature polysilicon film transistor array base palte seem very loaded down with trivial details.Therefore, the technology of existing low-temperature polysilicon film transistor array base palte not only panel size is difficult for promoting, and yield also comparatively is not easy control, and then causes the manufacturing cost problem of higher.
Summary of the invention
The manufacture method that the purpose of this invention is to provide a kind of thin-film transistor array base-plate is to reduce the photomask number.
For reaching above-mentioned or other purposes, the present invention also proposes a kind of manufacture method of thin-film transistor array base-plate, and it comprises the following steps.At first, on a substrate, form a polysilicon layer, and substrate have a surrounding zone and an array district.Then, utilize one the first half mode photomask on polysilicon layer, to form one first patterning photoresist layer.Then, be that mask removes the part polysilicon layer with the first patterning photoresist layer, to form a plurality of first polysilicon island things, a plurality of second polysilicon island thing and a plurality of the 3rd polysilicon island thing.Wherein, these first polysilicon island things and these second polysilicon island things are positioned on the surrounding zone, and these the 3rd polysilicon island things are positioned on the array area.Then, remove the first patterning photoresist layer of these second polysilicon island things and these the 3rd polysilicon island things top.Then, carry out a channel doping technology, in these second polysilicon island things and these the 3rd polysilicon island things, to inject ion.Then, remove the first patterning photoresist layer.Carry out one second ion implantation technology, in each second polysilicon island thing, to form one second source/drain and in each the 3rd polysilicon island thing, to form one the 3rd source/drain.Wherein, promptly be one second channel region between second source/drain, and promptly be a triple channel district between the 3rd source/drain.Then, on substrate, form a gate insulation layer, to cover these first polysilicon island things, these second polysilicon island things and these the 3rd polysilicon island things.Then, on gate insulation layer, form a plurality of first grids, a plurality of second grid and a plurality of the 3rd grid.Wherein, these first grids, these second grids and these the 3rd grids lay respectively at these first polysilicon island things, these second polysilicon island things and these the 3rd polysilicon island things top.Then, carrying out one first ion implantation technology, with formation one first source/drain in each first polysilicon island thing, and promptly is one first channel region between first source/drain.On substrate, form one first patterning protective layer, to cover these first grids, these second grids and these the 3rd grids.Then, be that mask removes the part gate insulation layer with the first patterning protective layer, with the part of the part that exposes each first source/drain, each second source/drain and the part of each the 3rd source/drain.Then, on the first patterning protective layer, form a plurality of first source/drain conductor layers, a plurality of second source/drain conductor layer and a plurality of the 3rd source/drain conductor layer.Wherein, these first source/drain conductor layers electrically connect with these first source/drains respectively, and these second source/drain conductor layers electrically connect with these second source/drains respectively, and these the 3rd source/drain conductor layers electrically connect with these the 3rd source/drains respectively.Then, on the first patterning protective layer, form one second patterning protective layer.Wherein, the second patterning protective layer exposes the part of each the 3rd source/drain conductor layer.Then, on the second patterning protective layer, form a plurality of pixel electrodes.Wherein, each pixel electrode and corresponding the 3rd source/drain conductor layer electrically connect.
In another embodiment of the present invention, above-mentioned after forming these first grids, these second grids and these the 3rd grids, also comprise and carry out a lightly doped drain ion implantation technology, with formation one second lightly doped drain between each second source/drain and second channel region, and between each the 3rd source/drain and triple channel district, form one the 3rd lightly doped drain.
For reaching above-mentioned or other purposes, the present invention proposes a kind of manufacture method of thin-film transistor array base-plate again, and it comprises the following steps.At first, on a substrate, form a polysilicon layer, and substrate have a surrounding zone and an array district.Utilize one the first half mode photomask on polysilicon layer, to form one first patterning photoresist layer.Then, be that mask removes the part polysilicon layer with the first patterning photoresist layer, to form a plurality of first polysilicon island things, a plurality of second polysilicon island thing and a plurality of the 3rd polysilicon island thing.Wherein, these first polysilicon island things and these second polysilicon island things are positioned on the surrounding zone, and these the 3rd polysilicon island things are positioned on the array area.Then, remove the first patterning photoresist layer of these second polysilicon island things and these the 3rd polysilicon island things top.Then, carry out a channel doping technology, in these second polysilicon island things and these the 3rd polysilicon island things, to inject ion.Then, remove the first patterning photoresist layer.Then, carry out one second ion implantation technology, in each second polysilicon island thing, to form one second source/drain and in each the 3rd polysilicon island thing, to form one the 3rd source/drain.Wherein, promptly be one second channel region between second source/drain, and promptly be a triple channel district between the 3rd source/drain.On substrate, form a gate insulation layer, to cover these first polysilicon island things, these second polysilicon island things and these the 3rd polysilicon island things.Then, on gate insulation layer, form a patterned conductor material layer.Wherein, the patterned conductor material layer has a plurality of first grids, is positioned on the gate insulation layer of these first polysilicon island thing tops.Then, be that mask carries out one first ion implantation technology with the patterned conductor material layer, in each first polysilicon island thing, to form one first source/drain.Wherein promptly one first channel region between first source/drain.Then, remove partially patterned conductor material layer, exposing the subregion of gate insulation layer of these second polysilicon island things and these the 3rd polysilicon island things top, and form a plurality of second grids and a plurality of the 3rd grid.Then, on gate insulation layer, form one first patterning protective layer, to cover these first grids, these second grids and these the 3rd grids.Wherein, the first patterning protective layer exposes the subregion of the gate insulation layer of these first polysilicon island things, these second polysilicon island things and these the 3rd polysilicon island things top.Then, be that mask removes the part gate insulation layer with the first patterning protective layer, with the part of the part that exposes each first source/drain, each second source/drain and the part of each the 3rd source/drain.Then, on the first patterning protective layer, form a plurality of first source/drain conductor layers, a plurality of second source/drain conductor layer and a plurality of the 3rd source/drain conductor layer.Wherein, these first source/drain conductor layers electrically connect with these first source/drains respectively, and these second source/drain conductor layers electrically connect with these second source/drains respectively, and these the 3rd source/drain conductor layers electrically connect with these the 3rd source/drains respectively.Then, on the first patterning protective layer, form one second patterning protective layer.Wherein, the second patterning protective layer exposes the part of each the 3rd source/drain conductor layer.Then, on the second patterning protective layer, form a plurality of pixel electrodes.Wherein, each pixel electrode and corresponding the 3rd source/drain conductor layer electrically connect.
In another embodiment of the present invention, above-mentioned after forming these first grids, these second grids and these the 3rd grids, also comprise and carry out a lightly doped drain ion implantation technology, with formation one second lightly doped drain between each second source/drain and second channel region, and between each the 3rd source/drain and triple channel district, form one the 3rd lightly doped drain.
The present invention reduces on the low-temperature polysilicon film transistor technology needed photomask quantity simplifying its technology because of adopting half mode photomask, and then reaches and promote yield and the purpose that increases panel size.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Figure 1A to Fig. 1 E is existing a kind of low-temperature polysilicon film transistor manufacturing process schematic diagram.
Fig. 2 A to Fig. 2 E is another manufacturing process schematic diagram of existing a kind of low-temperature polysilicon film transistor.
Fig. 3 A to Fig. 3 G is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of first embodiment of the invention.
Fig. 4 A to Fig. 4 F is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of second embodiment of the invention.
Fig. 5 A to Fig. 5 F is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of third embodiment of the invention.
Fig. 6 A to Fig. 6 H is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of fourth embodiment of the invention.
Fig. 7 A to Fig. 7 G is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of fifth embodiment of the invention.
Fig. 8 A to Fig. 8 G is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of sixth embodiment of the invention.
Fig. 9 A to Fig. 9 F is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of seventh embodiment of the invention.
Figure 10 A to Figure 10 E is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of eighth embodiment of the invention.
Figure 11 A to Figure 11 G is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of ninth embodiment of the invention.
Figure 12 A to Figure 12 F is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of tenth embodiment of the invention.
Embodiment
First embodiment
Fig. 3 A to Fig. 3 G is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of first embodiment of the invention.Please refer to shown in Fig. 3 A, at first, provide a substrate 310, and substrate 310 has a surrounding zone 310a and an array district 310b.In addition, substrate 310 can be glass substrate, quartz base plate or plastic substrate.Then, on substrate 310, form a polysilicon layer 330.
More specifically, the step that forms polysilicon layer 330 for example is to form an amorphous silicon layer (not shown) earlier on substrate 310, and the mode that forms amorphous silicon layer for example is chemical vapor deposition (chemical vapordeposition, CVD) technology or ion growth form chemical vapor deposition (plasma enhanced CVD, PECVD) technology.Then, carry out a laser annealing (laser annealing) technology for this amorphous silicon layer, so that amorphous silicon layer is transformed into polysilicon layer 330.Laser annealing technique for example be excimer laser (excimer laserannealing, ELR), solid-state laser (solid-state laser) or diode excitation formula solid-state laser (diodepumped solid state laser, DPSS) technology.And, before amorphous silicon layer is carried out laser annealing technique, more can carry out a dehydrogenation (dehydrogenation) technology earlier, to reduce the hydrogen content in the amorphous silicon layer.When dehydrogenation technology can be avoided carrying out laser annealing technique, the interior contained hydrogen of amorphous silicon layer was heated and produces hydrogen quick-fried (hydrogen exploration) phenomenon.
In addition, before forming polysilicon layer 330, can be prior on the substrate 310, (low pressure chemical vapor deposition, LPCVD) technology or ion growth form are strengthened chemical vapor deposition process and are formed a resilient coating 320 with low-pressure chemical vapor deposition.Resilient coating 320 can stop that substrate 310 contained diffusion of impurities enter in the polysilicon layer 330.In addition, resilient coating 320 can be the mono-layer oxidized silicon or the double-decker of silica/silicon nitride.
Please continue 3A, after forming polysilicon layer 330, utilize one the first half mode photomask 410a on polysilicon layer 330, to form one first patterning photoresist layer 420a with reference to figure.More specifically, the first half mode photomask 410a comprise that a transparency carrier 412a, a metal level 414a and half see through film 416a, and the wherein semi-transparent film 416a that crosses is disposed on the transparency carrier 412a, and metal level 414a is disposed at semi-transparent the mistake on the film 416a.The semi-transparent light transmittance of crossing the light transmittance of film 416a greater than metal level 414a, therefore the thickness of the first patterning photoresist layer 420a is also just inconsistent.Though the first half mode photomask 410a utilize metal level 414a and the semi-transparent film 416a of mistake and the first patterning photoresist layer 420a that forms different-thickness, yet GTG photomask (gray tone mask) or other photomasks with two or more light transmittances also can replace the first half mode photomask 410a and form the first patterning photoresist layer 420a.In addition, the GTG photomask is to adopt slit to change light transmittance.
Please refer to shown in Fig. 3 B, is that mask removes part polysilicon layer 330 with the first patterning photoresist layer 420a, to form a plurality of first polysilicon island thing 330a, a plurality of second polysilicon island thing 330b and a plurality of the 3rd polysilicon island thing 330c.Wherein, the first polysilicon island thing 330a and the second polysilicon island thing 330b are positioned on the 310a of surrounding zone, and the 3rd polysilicon island thing 330c is positioned on the array area 310b.
Please refer to shown in Fig. 3 C, remove the first patterning photoresist layer 420a of the second polysilicon island thing 330b and the 3rd polysilicon island thing 330c top.Then, carry out a channel doping technology S310, in the second polysilicon island thing 330b and the 3rd polysilicon island thing 330c, to inject ion.In addition, channel doping technology S310 is in order to adjust the electrical character of the second polysilicon island thing 330b and the second polysilicon island thing 330c.Then, remove the remaining first patterning photoresist layer 420a.
Please refer to shown in Fig. 3 D, on substrate 310, form a patterning photoresist layer 520b, and patterning photoresist layer 520b covers the part zone of the first polysilicon island thing 330a and first and second polysilicon island thing 330b, 330c.Then, carry out one second ion implantation technology S320b,, and in each the 3rd polysilicon island thing 330c, form one the 3rd source/drain 332c with formation one second source/drain 332b in each second polysilicon island thing 330b.Wherein, promptly be one second channel region 334b between the second source/drain 332b, and promptly be a triple channel district 334c between the 3rd source/drain 332c.Come again, remove patterning photoresist layer 520b.
Please refer to shown in Fig. 3 E, on substrate 310, form a gate insulation layer 340, to cover first, second and the 3rd polysilicon island thing 330a, 330b, 330c.Then, on gate insulation layer 340, form a plurality of first grid 350a, a plurality of second grid 350b, a plurality of the 3rd grid 350c and a plurality of capacitance electrode 350d.Wherein, each first polysilicon island thing 330a top has a first grid 350a respectively, and each second polysilicon island thing 330b top has a second grid 350b respectively, and each the 3rd polysilicon island thing 330c top has two the 3rd grid 350c and a capacitance electrode 350d respectively.But the present invention is not limited in the design of two the 3rd grid 350c, and the present invention also is applicable to the design of single the 3rd grid 350c.More specifically, the mode that forms first, second, third grid and capacitance electrode 350a, 350b, 350c, 350d can be that earlier (physics vapor deposition, PVD) technology forms a conductor material layer (not shown) with sputter (sputtering) technology or physical vapor deposition on gate insulation layer 340.Wherein, the material of conductor material layer can be chromium (Cr) or other metal materials.Then, again this conductor material layer is carried out little shadow (photolithogrophy) technology and etching (etching) technology, to form first, second, third grid and capacitance electrode 350a, 350b, 350c, 350d.
In addition, after forming first, second, third grid and capacitance electrode 350a, 350b, 350c, 350d, also can carry out a lightly doped drain ion implantation technology S330, with formation one second lightly doped drain 336b between each the second source/drain 332b and the second channel region 334b, and between each the 3rd source/drain 332c and triple channel district 334c, form one the 3rd lightly doped drain 336c.The second and the 3rd shallow doped- drain 336b, 336c can improve N raceway groove NMOS N-channel MOS N (negtive channel metal oxidesemiconductor, NMOS) hot carrier's effect in (hot carrier effect).In addition, the ion that light dope ion implantation technology S330 is injected can be a n type alloy, and wherein n type alloy can be a phosphonium ion.
Please refer to shown in Fig. 3 F, on substrate 310, form a patterning photoresist layer 520a, and patterning photoresist layer 520a covers the second and the 3rd polysilicon island thing 330b, 330c.Then, carrying out one first ion implantation technology S320a, with formation one first source/drain 332a in each first polysilicon island thing 330a, and promptly is one first channel region 334a between the first source/drain 332a.Come again, remove patterning photoresist layer 520a.
More specifically, the ion that the first ion implantation technology S320a is injected can be a p type alloy, and p type alloy can be the boron ion.In addition, the ion that the second ion implantation technology S320b is injected can be a n type alloy, and n type alloy can be a phosphonium ion.
Please refer to shown in Fig. 3 G, on substrate 310, form one first patterning protective layer 360, to cover first grid 350a, second grid 350b, the 3rd grid 350c and capacitance electrode 350d.More specifically, the mode that forms the first patterning protective layer 360 can be to form a protective layer (not shown) with chemical vapor deposition process on substrate 310 earlier, and the material of this protective layer for example is silica, silicon nitride or other insulating material.Then, carry out lithography process and etching technics, to form the first patterning protective layer 360 for this protective layer.
Then, be that mask removes part gate insulation layer 340 with the first patterning protective layer 360, with the part of the part that exposes each first source/drain 332a, each second source/drain 332b and the part of 2 the 3rd source/drain 332c wherein.Then, on the first patterning protective layer 360, form a plurality of first source/drain conductor layer 370a, a plurality of second source/drain conductor layer 370b and a plurality of the 3rd source/drain conductor layer 370c.Wherein, each first source/drain conductor layer 370a electrically connects with each first source/drain 332a respectively, and each second source/drain conductor layer 370b electrically connects with each second source/drain 332b respectively, and each the 3rd source/drain conductor layer 370c electrically connects with each the 3rd source/drain 332c respectively.More specifically, the mode that forms first, second and the 3rd source/ drain conductor layer 370a, 370b, 370c can be to form source conductor material layer (not shown) with sputtering process or physical vapor deposition process on the first patterning protective layer 360 earlier.Wherein, the material of source/drain conductor material layer can be chromium or other metal materials.Then, again this source/drain conductor material layer is carried out lithography process and etching technics, to form first, second and the 3rd source/ drain conductor layer 370a, 370b, 370c.
Then, on the first patterning protective layer 360, form one second patterning protective layer 380.Wherein, the second patterning protective layer 380 exposes the wherein part of one the 3rd source/drain conductor layer 370c.In addition, the generation type of the second patterning protective layer 380 is identical with the first patterning protective layer 360 haply, repeats no more in this.
Then, on the second patterning protective layer 380, form a plurality of pixel electrodes 390.Wherein, pixel electrode 390 electrically connects with corresponding the 3rd source/drain conductor layer 370c.In addition, the mode of formation pixel electrode 390 can be to form a pixel electrode material layer (not shown) with sputtering process or physical vapor deposition process on the second patterning protective layer 380 earlier.Wherein, the material of pixel electrode material layer can be tin indium oxide (IndiumTin Oxide, ITO) or other transparency conductive electrode materials.Then, again this pixel electrode material layer is carried out lithography process and etching technics, to form pixel electrode 390.So far then roughly finish the manufacturing process of the low-temperature polysilicon film transistor array base palte 300 of first embodiment of the invention.
Because present embodiment is to utilize the first half formed first patterning photoresist layers of mode photomask, to form first, second and the 3rd polysilicon island thing.Then, remove the first patterning photoresist layer of the second polysilicon island thing and the 3rd polysilicon island thing top, to proceed channel doping technology.Briefly, present embodiment is to utilize the first half mode photomasks to replace the twice photomask of prior art, so the present invention can be in order to the usage quantity that reduces photomask to simplify technology, to reduce production costs.Yet the photomask that GTG photomask or other have two or more light transmittances also can replace the first half mode photomasks and be applied in the present embodiment.
Second embodiment
Fig. 4 A to Fig. 4 E is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of second embodiment of the invention.Please refer to shown in Fig. 4 A, at first, provide a substrate 310, and substrate 310 has a surrounding zone 310a and an array district 310b, and on substrate 310, form a plurality of first polysilicon island thing 330a, a plurality of second polysilicon island thing 330b and a plurality of the 3rd polysilicon island thing 330c.Wherein, the first polysilicon island thing 330a and the second polysilicon island thing 330b are positioned on the 310a of surrounding zone, and the 3rd polysilicon island thing 330c is positioned on the array area 310b.Then, utilize one the second half mode photomask 410b on first, second and the 3rd polysilicon island thing 330a, 330b, 330c, to form one second patterning photoresist layer 420b, and the second patterning photoresist layer 420b cover the part zone of the first polysilicon island thing 330a and the second and the 3rd polysilicon island thing 330b, 330c.Wherein, the composition of the second half mode photomask 410b, material and function are identical with the first half mode photomask 410a, repeat no more in this.
More specifically, the step that forms first, second and the 3rd polysilicon island thing 330a, 330b, 330c for example is to form a polysilicon layer (not shown) earlier on substrate 310.Then, this polysilicon layer is carried out lithography process and etching technics, on substrate 310, to form first, second and the 3rd polysilicon island thing 330a, 330b, 330c.Identical, form before the polysilicon layer, can be prior to forming a resilient coating 320 on the substrate 310.It is similar to first embodiment to mode, material and the function thereof of resilient coating to form polysilicon layer, repeats no more in this.
Please refer to shown in Fig. 4 B, carry out one second ion implantation technology S320b,, and in each the 3rd polysilicon island thing 330c, form one the 3rd source/drain 332c with formation one second source/drain 332b in each second polysilicon island thing 330b.Wherein, promptly be one second channel region 334b between the second source/drain 332b, and promptly be a triple channel district 334c between the 3rd source/drain 332c.
Please refer to shown in Fig. 4 C, remove the second patterning photoresist layer 420b of the second and the 3rd polysilicon island thing 330b, 330c top.Then, carry out a channel doping technology S310, in the second polysilicon island thing 330b and the 3rd polysilicon island thing 330c, to inject ion.Then, remove the second patterning photoresist layer 420b.
Please refer to shown in Fig. 4 D to Fig. 4 F, the step of Fig. 4 D to Fig. 4 F is similar to Fig. 3 E to Fig. 3 G among first embodiment haply.It comprises and forms gate insulation layer 340, first grid 350a, second grid 350b, the 3rd grid 350c, capacitance electrode 350d, the first source/drain 332a, the first channel region 334a, the first patterning protective layer 360, the first source/drain conductor layer 370a, the second source/drain conductor layer 370b, the 3rd source/drain conductor layer 370c, the second patterning protective layer 380 and pixel electrode 390 in regular turn, with the manufacturing process of the thin-film transistor array base-plate 300 of finishing this embodiment.And the material of above-mentioned each member is identical with first embodiment haply with generation type, repeats no more in this.
Please refer to shown in Fig. 4 D, identical, the present invention is not limited in the design of two the 3rd grid 350c, and the present invention also is applicable to the design of single the 3rd grid 350c.In addition, after forming first, second, third grid and capacitance electrode 350a, 350b, 350c, 350d, also can comprise and carry out a lightly doped drain ion implantation technology S330, with formation one second lightly doped drain 336b between each the second source/drain 332b and the second channel region 334b, and between each the 3rd source/drain 332c and triple channel district 334c, form one the 3rd lightly doped drain 336c.
Present embodiment utilizes the second half formed second patterning photoresist layers of mode photomask, to carry out second ion implantation technology.Then, remove the second patterning photoresist layer of the second polysilicon island thing and the 3rd polysilicon island thing top, to proceed channel doping technology.Briefly, present embodiment is to utilize the second half mode photomasks to replace the twice photomask of prior art, so the present invention can be in order to the usage quantity that reduces photomask to simplify technology, to reduce production costs.Yet the photomask that GTG photomask or other have two or more light transmittances also can replace the second half mode photomasks and be applied in the present embodiment.
The 3rd embodiment
Fig. 5 A to Fig. 5 F is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of third embodiment of the invention.Please refer to shown in Fig. 5 A, at first, provide a substrate 310, and substrate 310 has a surrounding zone 310a and an array district 310b, and on substrate 310, form a plurality of first polysilicon island thing 330a, a plurality of second polysilicon island thing 330b and a plurality of the 3rd polysilicon island thing 330c.Wherein, the first polysilicon island thing 330a and the second polysilicon island thing 330b are positioned on the 310a of surrounding zone, and the 3rd polysilicon island thing 330c is positioned on the array area 310b.Identical, can be prior to forming a resilient coating 320 on the substrate 310, just form first, second and the 3rd polysilicon island thing 330a, 330b, 330c then.And form resilient coating 320, first, second mode and material thereof to the 3rd polysilicon island thing 330a, 330b, 330c is similar to second embodiment, repeat no more in this.Then, on substrate 310, form a patterning photoresist layer 510, and patterning photoresist layer 510 covers the first polysilicon island thing 330a.Then, the second and the 3rd polysilicon island thing 330b, 330c are carried out a channel doping technology S310.Come again, remove patterning photoresist layer 510.
Please refer to shown in Fig. 5 B, on substrate 310, form a patterning photoresist layer 520b, and patterning photoresist layer 520b covers the part zone of the first polysilicon island thing 330a and first and second polysilicon island thing 330b, 330c.Then, carry out one second ion implantation technology S320b,, and in each the 3rd polysilicon island thing 330c, form one the 3rd source/drain 332c with formation one second source/drain 332b in each second polysilicon island thing 330b.Wherein, promptly be one second channel region 334b between the second source/drain 332b, and promptly be a triple channel district 334c between the 3rd source/drain 332c.Come again, remove patterning photoresist layer 520b.
Please refer to shown in Fig. 5 C, on substrate 310, form a gate insulation layer 340, to cover first, second and the 3rd polysilicon island thing 330a, 330b, 330c.Then, on gate insulation layer 340, form a plurality of first grid 350a, a plurality of second grid 350b, a plurality of the 3rd grid 350c and a plurality of capacitance electrode 350d.Wherein, each first polysilicon island thing 330a top, have a first grid 350a respectively, and each second polysilicon island thing 330b top has a second grid 350b respectively, and each the 3rd polysilicon island thing 330c top have two the 3rd grid 350c and a capacitance electrode 350d respectively.Identical, the present invention is not limited in the design of two the 3rd grid 350c, and the present invention also is applicable to the design of single the 3rd grid 350c.And it is similar to first embodiment to mode and the material thereof of capacitance electrode 350d to form gate insulation layer 340, first grid 350a, second grid 350b, the 3rd grid 350c, repeats no more in this.
Please continue with reference to shown in the figure 5C, after forming first, second, third grid and capacitance electrode 350a, 350b, 350c, 350d, also can comprise and carry out a lightly doped drain ion implantation technology S330, with formation one second lightly doped drain 336b between each the second source/drain 332b and the second channel region 334b, and between each the 3rd source/drain 332c and triple channel district 334c, form one the 3rd lightly doped drain 336c.
Please refer to shown in Fig. 5 D, on substrate 310, form one first protective layer 360a, to cover first grid 350a, second grid 350b, the 3rd grid 350c and capacitance electrode 350d.Then, utilize one the 3 half mode photomask 410c on the first protective layer 360a, to form one the 3rd patterning photoresist layer 420c.Wherein, the composition of the 3 half mode photomask 410c, material and function are identical with the first half mode photomask 410a, repeat no more in this.The 3rd patterning photoresist layer 420c exposes the subregion of the first protective layer 360a of each first polysilicon island thing 330a top.Then, be that mask carries out one first ion implantation technology S320a with the 3rd patterning photoresist layer 420c, in each first polysilicon island thing 330a, to form one first source/drain 332a.Wherein, between the first source/drain 332a promptly be one first channel region 334a.
Please refer to shown in Fig. 5 E, remove the segment thickness of the 3rd patterning photoresist layer 420c, to expose the subregion of the first protective layer 360a of the second polysilicon island thing 330b and the 3rd polysilicon island thing 330c top.Then; with the 3rd patterning photoresist layer 420c is that mask removes part first protective layer 360a and gate insulation layer 340; with the part of the part that exposes each first source/drain 332a, each second source/drain 332b and the part of each the 3rd source/drain 332c, and form one first patterning protective layer 360.Then, remove the 3rd patterning photoresist layer 420c.
More specifically, the mode that forms the first protective layer 360a for example is to form with CVD technology on substrate 310, and its material for example is silica, silicon nitride or other insulating material.And the mode that removes part first protective layer 360a and gate insulation layer 340 for example is that it is carried out lithography process and etching technics.
Please refer to shown in Fig. 5 F, the step of Fig. 5 F is similar to Fig. 3 G among first embodiment haply.After it is included in and forms the first patterning protective layer 360; form the first source/drain conductor layer 370a, the second source/drain conductor layer 370b, the 3rd source/drain conductor layer 370c, the second patterning protective layer 380 and pixel electrode 390 in regular turn, with the manufacturing process of the low-temperature polysilicon film transistor 300 of finishing this embodiment.And the material of above-mentioned each member is identical with first embodiment haply with generation type, repeats no more in this.
Present embodiment utilizes formed the 3rd patterning photoresist layer of the 3 half mode photomask, to carry out first ion implantation technology.Then, remove the segment thickness of the 3rd patterning photoresist layer, first protective layer is changed into the first patterning protective layer.Briefly, present embodiment is to utilize the 3 half mode photomask to replace the twice photomask of prior art, so the present invention can be in order to the usage quantity that reduces photomask to simplify technology, to reduce production costs.Yet the photomask that GTG photomask or other have two or more light transmittances also can replace the 3 half mode photomask and be applied in the present embodiment.
The 4th embodiment
Fig. 6 A to Fig. 6 H is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of fourth embodiment of the invention.Please refer to shown in Fig. 6 A to Fig. 6 E, the content shown in Fig. 6 A to Fig. 6 E is identical with the content shown in Fig. 3 A to Fig. 3 E haply.Briefly, utilize the first half mode photomask 410a to form the first patterning photoresistance 420a, on substrate 310, to finish the first polysilicon island thing 330a, the second polysilicon island thing 330b, the 3rd polysilicon island thing 330c and channel doping technology S310.Then, finish steps such as the second source/drain 332b, the 3rd source/drain 332c, the second channel region 334b, triple channel district 334c, gate insulation layer 340, first grid 350a, second grid 350b, the 3rd grid 350c and capacitance electrode 350d more in regular turn.
Identical, can be prior to forming a resilient coating 320 on the substrate 310, just form first, second and the 3rd polysilicon island thing 330a, 330b, 330c then.Moreover the present invention is not limited in the design of two the 3rd grid 350c, and the present invention also is applicable to the design of single the 3rd grid 350c.In addition, after forming first, second, third grid and capacitance electrode 350a, 350b, 350c, 350d, also can comprise and carry out a lightly doped drain ion implantation technology S330, to form the second lightly doped drain 336b, with the 3rd lightly doped drain 336c.And the material of above-mentioned each member is identical with first embodiment haply with generation type, repeats no more in this.
Please refer to shown in Fig. 6 F to Fig. 6 H, the step of Fig. 6 F to Fig. 6 H is similar to Fig. 5 D to Fig. 5 F among the 3rd embodiment haply.At first, on substrate 310, form the first protective layer 360a.Then, utilize the 3 half mode photomask 410c to form the 3rd patterning photoresist layer 420c, to finish the first source/drain 332a, the first channel region 334a and the first patterning protective layer 360.Then; finish the first source/drain conductor layer 370a, the second source/drain conductor layer 370b, the 3rd source/drain conductor layer 370c, the second patterning protective layer 380 and pixel electrode 390 more in regular turn, with the manufacturing process of the low-temperature polysilicon film transistor 300 of finishing this embodiment.And the material of above-mentioned each member is identical with the 3rd embodiment haply with generation type, repeats no more in this.
Present embodiment utilizes the first half formed first patterning photoresist layers of mode photomask, to form first, second and the 3rd polysilicon island thing.Then, remove the first patterning photoresist layer of the second polysilicon island thing and the 3rd polysilicon island thing top, to proceed channel doping technology.Then, utilize formed the 3rd patterning photoresist layer of the 3 half mode photomask again, to carry out first ion implantation technology.Then, remove the segment thickness of the 3rd patterning photoresist layer, first protective layer is changed into the first patterning protective layer.Briefly, present embodiment is to utilize the first half mode photomasks and the twice photomask that replaces prior art, then, utilize the 3 half mode photomask to replace the twice photomask in addition of prior art again, so the present invention can be in order to the usage quantity that reduces photomask to simplify technology, to reduce production costs.Similarly, GTG photomask or other photomasks with two or more light transmittances also can replace the first and/or the 3 half mode photomask and be applied in the present embodiment.
The 5th embodiment
Fig. 7 A to Fig. 7 G is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of fifth embodiment of the invention.Please refer to shown in Fig. 7 A to Fig. 7 C, the content shown in Fig. 7 A to Fig. 7 C is identical with the content shown in Fig. 4 A to Fig. 4 C haply.Briefly, on substrate 310, form a plurality of first polysilicon island thing 330a, a plurality of second polysilicon island thing 330b and a plurality of the 3rd polysilicon island thing 330c.Then, utilize the second half mode photomask 410b to form the second patterning photoresist layer 420b, to finish the second source/drain 332b, the 3rd source/drain 332c, the second channel region 334b, triple channel district 334c and channel doping technology S310.Identical, can be prior to forming a resilient coating 320 on the substrate 310, just form first, second and the 3rd polysilicon island thing 330a, 330b, 330c then.And the material of above-mentioned each member is identical with second embodiment haply with generation type, repeats no more in this.
Please refer to shown in Fig. 7 D, on substrate 310, form a gate insulation layer 340, to cover first, second and the 3rd polysilicon island thing 330a, 330b, 330c.Then, on gate insulation layer 340, form a plurality of first grid 350a, a plurality of second grid 350b, a plurality of the 3rd grid 350c and a plurality of capacitance electrode 350d.Wherein, each first polysilicon island thing 330a top has a first grid 350a respectively, and each second polysilicon island thing 330b top has a second grid 350b respectively, and each the 3rd polysilicon island thing 330c top has two the 3rd grid 350c and a capacitance electrode 350d respectively.Identical, the present invention is not limited in the design of two the 3rd grid 350c, and the present invention also is applicable to the design of single the 3rd grid 350c.In addition, it is similar to first embodiment to mode and the material thereof of capacitance electrode 350d to form gate insulation layer 340, first grid 350a, second grid 350b, the 3rd grid 350c, repeats no more in this.
Please continue with reference to shown in the figure 7D, after forming first, second, third grid and capacitance electrode 350a, 350b, 350c, 350d, also can comprise and carry out a lightly doped drain ion implantation technology S330, with formation one second lightly doped drain 336b between each the second source/drain 332b and the second channel region 334b, and between each the 3rd source/drain 332c and triple channel district 334c, form one the 3rd lightly doped drain 336c.
Please refer to shown in Fig. 7 E to Fig. 7 G, the step of Fig. 7 E to Fig. 7 G is similar to Fig. 5 D to Fig. 5 F among the 3rd embodiment haply.At first, on substrate 310, form the first protective layer 360a.Then, utilize the 3 half mode photomask 410c to form the 3rd patterning photoresist layer 420c, to finish the first source/drain 332a, the first channel region 334a and the first patterning protective layer 360.Then; finish the first source/drain conductor layer 370a, the second source/drain conductor layer 370b, the 3rd source/drain conductor layer 370c, the second patterning protective layer 380 and pixel electrode 390 more in regular turn, with the manufacturing process of the thin-film transistor array base-plate 300 of finishing this embodiment.And the material of above-mentioned each member is identical with the 3rd embodiment haply with generation type, repeats no more in this.
Present embodiment utilizes the second half formed second patterning photoresist layers of mode photomask, to carry out second ion implantation technology.Then, remove the second patterning photoresist layer of the second polysilicon island thing and the 3rd polysilicon island thing top, to proceed channel doping technology.Then, utilize formed the 3rd patterning photoresist layer of the 3 half mode photomask again, to carry out first ion implantation technology.Then, remove the segment thickness of the 3rd patterning photoresist layer, first protective layer is changed into the first patterning protective layer.Briefly, present embodiment is to utilize the second half mode photomasks to replace the twice photomask of prior art, then, utilize the 3 half mode photomask to replace the twice photomask in addition of prior art again, so the present invention can be in order to the usage quantity that reduces photomask to simplify technology, to reduce production costs.Similarly, GTG photomask or other photomasks with two or more light transmittances also can replace the second and/or the 3 half mode photomask and be applied in the present embodiment.
The 6th embodiment
Fig. 8 A to Fig. 8 G is a kind of low-temperature polysilicon film transistor manufacturing process schematic diagram of sixth embodiment of the invention.Please refer to shown in Fig. 8 A to Fig. 8 D, the content shown in Fig. 8 A to Fig. 8 D is identical with the content shown in Fig. 3 A to Fig. 3 D haply.Briefly, utilize the first half mode photomask 410a to form the first patterning photoresistance 420a, on substrate 310, to finish the first polysilicon island thing 330a, the second polysilicon island thing 330b, the 3rd polysilicon island thing 330c and channel doping technology S310.Then, carry out one second ion implantation technology S320b again to form the second source/drain 332b, the 3rd source/drain 332c, the second channel region 334b, triple channel district 334c.Identical, can be prior to forming a resilient coating 320 on the substrate 310, just form first, second and the 3rd polysilicon island thing 330a, 330b, 330c then.And the material of above-mentioned each member is identical with first embodiment haply with generation type, repeats no more in this.
Please refer to shown in Fig. 8 E, on substrate 310, form a gate insulation layer 340, to cover first, second and the 3rd polysilicon island thing 330a, 330b, 330c.Then, on gate insulation layer 340, form a patterned conductor material layer 350 and a plurality of first grid 350a.Wherein, patterned conductor material layer 350 covers the second polysilicon island thing 330b and the 3rd polysilicon island thing 330c.Then, be that mask carries out one first ion implantation technology S320a with first grid 350a, in each first polysilicon island thing 130a, to form one first source/drain 332a.Wherein, between the first source/drain 332a promptly be one first channel region 334a.
More specifically, the material of gate insulation layer 340 can be that silica or other insulating material are formed.And the mode that forms silica can be to adopt ion growth form chemical vapor deposition process, and cooperates SiH 4/ N 2O or TEOS/O 2Deng reacting gas.Moreover forming patterned conductor material layer 350 can be to form a conductor material layer (not shown) with sputtering process or physical vapor deposition process earlier on gate insulation layer 340.Wherein, the material of conductor material layer can be chromium (Cr) or other metal materials.Then, again this conductor material layer is carried out lithography process and etching technics, to form patterned conductor material layer 350 and first grid 350a.
Please refer to shown in Fig. 8 F, remove partially patterned conductor material layer 350, exposing the subregion of gate insulation layer 340 of the second polysilicon island thing 330b and the 3rd polysilicon island thing 330c top, and form a plurality of second grid 350b, a plurality of the 3rd grid 350c and a plurality of capacitance electrode 350d.Wherein, each second polysilicon island thing 330b top has a second grid 350b respectively, and each the 3rd polysilicon island thing 330c top has two the 3rd grid 350c and a capacitance electrode 350d respectively.Identical, the present invention is not limited in the design of two the 3rd grid 350c, and the present invention also is applicable to the design of single the 3rd grid 350c.More specifically, forming the mode of second, third grid and capacitance electrode 350b, 350c, 350d, for example is that patterned conductor material layer 350 is carried out lithography process and etching technics.In addition, after forming first, second, third grid and capacitance electrode 350a, 350b, 350c, 350d, also can comprise and carry out a lightly doped drain ion implantation technology S330, with formation one second lightly doped drain 336b between each the second source/drain 332b and the second channel region 334b, and between each the 3rd source/drain 332c and triple channel district 334c, form one the 3rd lightly doped drain 336c.
Please refer to shown in Fig. 8 G, the step of Fig. 8 G is similar to Fig. 3 G among first embodiment haply.It comprises and forms the first patterning protective layer 360, the first source/drain conductor layer 370a, the second source/drain conductor layer 370b, the 3rd source/drain conductor layer 370c, the second patterning protective layer 380 and pixel electrode 390 in regular turn, with 300 manufacturing process of the thin-film transistor array base-plate of finishing this embodiment.And the material of above-mentioned each member is identical with first embodiment haply with generation type, repeats no more in this.
Present embodiment utilizes the first half formed first patterning photoresist layers of mode photomask, to form first, second and the 3rd polysilicon island thing.Then, remove the first patterning photoresist layer of the second polysilicon island thing and the 3rd polysilicon island thing top, to proceed channel doping technology.Briefly, present embodiment is to utilize the first half mode photomasks to replace the twice photomask of prior art, so the present invention can be in order to the usage quantity that reduces photomask to simplify technology, to reduce production costs.Similarly, GTG photomask or other photomasks with two or more light transmittances also can replace the first half mode photomasks and be applied in the present embodiment.
The 7th embodiment
Fig. 9 A to Fig. 9 F is a kind of low-temperature polysilicon film transistor manufacturing process schematic diagram of seventh embodiment of the invention.Please refer to shown in Fig. 9 A to Fig. 9 C, the content shown in Fig. 9 A to Fig. 9 C is identical with the content shown in Fig. 4 A to Fig. 4 C haply.Briefly, on substrate 310, form a plurality of first polysilicon island thing 330a, a plurality of second polysilicon island thing 330b and a plurality of the 3rd polysilicon island thing 330c.Then, utilize the second half mode photomask 410b to form the second patterning photoresist layer 420b, to finish the second source/drain 332b, the 3rd source/drain 332c, the second channel region 334b, triple channel district 334c and channel doping technology S310.Identical, can be prior to forming a resilient coating 320 on the substrate 310, just form first, second and the 3rd polysilicon island thing 330a, 330b, 330c then.And the material of above-mentioned each member is identical with second embodiment haply with generation type, repeats no more in this.
Please refer to shown in Fig. 9 D to Fig. 9 F, the step of Fig. 9 D to Fig. 9 F is similar to Fig. 8 E to Fig. 8 G among the 6th embodiment haply.It comprises and forms gate insulation layer 340, first grid 350a, the first source/drain 332a, the first channel region 334a, second grid 350b, the 3rd grid 350c, capacitance electrode 350d, the first patterning protective layer 360, the first source/drain conductor layer 370a, the second source/drain conductor layer 370b, the 3rd source/drain conductor layer 370c, the second patterning protective layer 380 and pixel electrode 390 in regular turn, with 300 manufacturing process of the thin-film transistor array base-plate of finishing this embodiment.Identical, the present invention is not limited in the design of two the 3rd grid 350c, and the present invention also is applicable to the design of single the 3rd grid 350c.In addition, after forming first, second, third grid and capacitance electrode 350a, 350b, 350c, 350d, also can comprise and carry out a lightly doped drain ion implantation technology S330, to form the second lightly doped drain 336b, with the 3rd lightly doped drain 336c.And the material of above-mentioned each member is identical with the 6th embodiment haply with generation type, repeats no more in this.
Present embodiment utilizes the second half formed second patterning photoresist layers of mode photomask, to carry out second ion implantation technology.Then, remove the second patterning photoresist layer of the second polysilicon island thing and the 3rd polysilicon island thing top, to proceed channel doping technology.Briefly, present embodiment is to utilize the second half mode photomasks to replace the twice photomask of prior art, so the present invention can be in order to the usage quantity that reduces photomask to simplify technology, to reduce production costs.Similarly, GTG photomask or other photomasks with two or more light transmittances also can replace the second half mode photomasks and be applied in the present embodiment.
The 8th embodiment
Figure 10 A to Figure 10 E illustrates the manufacturing process schematic diagram into a kind of thin-film transistor array base-plate of eighth embodiment of the invention.Please refer to shown in Figure 10 A to Figure 10 B, the content shown in Figure 10 A to Figure 10 B is identical with the content shown in Fig. 5 A to Fig. 5 B haply.Briefly, finish earlier the first polysilicon island thing 330a, the second polysilicon island thing 330b, the 3rd polysilicon island thing 330c, the second source/drain 332b, the 3rd source/drain 332c, the second channel region 334b and triple channel district 334c in regular turn.Identical, can be prior to forming a resilient coating 320 on the substrate 310, just form first, second and the 3rd polysilicon island thing 330a, 330b, 330c then.And form resilient coating 320, first, second mode and material thereof to the 3rd polysilicon island thing 330a, 330b, 330c is similar to the 3rd embodiment, repeat no more in this.
Please refer to shown in Figure 10 C, at first, on substrate 310, form a gate insulation layer 340 and a conductor material layer (not shown) in regular turn.Then, utilize one the 4 half mode photomask 410d on conductor material layer, to form one the 4th patterning photoresist layer 420d.Wherein, the composition of the 4 half mode photomask 410d, material and function are identical with the first half mode photomask 410a, repeat no more in this.Then, be that mask removes the segment conductor material layer with the 4th patterning photoresist layer 420d, to form a patterned conductor material layer 350 and a plurality of first grid 350a.Wherein, patterned conductor material layer 350 covers the second polysilicon island thing 330b and the 3rd polysilicon island thing 330c.More specifically, the mode that forms conductor material layer for example is sputtering process or physical vapor deposition process, and the mode of formation patterned conductor material layer 350 for example is lithography process and etching technics.Wherein, the material of conductor material layer can be chromium (Cr) or other metal materials.
Please continue with reference to shown in the figure 10C, be that mask carries out one first ion implantation technology S320a with the 4th patterning photoresist layer 420d, to form one first source/drain 332a in each first polysilicon island thing 330a.Wherein, between the first source/drain 332a promptly be one first channel region 334a.Then, remove the segment thickness of the 4th patterning photoresist layer 420d, to expose the subregion of gate insulation layer 340 of the second polysilicon island thing 330b and the 3rd polysilicon island thing 330c top.
Please refer to shown in Figure 10 D, is that mask removes partially patterned conductor material layer 350 with the 4th patterning photoresist layer 420d, to form a plurality of second grid 350b, a plurality of the 3rd grid 350c and a plurality of capacitance electrode 350d.Wherein, each second polysilicon island thing 330b top has a second grid 350b respectively, and each the 3rd polysilicon island thing 330c top has two the 3rd grid 350c and a capacitance electrode 350d respectively.Identical, the present invention is not limited in the design of two the 3rd grid 350c, and the present invention also is applicable to the design of single the 3rd grid 350c.More specifically, forming the mode of second, third grid and capacitance electrode 350b, 350c, 350d, for example is that patterned conductor material layer 350 is carried out lithography process and etching technics.In addition, after forming first, second, third grid and capacitance electrode 350a, 350b, 350c, 350d, also can comprise and carry out a lightly doped drain ion implantation technology S330, with formation one second lightly doped drain 336b between each the second source/drain 332b and the second channel region 334b, and between each the 3rd source/drain 332c and triple channel district 334c, form one the 3rd lightly doped drain 336c.
Please refer to shown in Figure 10 E, the step of Figure 10 E is similar to Fig. 9 F among the 7th embodiment haply.It comprises and forms the first patterning protective layer 360, the first source/drain conductor layer 370a, the second source/drain conductor layer 370b, the 3rd source/drain conductor layer 370c, the second patterning protective layer 380 and pixel electrode 390 in regular turn, with the manufacturing process of the low-temperature polysilicon film transistor 300 of finishing this embodiment.And the material of above-mentioned each member is identical with the 7th embodiment haply with generation type, repeats no more in this.
Present embodiment utilizes formed the 4th patterning photoresist layer of the 4 half mode photomask, carries out first ion implantation technology again behind the formation first grid earlier.Then, remove the segment thickness of the 4th patterning photoresist layer, to continue to form second, third grid and capacitance electrode.Briefly, present embodiment is to utilize the 4 half mode photomask to replace the twice photomask of prior art, so the present invention can be in order to the usage quantity that reduces photomask to simplify technology, to reduce production costs.Similarly, GTG photomask or other photomasks with two or more light transmittances also can replace the 4 half mode photomask and be applied in the present embodiment.
The 9th embodiment
Figure 11 A to Figure 11 G is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of ninth embodiment of the invention.Please refer to shown in Figure 11 A to Figure 11 D, the content shown in Figure 11 A to Figure 11 D content with first embodiment shown in Fig. 3 A to Fig. 3 D haply is identical.Briefly, utilize the first half mode photomask 410a to form the first patterning photoresistance 420a, on substrate 310, to finish the first polysilicon island thing 330a, the second polysilicon island thing 330b, the 3rd polysilicon island thing 330c and channel doping technology S310.Then, finish the second source/drain 332b, the 3rd source/drain 332c, the second channel region 334b and triple channel district 334c with the second ion implantation technology S320b again.
Identical, can be prior to forming a resilient coating 320 on the substrate 310, just form first, second and the 3rd polysilicon island thing 330a, 330b, 330c then.And the material of above-mentioned each member is identical with first embodiment haply with generation type, repeats no more in this.
Please refer to shown in Figure 11 E to Figure 11 G, the step of Figure 11 E to Figure 11 G is similar to Figure 10 C to Figure 10 E among the 8th embodiment haply.On substrate 310, form a gate insulation layer 340 and a conductor material layer (not shown) at first, in regular turn.Then, utilize the 4 half mode photomask 410d to form the 4th patterning photoresist layer 420d, to finish first grid 350a, the first source/drain 332a, the first channel region 334a, second grid 350b, the 3rd grid 350c and capacitance electrode 350d in regular turn.Then; finish the first patterning protective layer 360, the first source/drain conductor layer 370a, the second source/drain conductor layer 370b, the 3rd source/drain conductor layer 370c, the second patterning protective layer 380 and pixel electrode 390 more in regular turn, with the manufacturing process of the thin-film transistor array base-plate 300 of finishing this embodiment.
Identical, the present invention is not limited in the design of two the 3rd grid 350c, and the present invention also is applicable to the design of single the 3rd grid 350c.In addition, after forming first, second, third grid and capacitance electrode 350a, 350b, 350c, 350d, also can comprise and carry out a lightly doped drain ion implantation technology S330, with formation one second lightly doped drain 336b between each the second source/drain 332b and the second channel region 334b, and between each the 3rd source/drain 332c and triple channel district 334c, form one the 3rd lightly doped drain 336c.And the material of above-mentioned each member is identical with the 8th embodiment haply with generation type, repeats no more in this.
Present embodiment utilizes the first half formed first patterning photoresist layers of mode photomask, to form first, second and the 3rd polysilicon island thing.Then, remove the first patterning photoresist layer of the second polysilicon island thing and the 3rd polysilicon island thing top, to proceed channel doping technology.Then, utilize formed the 4th patterning photoresist layer of the 4 half mode photomask again, carry out first ion implantation technology again behind the formation first grid earlier.Then, remove the segment thickness of the 4th patterning photoresist layer, to continue to form second, third grid and capacitance electrode.Briefly, present embodiment is to utilize the first half mode photomasks and the twice photomask that replaces prior art, then, utilize the 4 half mode photomask to replace the twice photomask in addition of prior art again, so the present invention can be in order to the usage quantity that reduces photomask to simplify technology, to reduce production costs.Similarly, GTG photomask or other photomasks with two or more light transmittances also can replace the first and/or the 4 half mode photomask and be applied in the present embodiment.
The tenth embodiment
Figure 12 A to Figure 12 F is the manufacturing process schematic diagram of a kind of thin-film transistor array base-plate of tenth embodiment of the invention.Please refer to shown in Figure 12 A to Figure 12 C, the content shown in Figure 12 A to Figure 12 C is identical with the content shown in Fig. 4 A to Fig. 4 C haply.Briefly, on substrate 310, form a plurality of first polysilicon island thing 330a, a plurality of second polysilicon island thing 330b and a plurality of the 3rd polysilicon island thing 330c.Then, utilize the second half mode photomask 410b to form the second patterning photoresist layer 420b, to finish the second source/drain 332b, the 3rd source/drain 332c, the second channel region 334b, triple channel district 334c and channel doping technology S310.Identical, can be prior to forming a resilient coating 320 on the substrate 310, just form first, second and the 3rd polysilicon island thing 330a, 330b, 330c then.And the material of above-mentioned each member is identical with second embodiment haply with generation type, repeats no more in this.
Please refer to shown in Figure 12 D to Figure 12 F, the step of Figure 12 D to Figure 12 F is similar to Figure 10 C to Figure 10 E among the 8th embodiment haply.On substrate 310, form a gate insulation layer 340 and a conductor material layer (not shown) at first, in regular turn.Then, utilize the 4 half mode photomask 410d to form the 4th patterning photoresist layer 420d, to finish first grid 350a, the first source/drain 332a, the first channel region 334a, second grid 350b, the 3rd grid 350c and capacitance electrode 350d in regular turn.Then; finish the first patterning protective layer 360, the first source/drain conductor layer 370a, the second source/drain conductor layer 370b, the 3rd source/drain conductor layer 370c, the second patterning protective layer 380 and pixel electrode 390 more in regular turn, with the manufacturing process of the thin-film transistor array base-plate 300 of finishing this embodiment.
Identical, the present invention is not limited in the design of two the 3rd grid 350c, and the present invention also is applicable to the design of single the 3rd grid 350c.In addition, after forming first, second, third grid and capacitance electrode 350a, 350b, 350c, 350d, also can comprise and carry out a lightly doped drain ion implantation technology S330, with formation one second lightly doped drain 336b between each the second source/drain 332b and the second channel region 334b, and between each the 3rd source/drain 332c and triple channel district 334c, form one the 3rd lightly doped drain 336c.And the material of above-mentioned each member is identical with the 8th embodiment haply with generation type, repeats no more in this.
Present embodiment utilizes the second half formed second patterning photoresist layers of mode photomask, to carry out second ion implantation technology.Then, remove the second patterning photoresist layer of the second polysilicon island thing and the 3rd polysilicon island thing top, to proceed channel doping technology.Then, utilize formed the 4th patterning photoresist layer of the 4 half mode photomask again, carry out first ion implantation technology again behind the formation first grid earlier.Then, remove the segment thickness of the 4th patterning photoresist layer, to continue to form second, third grid and capacitance electrode.Briefly, present embodiment is to utilize the second half mode photomasks to replace the twice photomask of prior art, then, utilize the 4 half mode photomask to replace the twice photomask in addition of prior art again, so the present invention can be in order to the usage quantity that reduces photomask to simplify technology, to reduce production costs.Similarly, GTG photomask or other photomasks with two or more light transmittances also can replace second and/the four half mode photomask and be applied in the present embodiment.
In sum, the present invention forms with different height with the photoresistance that needed twice on the technology are continuous simultaneously because of adopting half mode photomask or GTG photomask.Therefore, the user can be reduced to 7 roads or 8 road photomasks by half mode photomask or GTG photomask with 9 road photomasks of existing low-temperature polysilicon film transistor.So the technology of thin-film transistor array base-plate can be simplified, and then reach the purpose that promotes yield and then increase panel size.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those of ordinary skills, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.

Claims (4)

1. the manufacture method of a thin-film transistor array base-plate comprises:
On a substrate, form a polysilicon layer, and this substrate have a surrounding zone and an array district;
Utilize one the first half mode photomask on this polysilicon layer, to form one first patterning photoresist layer;
With this first patterning photoresist layer is that mask removes this polysilicon layer of part, to form a plurality of first polysilicon island things, a plurality of second polysilicon island thing and a plurality of the 3rd polysilicon island thing, wherein those first polysilicon island things and those second polysilicon island things are positioned on this surrounding zone, and those the 3rd polysilicon island things are positioned on this array area;
Remove this first patterning photoresist layer of those second polysilicon island things and those the 3rd polysilicon island things top;
Carry out a channel doping technology, in those second polysilicon island things and those the 3rd polysilicon island things, to inject ion;
Remove this first patterning photoresist layer;
Carry out one second ion implantation technology, in this second polysilicon island thing respectively, to form one second source/drain and in respectively forming one the 3rd source/drain in the 3rd polysilicon island thing, promptly be one second channel region between this second source/drain wherein, and promptly be a triple channel district between the 3rd source/drain;
On this substrate, form a gate insulation layer, to cover those first polysilicon island things, those second polysilicon island things and those the 3rd polysilicon island things;
Form a plurality of first grids, a plurality of second grid and a plurality of the 3rd grid on this gate insulation layer, wherein those first grids, those second grids and those the 3rd grids lay respectively at those first polysilicon island things, those second polysilicon island things and those the 3rd polysilicon island things top;
Carrying out one first ion implantation technology, forming one first source/drain in this first polysilicon island thing respectively, and promptly is one first channel region between this first source/drain;
On this substrate, form one first patterning protective layer, to cover those first grids, those second grids and those the 3rd grids;
With this first patterning protective layer is that mask removes this gate insulation layer of part, with the part that exposes this first source/drain respectively, the respectively part and the part of the 3rd source/drain respectively of this second source/drain;
On this first patterning protective layer, form a plurality of first source/drain conductor layers, a plurality of second source/drain conductor layer and a plurality of the 3rd source/drain conductor layer, wherein those first source/drain conductor layers electrically connect with those first source/drains respectively, and those second source/drain conductor layers electrically connect with those second source/drains respectively, and those the 3rd source/drain conductor layers electrically connect with those the 3rd source/drains respectively;
Form one second patterning protective layer on this first patterning protective layer, wherein this second patterning protective layer exposes the respectively part of the 3rd source/drain conductor layer; And
Form a plurality of pixel electrodes on this second patterning protective layer, wherein respectively this pixel electrode and corresponding the 3rd source/drain conductor layer electrically connect.
2. the manufacture method of thin-film transistor array base-plate as claimed in claim 1, it is characterized in that, after forming those first grids, those second grids and those the 3rd grids, also comprise and carry out a lightly doped drain ion implantation technology, respectively forming one second lightly doped drain between this second source/drain and this second channel region, and at formation one the 3rd lightly doped drain between the 3rd source/drain and this triple channel district respectively.
3. the manufacture method of a thin-film transistor array base-plate comprises:
On a substrate, form a polysilicon layer, and this substrate have a surrounding zone and an array district;
Utilize one the first half mode photomask on this polysilicon layer, to form one first patterning photoresist layer;
With this first patterning photoresist layer is that mask removes this polysilicon layer of part, to form a plurality of first polysilicon island things, a plurality of second polysilicon island thing and a plurality of the 3rd polysilicon island thing, wherein those first polysilicon island things and those second polysilicon island things are positioned on this surrounding zone, and those the 3rd polysilicon island things are positioned on this array area;
Remove this first patterning photoresist layer of those second polysilicon island things and those the 3rd polysilicon island things top;
Carry out a channel doping technology, in those second polysilicon island things and those the 3rd polysilicon island things, to inject ion;
Remove this first patterning photoresist layer;
Carry out one second ion implantation technology, in this second polysilicon island thing respectively, to form one second source/drain and in respectively forming one the 3rd source/drain in the 3rd polysilicon island thing, promptly be one second channel region between this second source/drain wherein, and promptly be a triple channel district between the 3rd source/drain;
On this substrate, form a gate insulation layer, to cover those first polysilicon island things, those second polysilicon island things and those the 3rd polysilicon island things;
Form a patterned conductor material layer on this gate insulation layer, wherein this patterned conductor material layer has a plurality of first grids, is positioned on this gate insulation layer of those first polysilicon island thing tops;
With this patterned conductor material layer is that mask carries out one first ion implantation technology, with in respectively forming one first source/drain in this first polysilicon island thing, wherein promptly is one first channel region between this first source/drain;
Remove this patterned conductor material layer of part, exposing the subregion of this gate insulation layer above those second polysilicon island things and those the 3rd polysilicon island things, and form a plurality of second grids and a plurality of the 3rd grid;
On this gate insulation layer, form one first patterning protective layer, to cover those first grids, those second grids and those the 3rd grids, wherein this first patterning protective layer exposes the subregion of this gate insulation layer of those first polysilicon island things, those second polysilicon island things and those the 3rd polysilicon island things top;
With this first patterning protective layer is that mask removes this gate insulation layer of part, with the part that exposes this first source/drain respectively, the respectively part and the part of the 3rd source/drain respectively of this second source/drain;
On this first patterning protective layer, form a plurality of first source/drain conductor layers, a plurality of second source/drain conductor layer and a plurality of the 3rd source/drain conductor layer, wherein those first source/drain conductor layers electrically connect with those first source/drains respectively, and those second source/drain conductor layers electrically connect with those second source/drains respectively, and those the 3rd source/drain conductor layers electrically connect with those the 3rd source/drains respectively;
Form one second patterning protective layer on this first patterning protective layer, wherein this second patterning protective layer exposes the respectively part of the 3rd source/drain conductor layer; And
Form a plurality of pixel electrodes on this second patterning protective layer, wherein respectively this pixel electrode and corresponding the 3rd source/drain conductor layer electrically connect.
4. the manufacture method of thin-film transistor array base-plate as claimed in claim 3, it is characterized in that, after forming those first grids, those second grids and those the 3rd grids, also comprise and carry out a lightly doped drain ion implantation technology, respectively forming one second lightly doped drain between this second source/drain and this second channel region, and at formation one the 3rd lightly doped drain between the 3rd source/drain and this triple channel district respectively.
CN2008101868270A 2006-08-25 2006-08-25 Thin-film transistor array substrate preparation method Expired - Fee Related CN101640189B (en)

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