CN101640074B - Memory repair circuit and imitative dual-port static random access memory using same - Google Patents
Memory repair circuit and imitative dual-port static random access memory using same Download PDFInfo
- Publication number
- CN101640074B CN101640074B CN 200810128097 CN200810128097A CN101640074B CN 101640074 B CN101640074 B CN 101640074B CN 200810128097 CN200810128097 CN 200810128097 CN 200810128097 A CN200810128097 A CN 200810128097A CN 101640074 B CN101640074 B CN 101640074B
- Authority
- CN
- China
- Prior art keywords
- multiplexer
- block
- row address
- input end
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Static Random-Access Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention relates to a memory repair circuit and an imitative dual-port static random access memory using the same. The memory repair circuit reduces the complexity for decoding standby blocks required for the standby row blocks by using a small number of standby row blocks and a mode of storing a small number of damaged block addresses. Therefore, the memory repair circuit and the imitative dual-port static random access memory using the same can reduce a layout area required for a standby memory unit.
Description
Technical field
The invention relates to a kind of technology of memory repair, and particularly relevant for a kind of repairable imitative dual-port static random access memory.
Background technology
Electronic industry is flourish in recent years, and relevant electronic technology is progressive fast, so that the technique of storer is constantly dwindled.Static RAM (Static Random Access Memory, SRAM) is to use at present very general in-line memory (embedded memory) device in VLSI (very large scale integrated circuit) (VLSI) field.Be accompanied by the progress of technique, the area of the memory cell (cell) of single static random access memory is little of 2 μ m in 0.13 μ m technique at present
2Below, in 90nm technique, also can arrive 1 μ m nearly
2A minimum particulate (particle) this means in the technique way as long as just might cause the position defective (bit failure) of static RAM.
In the application of panel driving integrated circuit, because the resolution of panel constantly promotes, the size and area also thereupon increase of its required built-in static RAM.When the total area increase of static RAM, its single bit memory cell area reducing, the chance of the position defective that occurs because of technique or particulate in same panel driving integrated circuit will increase gradually.Also therefore, whole panel drive circuit is a position defective because of static RAM usually, thereby becomes fault wafer (fail die), and the impact that reduces the rate (yield) that manufactures a finished product will be more and more obvious.
For the position defective that overcomes static RAM and promote yield rate, the repair mechanism of static RAM becomes important.And in repair mechanism, how to design shelf storage unit (redundant memory cells) and automatic replacement fault position (failed bit) how, usually be integrated circuit (IC) design person's a difficult problem.In known technology, it is technology of patch memory defective that several technology are arranged: be respectively No. 5,257,229, United States Patent (USP) bulletin US Patent and United States Patent (USP) bulletin US Patent 7,173, and 867B2 number.
5,257, No. 229 patents of United States Patent (USP) bulletin US Patent are the static RAMs for single-port, utilize spare columns (redundant column) to repair.For asking the height utilization that reaches spare columns, in this piece of writing bulletin, each spare columns can mapped (map) be done the usefulness of repairing to any column position.Yet, it is designed that this technology is only made the repairing of row address for the static RAM of single-port (single-port), static RAM for dual-port (dual-port), therefore because the frequency range of the data bus of two ports (data bus) is different, can't be applied in fault position on the static RAM of repairing dual-port (dual-port) with same technology.In addition, although each spare columns can be used to repair arbitrary row in this technology, seem efficient very high, but because in static RAM, need the selection circuit of many spare columns and corresponding fuse (fuse), if it is then unactual therefore to be applied in the static RAM of dual-port (dual-port).
United States Patent (USP) bulletin US Patent 7,173, the 867B2 patent is to make storer for very highdensity storer to cut apart (memory partition).It uses universe (global)/zone (local) bit line (bit line) and universe (global)/zone (local) character line (word line), storer is divided into the block of cells (block) that can work fast.Afterwards, place column or row for subsequent use (redundant row or column) as repair mechanism for each block of cells.The shortcoming of this technology is similar to last technology.Although storer is divided into many fritters, and each block of cells can have separately spare columns or spare row to do reparation.But the method need to store a large amount of fault bit address (failed bit address).Therefore, use the decode structures (decoding scheme of redundant column) of spare row of the storer of this technology to be difficult to be applied in storer on the driving circuit of display panels.
Because the storer of the driving circuit of display panels needs the dual-port static random access memory of different frequency ranges, general memory repair technology all is the master that is applied as with the single port static RAM.When above-mentioned repairing technique must be used in asymmetrical dual-port static random access memory (for example driving circuit of liquid crystal display), automatically the circuit of repairing and the layout arrangement of its representative can not can both efficiently be used on asymmetrical two ports with prior art.
Summary of the invention
In view of this, one object of the present invention is exactly a kind of repairable imitative dual-port static random access memory is provided, in order to be applied in asymmetrical dual-port static random access memory.
Another object of the present invention is exactly in the fix-up circuit that a kind of repairable imitative dual-port static random access memory and imitative dual-port static random access memory are provided, in order to the complexity of the decoding that reduces the needed layout area in shelf storage unit and shelf storage unit.
For reaching above-mentioned or other purposes, the present invention proposes a kind of repairable imitative dual-port static random access memory, and this imitative dual-port static random access memory comprises a memory cell array, an address decoding circuitry, one first input/output port, one second input/output port, one first selection circuit and one second selection circuit.Memory cell array comprises a plurality of block of memory cells and a spare blocks, and wherein, each above-mentioned block of memory cells is divided into a plurality of memory cell sub-block, and in addition, the spare area block size is identical with above-mentioned memory cell sub-block.Address decoding circuitry comprises a column address decoding circuit, a first row address decoding circuitry and one second row address decoding circuit.The particular column of column address decoding circuit in order to open memory cell array according to the specified particular column of column address.The first row address decoding circuitry has the connection bus of N position, and it connects bus in order to the N position that is connected to the first row address decoding circuitry according to N the first particular row in individual the first specific enforcement memory cell array of the specified N of the first row address signal.The second row address decoding circuit has the connection bus of M position, and it connects bus in order to the M position that is connected to the second row address decoding circuit according to M the second particular row in individual the second specific enforcement memory cell array of the specified M of the second row address signal.The first input/output port has N position bus.The second input/output port has M position bus.First selects circuit to couple the N position bus that the first row address decoding circuitry N position connects bus and the first input/output port.The second M position of selecting circuit to couple the second row address decoding circuit connects the M position bus of bus and the second input/output port.When one first specified particular row of the first row address signal is positioned at the memory cell sub-block of damage, then first select circuit to select one first corresponding row of spare blocks, and it is couple to the N position bus of the first input/output port, wherein the address of the first particular row in the memory cell sub-block of the relative address of the first corresponding row and damage is identical.When one second specified particular row of the second row address signal is positioned at the memory cell sub-block of damage, then second select circuit to select one second corresponding row of spare blocks, and it is couple to the M position bus of the second input/output port, wherein the address of the second particular row in the memory cell sub-block of the relative address of the second corresponding row and damage is identical.Above-mentioned M, N are natural number, and M〉N.
The present invention proposes a kind of fix-up circuit of imitative dual-port static random access memory in addition, wherein, this imitative dual-port static random access memory comprises a memory cell array, an address decoding circuitry, one first input/output port and one second input/output port.Memory cell array comprises a plurality of block of memory cells, and wherein, each above-mentioned block of memory cells is divided into a plurality of memory cell sub-block.Address decoding circuitry comprises a column address decoding circuit, a first row address decoding circuitry and one second row address decoding circuit.The particular column of column address decoding circuit in order to open memory cell array according to the specified particular column of column address.The first row address decoding circuitry has the connection bus of N position, and it connects bus in order to the N position that is connected to the first row address decoding circuitry according to N the first particular row in individual the first specific enforcement memory cell array of the specified N of the first row address signal.The second row address decoding circuit has the connection bus of M position, and it connects bus in order to the M position that is connected to the second row address decoding circuit according to M the second particular row in individual the second specific enforcement memory cell array of the specified M of the second row address signal.The first input/output port has N position bus.The second input/output port has M position bus.In addition, memory repair circuit comprises a spare blocks, one first selection circuit and one second selection circuit.Spare blocks is disposed in the memory cell array, and wherein, the spare area block size is identical with above-mentioned memory cell sub-block.First selects circuit to couple the N position bus that the first row address decoding circuitry N position connects bus and the first input/output port.The second M position of selecting circuit to couple the second row address decoding circuit connects the M position bus of bus and the second input/output port.When one first specified particular row of the first row address signal is positioned at the memory cell sub-block of damage, then first select circuit to select one first corresponding row of spare blocks, and it is couple to the N position bus of the first input/output port, wherein the address of the first particular row in the memory cell sub-block of the relative address of the first corresponding row and damage is identical.When one second specified particular row of the second row address signal is positioned at the memory cell sub-block of damage, then second select circuit to select one second corresponding row of spare blocks, and it is couple to the M position bus of the second input/output port, wherein the address of the second particular row in the memory cell sub-block of the relative address of the second corresponding row and damage is identical.Above-mentioned M, N are natural number, and M〉N.
According to the described memory repair circuit of preferred embodiment of the present invention and use its imitative dual-port static random access memory, above-mentioned memory cell array comprises that a block of memory cells, each block of memory cells comprise b memory cell sub-block, each memory cell sub-block comprises c row address, and then the first row address decoding circuitry comprises a * b the first multiplexer and a the second multiplexer.Each above-mentioned first multiplexer comprises c input end and d output terminal, and wherein, c input end of the i * j the first multiplexer couples respectively c row address of j memory cell sub-block of i block of memory cells.Each above-mentioned second multiplexer comprises b * d input end and d output terminal, wherein, the p of k the second multiplexer * 1～the p * d input end couples respectively the 1st～a d output terminal of the k * p the first multiplexer, and wherein a, b, c, d, i, j, k, p belong to natural number; D * a=N; I and k between 0 and a between, j and p between 0 and b between.Each first multiplexer is selected d row address according to the first of the first row address signal, and an above-mentioned d row address is electrically connected with its d output terminal.In addition, each second multiplexer from described b the multiplexer that it couples, is selected one of them specific multiplexer according to the second portion of the first row address signal, and d output terminal of this specific multiplexer is electrically connected to its d output terminal.
In addition, according to the design of above-mentioned preferred embodiment, spare blocks comprises c row address, and first selects circuit to comprise: one the 3rd multiplexer, a the 4th multiplexer and a first control circuit.The 3rd multiplexer comprises c input end and d output terminal, wherein, the c of the 3rd a multiplexer input end couples respectively c row address of spare blocks, and according to the first of the first row address signal, select d row address, an above-mentioned d row address is electrically connected with its d output terminal.Each above-mentioned the 4th multiplexer comprises control input end, first group of input end, second group of input end and d output terminal, wherein, its first group of input end and second group of input end comprise respectively d input end, first group of input end of u the 4th multiplexer couples d output terminal of u the second multiplexer, and second group of input end of each described the 4th multiplexer couples d output terminal of the 3rd multiplexer.First control circuit comprises a control output end, couples respectively the control input end of above-mentioned the 4th multiplexer.When the first specified particular row of the first row address signal, be positioned at y memory cell sub-block of v block of memory cells, and during the memory cell sub-block that y memory cell sub-block of v block of memory cells is above-mentioned damage, then v the 4th multiplexer controlled in v control output end of first control circuit, make its second group of input end be electrically connected to its d output terminal, wherein, v, y belong to natural number, and v between 0 and a between, y between 0 and b between.
Spirit of the present invention is the position defective (bit failure) that the imitative dual-port static random access memory that is to utilize spare blocks reparation to can be applicable to have in the driving circuit of liquid crystal display two different frequency range input/output port may occur.The present invention can utilize the spare row block (redundant column) of lesser amt, and the mode that stores a small amount of bad block address (failed address) reduces the complexity of the needed spare blocks decoding of spare row block (redundancy decoding).Therefore, the present invention can reduce the needed layout area in shelf storage unit.
For above and other purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the circuit block diagram of the imitative dual-port static random access memory that illustrates according to the embodiment of the invention.
Fig. 2 is the circuit block diagram of the imitative dual-port static random access memory that illustrates according to embodiment of the invention Fig. 1.
Fig. 3 be according to the embodiment of the invention illustrate in order to export control signal ASEL[0]～ASEL[3] the circuit diagram of control circuit.
Fig. 4 be according to the embodiment of the invention illustrate in order to export control signal BSEL[0]～BSEL[7] the circuit diagram of control circuit.
Drawing reference numeral
101: memory cell array
102: the column address decoding circuit
103: the first row address decoding circuitry
104: the second row address decoding circuit
105: the first input/output port
106: the second input/output port
107: the first selection circuit
108: the second selection circuit
I/O[0]～I/O[k], I/O[0]～I/O[3]: block of memory cells
I/O[s]: spare blocks
109: first control circuit
110,111,113,114: multiplexer
112: second control circuit
BL[0:15], BL[16:31], BL[32:47], BL[48:63]: row address (bit line)
Douta[0]～douta[3]: 4 positions of the first input/output port 105
Doutb[0:3]～doutb[28:31]: 32 positions of the second input/output port 106
RED[0:7]: spare blocks IO[s] row address (bit line)
MUX8-1-1～MUX8-1-8, SMUX8-1: eight pairs of multiplexers
MUX2-1-1～MUX2-1-4, SEL2-1-1～SEL2-1-4: two pairs of multiplexers
MUX8-4-1～MUX8-4-8, SEL8-4-1～SEL8-4-8: eight pairs of four multiplexers
YA[2:0]: the least significant bit (LSB) of the row address signal of the first input/output port 105
YA[3]: the highest significant position of the row address signal of the first input/output port 105
YB[0]: the row address signal of the second input/output port 106
SA/IO1～SA/IO4: the bus pin of the first input/output port 105
SB/IO1～SB/IO8: the bus pin of the second input/output port 106
ASEL[0]～ASEL[3], BSEL[0]～BSEL[7]: control signal
301: two pairs of four decoding circuits
302: mutual exclusion or door
303～306: multiplexer
In[1:0], in[2:0]: the input pin
RED EN: two pairs of four decoding circuits 301 enable pin
Dec[0]～Dec[3], Dec[7:0]: the decoding pin
RED_AD[2], RED_AD[1:0]: the address of the memory cell sub-block of damage
401: three pairs of eight decoding circuits
Embodiment
Fig. 1 is the circuit block diagram of the imitative dual-port static random access memory that illustrates according to the embodiment of the invention.Please refer to Fig. 1, this imitative dual-port static random access memory comprises a memory cell array 101, a column address decoding circuit 102, a first row address decoding circuitry 103, one second row address decoding circuit 104, one first input/output port 105, one second input/output port 106, one first selection circuit 107 and one second selection circuit 108.
In this embodiment, the memory cell of memory cell array 101 is 6 traditional memory cells that electric crystal consists of, yet its bit line is coupled to two different row address decoding circuit 103,104 to consist of imitative dual-port static random access memory.Because this imitative dual-port static random access memory and fict dual-port static random access memory, its share same memory cell array 101, therefore, can not carry out access to the first input/output port 105 and the second input/output port 106 simultaneously.In general, imitative dual-port static random access memory is to utilize the different periods to carry out access through the first input/ output port 105 and 106 pairs of memory cell arrays of the second input/output port 101.
Yet because the progress of technique, the probability that position defectives (bit failure) occur for two above blocks is suitable low.In order to overcome the position defective in the SRAM cell, in this embodiment, above-mentioned a plurality of block of memory cells I/O[0]～I/O[k] all be split into again a plurality of sub-block, and spare blocks I/O[s] line position count n and the line position of above-mentioned sub-block to count n identical, namely the line number of spare blocks or memory cell counts are identical with line number or the memory cell counts of above-mentioned sub-block.When arbitrary above-mentioned sub-block has defective, just can write by the row address with this sub-block representative first control circuit 109 and second control circuit 112.Afterwards, as long as when receiving arbitrary input/ output port 105 or 106 and wanting the instruction of sub-block of the above-mentioned damage of accesses, first control circuit 109 or second control circuit 112 just can see through control above-mentioned multiplexer 111 or 114, make input/ output port 105 or 106 be electrically connected to spare blocks I/O[s].For the present invention more clearly is described, below enumerates again a detailed circuit according to the circuit of Fig. 1 and know that usually the knowledgeable can spirit according to the present invention implement the present invention so that affiliated technical field has.
Fig. 2 is the circuit block diagram of the imitative dual-port static random access memory that illustrates according to embodiment of the invention Fig. 1.Please refer to Fig. 2, for spirit of the present invention more clearly is described, in this embodiment, with 4 block of memory cells I/O[0]～I/O[3] for example, each block of memory cells I/O[0 wherein]～I/O[3] row address (bit line) BL[0:15 of 16 positions arranged], BL[16:31], BL[32:47], BL[48:63], the frequency range of the first input/output port 105 is 4 position douta[0]～douta[3], the frequency range of the second input/output port 106 is 32 position doutb[0:3]～doutb[28:31].In addition, in this embodiment, spare blocks IO[s] have row address (bit line) RED[0:7 of 8 positions].8 eight couples multiplexer MUX8-1-1～MUX8-1-8 of the first row address decoding circuitry 103 usefulness and 4 two couples multiplexer MUX2-1-1～MUX2-1-4 implement.8 eight couples four multiplexers MUX8-4-1 of the second row address decoding circuit 104 usefulness～MUX8-4-8 implements.One first selects eight couples of multiplexer SMUX8-1 of circuit 107 usefulness and 4 two couples multiplexer SEL2-1-1～SEL2-1-4 to implement.Second selects 8 eight couples four multiplexers SEL8-4-1 of circuit 108 usefulness～SEL8-4-8 to implement.
Structure according to this circuit, affiliated technical field has knows that usually the knowledgeable can find out, the design of this kind memory circuitry is the configuration that utilizes the multiplexer of the first row address decoding circuitry 103 and the second row address decoding circuit 104, with each block of memory cells I/O[0]～I/O[3] be divided into two memory cell sub-block, wherein, each memory cell sub-block comprises 8 row addresses (bit line), for example, first block of memory cells I/O[0] bit line BL[0:7] be coupled to first eight couple four multiplexer MUX8-4-1 and first eight couple one multiplexer MUX8-1-1, bit line BL[7:15] be coupled to second eight couples four multiplexer MUX8-4-2 and second eight couples multiplexer MUX8-1-2.
Each the eight couples multiplexer MUX8-1-1～MUX8-1-8 are according to least significant bit (LSB) (the Least Significant Bits of the row address signal of the first input/output port 105, LSB) part YA[2:0] come from block of memory cells I/O[0]～I/O[3] 8 row addresses of memory cell sub-block select 1 select row address, the two couples of multiplexer MUX2-1-1～MUX2-1-4 then are highest significant position (Most Significant Bits, MSB) the part YA[3 according to the row address signal of the first input/output port 105] select 1 output terminal that is electrically connected to two couples of multiplexer MUX2-1-1～MUX2-1-4 from the output terminal of its two eight couples multiplexer MUX8-1-1～MUX8-1-8 that couple.In addition, each the eight couples four multiplexer MUX8-4-1～MUX8-4-8 are according to the row address signal YB[0 of the second input/output port 106], from block of memory cells I/O[0]～I/O[3] 8 row addresses of memory cell sub-block select 4 select row addresses.
Suppose the block of memory cells I/O[0 of described imitative dual-port static random access memory]～I/O[3] do not damage, then then can be directly the bus pin SA/IO1～SA/IO4 of the first input/output port 105 to be electrically connected to its label be 0 input end for the two couples of multiplexer SEL2-1-1～SEL2-1-4, and it is electrically connected with two couples of multiplexer MUX2-1-1～MUX2-1-4; Same, it is 0 input bus that the eight couples of four multiplexer SEL8-4-1～SEL8-4-8 then can be directly be electrically connected to its label with the bus pin SB/IO1～SB/IO8 of the second input/output port 106, and it is electrically connected with eight couples of four multiplexer MUX8-4-1～MUX8-4-8.
Next, suppose when dispatching from the factory test, discovery is at the 16th bit lines～the 23rd bit lines BL[16:23] scope in a defective (bit failure) is arranged, in factory, just can utilize the mechanism of repairing this moment, make the highest significant position part YA[3 when the row address signal of the first input/output port 105] when being 0, control signal ASEL[1 then] be 1; In addition, make control signal BSEL[2] be 1.Therefore, no matter see through the first input/output port 105 and come access the 16th bit lines～the 23rd bit lines BL[16:23] the address or see through the second input/output port 105 and come access the 16th bit lines～the 23rd bit lines BL[16:23] the address, all can be forced to be electrically connected to spare blocks IO[s].Moreover, because spare blocks IO[s] eight couples, the one multiplexer SMUX8-1 that couples receives the least significant bit (LSB) part YA[2:0 of the row address signal of the first input/output port 105], spare blocks IO[s] eight couples, the four multiplexer SMUX8-4 that couple receive the row address signal YB[0 of the second input/output port 106], therefore, its chosen row address (bit line) should be identical with the relative address of the bit line of chosen sub-block (the 16th bit lines～the 23rd bit lines BL[16:23]), therefore, just can reach utilize spare blocks IO[s] replace section with fault position (the 16th bit lines～the 23rd bit lines BL[16:23]).
In the embodiment of Fig. 2, do not show output control signal ASEL[0]～ASEL[3] and BSEL[0]～BSEL[7] circuit.Below, just for above-mentioned two groups of control signal ASEL[0]～ASEL[3] and BSEL[0]～BSEL[7] the embodiment of control circuit know that usually the knowledgeable can implement the present invention according to spirit of the present invention so that affiliated technical field has.
Fig. 3 be according to the embodiment of the invention illustrate in order to export control signal ASEL[0]～ASEL[3] the circuit diagram of control circuit.Please refer to Fig. 3, this control circuit comprises one or two pairs of four decoding circuits 301, a mutual exclusion or 302 and 4 multiplexers 303～306 of door.Two pairs of four decoding circuits 301 have comprised two input pin in[1:0], one enable pin RED_EN and four decoding pin Dec[0]～Dec[3].For the running of the control circuit of the simple explanation embodiment of the invention, suppose at the 16th bit lines～the 23rd bit lines BL[16:23 equally] scope in the fault position is arranged.Next, in this embodiment, the sub-block of each block of memory cells is defined an address number, wherein, block of memory cells IO[0] bit line BL[0:7] address number be defined as 100; Block of memory cells IO[0] bit line BL[7:15] address number be defined as address 000; Block of memory cells IO[1] bit line BL[16:23] address number be defined as address 101; Block of memory cells IO[1] bit line BL[24:31] address number be defined as address 001; Block of memory cells IO[2] bit line BL[32:39] address number be defined as address 110; Block of memory cells IO[2] bit line BL[39:47] address number be defined as address 010; Block of memory cells IO[3] bit line BL[48:53] address number be defined as address 111; Block of memory cells IO[3] bit line BL[54:63] address number be defined as address 011.
Because the block with fault position is block of memory cells IO[1] first sub-block, bit line BL[16:23 namely], and RED_AD[2:0] be the address of the memory cell sub-block damaged of expression.According to above-mentioned, when testing out BL[16:23] when the fault position is arranged, bad block address number RED_AD[2:0] namely when dispatching from the factory, can be set to 101, that is to say RED_AD[2] be 1, RED_AD[1:0] be 01.In addition, be found when the fault position is arranged in test, fault position enable signal RED_EN just can be set to and enable, and the input end of decoding circuit 301 receives 01, just can make decoding pin Dec[1] the output logic high voltage.In addition, highest significant position part YA[3 when the row address signal of the first input/output port 105] when being 0, mutual exclusion or door 302 meeting output logic high voltages make multiplexer 303～306 select Dec[0]～Dec[3] as control signal ASEL[0]～ASEL[3], make ASEL[1] and be logic high voltage.Because ASEL[1] be logic high voltage, therefore the bus pin SA/IO2 of the first input/output port 105 can see through two couples of multiplexer SEL2-1-2 and be electrically connected to eight couples, the one multiplexer SMUX8-1 that spare blocks connects.
Fig. 4 be according to the embodiment of the invention illustrate in order to export control signal BSEL[0]～BSEL[7] the circuit diagram of control circuit.Please refer to Fig. 4, this control circuit is to implement with three pairs of eight decoding circuits 401.This three couple eight decoding circuits 401 have comprised three input pin in[2:0], one enable pin RED_EN and eight decoding pin Dec[7:0].Same reason is supposed at the 16th bit lines～the 23rd bit lines BL[16:23] scope in the fault position is arranged, and suppose that the sub-block of each block of memory cells is defined an address number as above.According to above-mentioned, when testing out BL[16:23] when the fault position is arranged, bad block address number RED_AD[2:0] namely when dispatching from the factory, can be set to 101.In addition, when being arranged in test, the fault position is found, fault position enable signal RED_EN just can be set to and enable, the input end of decoding circuit 401 receives 101, this moment decoding circuit 401 decoding pin Dec[5] be output as logic high voltage, all the other decoding pin Dec[0]～Dec[4] and Dec[6]～Dec[7] be logic low-voltage.Since address number as defined above, so Dec[7:0] with control signal BSEL[7:0] corresponding relation as shown in the table:
| Dec[0] | BSEL[1] | Dec[4] | BSEL[0] |
| Dec[1] | BSEL[3] | Dec[5] | BSEL[2] |
| Dec[2] | BSEL[5] | Dec[6] | BSEL[4] |
| Dec[3] | BSEL[7] | Dec[7] | BSEL[6] |
As can be seen from the above table, because above-mentioned design, to so that control signal BSEL[2] meeting output logic high voltage, therefore, the bus pin SB/IO3 of the second input/output port 106 can see through eight couples of four multiplexer SEL8-4-3 be electrically connected to eight couples, the four multiplexer SMUX8-4 that spare blocks connects.
Although above-described embodiment is with block of memory cells I/O[0]～I/O[3] to be divided into respectively two memory cell sub-block for example, yet having, affiliated technical field knows that usually the knowledgeable should be known in that being divided into several memory cell sub-block is the selection in the design.In addition, the first input/output port 105 also is according to different application from the frequency range size of the second input/output port 106, has different design alternatives.Should this present invention should be as limit.
In sum, spirit of the present invention is the position defective (bit failure) that the imitative dual-port static random access memory that is to utilize spare blocks reparation to can be applicable to have in the driving circuit of liquid crystal display two different frequency range input/output port may occur.The present invention can utilize the spare row block (redundant column) of lesser amt, and the mode that stores a small amount of bad block address (failed address) reduces the complexity of the needed spare blocks decoding of spare row block (redundancy decoding).Therefore, the present invention can reduce the needed layout area in shelf storage unit.
The specific embodiment that proposes in the detailed description of preferred embodiment is only in order to convenient explanation technology contents of the present invention, but not with narrow sense of the present invention be limited to above-described embodiment, in the situation that does not exceed spirit of the present invention and following claim, the many variations of doing is implemented, and all belongs to scope of the present invention.Therefore protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (10)
1. a repairable imitative dual-port static random access memory is characterized in that, described repairable imitative dual-port static random access memory comprises:
One memory cell array, comprise a plurality of block of memory cells and a spare blocks, each described block of memory cells is divided into a plurality of memory cell sub-block, and in addition, described spare area block size is identical with described memory cell sub-block;
One address decoding circuitry comprises:
One column address decoding circuit is according to the specified particular column of a column address, to open the described particular column of described memory cell array;
One the first row address decoding circuitry, connection bus with a N position, according to N specified the first particular row of the first row address signal, connect bus so that individual the first particular row of the described N in the described memory cell array is connected to the N position of described the first row address decoding circuitry, wherein N is natural number; And
One second row address decoding circuit, connection bus with a M position, according to M specified the second particular row of the second row address signal, so that being connected to the M position of described the second row address decoding circuit, individual the second particular row of the described M in the described memory cell array connects bus, wherein M is natural number, and M〉N;
One first input/output port has N position bus;
One second input/output port has M position bus;
One first selects circuit, the N position that couples described the first row address decoding circuitry connects the N position bus of bus and described the first input/output port, when one first specified particular row of described the first row address signal, when being positioned at the memory cell sub-block of a damage, then described first select circuit to select one first corresponding row of described spare blocks, and it is couple to the N position bus of described the first input/output port, the address of described the first particular row in the memory cell sub-block of the relative address of wherein said the first corresponding row and described damage is identical; And
One second selects circuit, the M position that couples described the second row address decoding circuit connects the M position bus of bus and described the second input/output port, when one second specified particular row of described the second row address signal, when being positioned at the memory cell sub-block of described damage, then described second select circuit to select one second corresponding row of described spare blocks, and it is couple to the M position bus of described the second input/output port, the address of described the second particular row in the memory cell sub-block of the relative address of wherein said the second corresponding row and described damage is identical.
2. repairable imitative dual-port static random access memory as claimed in claim 1, it is characterized in that, described memory cell array comprises that a block of memory cells, each block of memory cells comprise b memory cell sub-block, each memory cell sub-block comprises c row address, and then described the first row address decoding circuitry comprises:
A * b the first multiplexer, each described first multiplexer comprises c input end and d output terminal, wherein, c input end of the i * j the first multiplexer couples respectively c row address of j memory cell sub-block of i block of memory cells; And
A the second multiplexer, each described second multiplexer comprises b * d input end and d output terminal, wherein, the p of k the second multiplexer * 1～the p * d input end couples respectively the 1st～a d output terminal of the k * p the first multiplexer,
Wherein a, b, c, d, i, j, k, p belong to natural number; D * a=N; I and k between 0 and a between, j and p between 0 and b between; Each described first multiplexer is selected d row address according to the first of described the first row address signal, and a described d row address is electrically connected with its d output terminal; Each described second multiplexer from described b the multiplexer that it couples, is selected one of them specific multiplexer according to the second portion of described the first row address signal, and d output terminal of described specific multiplexer is electrically connected to its d output terminal.
3. repairable imitative dual-port static random access memory as claimed in claim 2 is characterized in that, described spare blocks comprises c row address, and described first selects circuit to comprise:
One the 3rd multiplexer, comprise c input end and d output terminal, wherein, the c of described the 3rd a multiplexer input end couples respectively c row address of spare blocks, and according to the first of described the first row address signal, select d row address, a described d row address is electrically connected with its d output terminal;
A the 4th multiplexer, each described the 4th multiplexer comprises control input end, first group of input end, second group of input end and d output terminal, wherein, its first group of input end and second group of input end comprise respectively d input end, first group of input end of u the 4th multiplexer couples d output terminal of u the second multiplexer, and second group of input end of each described the 4th multiplexer couples d output terminal of described the 3rd multiplexer; And
One first control circuit, comprise a control output end, couple respectively the control input end of described the 4th multiplexer, when specified described the first particular row of described the first row address signal, be positioned at y memory cell sub-block of v block of memory cells, and during the memory cell sub-block that y memory cell sub-block of v block of memory cells is described damage, v the 4th multiplexer controlled in v control output end of described first control circuit, make its second group of input be electrically connected to its d output
Wherein, v, y belong to natural number, and v between 0 and a between, y between 0 and b between.
4. repairable imitative dual-port static random access memory as claimed in claim 1, it is characterized in that, described memory cell array comprises that a block of memory cells, each block of memory cells comprise b memory cell sub-block, each memory cell sub-block comprises c row address, and then described the second row address decoding circuit comprises:
A * b the 5th multiplexer, each described the 5th multiplexer comprises c input end and x output terminal, wherein, c input end of the q * r the 5th multiplexer couples respectively c row address of r memory cell sub-block of q block of memory cells;
Wherein, a, b, c, x, q, r belong to natural number; X * a * b=M; Q between 0 and a between, r between 0 and b between; Each described the 5th multiplexer is selected x row address according to described the second row address signal, and a described x row address is electrically connected with its x output terminal.
5. repairable imitative dual-port static random access memory as claimed in claim 4 is characterized in that, described spare blocks comprises c row address, and described second selects circuit to comprise:
One the 6th multiplexer, comprise c input end and x output terminal, wherein, the c of described the 6th a multiplexer input end couples respectively c row address of spare blocks, and according to described the second row address signal, select x row address, a described x row address is electrically connected with its x output terminal;
A the 7th multiplexer, each described the 7th multiplexer comprises control input end, first group of input end, second group of input end and x output terminal, wherein, its first group of input end and second group of input end comprise respectively x input end, first group of input end of u the 7th multiplexer couples x output terminal of u the 5th multiplexer, and second group of input end of each described the 7th multiplexer couples x output terminal of described the 6th multiplexer; And
One second control circuit, comprise a control output end, couple respectively the control input end of described the 7th multiplexer, when specified described the second particular row of described the second row address signal, be positioned at z memory cell sub-block of w block of memory cells, and during the memory cell sub-block that z memory cell sub-block of w block of memory cells is described damage, then w the 7th multiplexer controlled in w control output end of described control circuit, makes its second group of input end be electrically connected to its x output terminal
Wherein, w, z belong to natural number, and w between 0 and a between, z between 0 and b between.
6. the fix-up circuit of an imitative dual-port static random access memory is characterized in that, described imitative dual-port static random access memory comprises:
One memory cell array comprises a plurality of block of memory cells, and wherein, each described block of memory cells is divided into a plurality of memory cell sub-block;
One address decoding circuitry comprises:
One column address decoding circuit is according to the specified particular column of a column address, to open the described particular column of described memory cell array;
One the first row address decoding circuitry, connection bus with a N position, according to N specified the first particular row of the first row address signal, connect bus so that individual the first particular row of the described N in the described memory cell array is connected to the N position of described the first row address decoding circuitry, wherein N is natural number; And
One second row address decoding circuit, connection bus with a M position, according to M specified the second particular row of the second row address signal, so that being connected to the M position of described the second row address decoding circuit, individual the second particular row of the described M in the described memory cell array connects bus, wherein M is natural number, and M〉N;
One first input/output port has N position bus;
One second input/output port has M position bus;
Described memory repair circuit comprises:
One spare blocks is disposed in the described memory cell array, and wherein, described spare area block size is identical with described memory cell sub-block;
One first selects circuit, the N position that couples described the first row address decoding circuitry connects the N position bus of bus and described the first input/output port, when one first specified particular row of described the first row address signal, when being positioned at the memory cell sub-block of a damage, then described first select circuit to select one first corresponding row of described spare blocks, and it is couple to the N position bus of described the first input/output port, the address of described the first particular row in the memory cell sub-block of the relative address of wherein said the first corresponding row and described damage is identical; And
One second selects circuit, the M position that couples described the second row address decoding circuit connects the M position bus of bus and described the second input/output port, when one second specified particular row of described the second row address signal, when being positioned at the memory cell sub-block of described damage, then described second select circuit to select one second corresponding row of described spare blocks, and it is couple to the M position bus of described the second input/output port, the address of described the second particular row in the memory cell sub-block of the relative address of wherein said the second corresponding row and described damage is identical.
7. the fix-up circuit of imitative dual-port static random access memory as claimed in claim 6, it is characterized in that, described memory cell array comprises that a block of memory cells, each block of memory cells comprise b memory cell sub-block, each memory cell sub-block comprises c row address, and then described the first row address decoding circuitry comprises:
A * b the first multiplexer, each described first multiplexer comprises c input end and d output terminal, wherein, c input end of the i * j the first multiplexer couples respectively c row address of j memory cell sub-block of i block of memory cells; And
A the second multiplexer, each described second multiplexer comprises b * d input end and d output terminal, wherein, the p of k the second multiplexer * 1～the p * d input end couples respectively the 1st～a d output terminal of the k * p the first multiplexer,
Wherein a, b, c, d, i, j, k, p belong to natural number; D * a=N; I and k between 0 and a between, j and p between 0 and b between; Each described first multiplexer is selected d row address according to the first of described the first row address signal, and a described d row address is electrically connected with its d output terminal; Each described second multiplexer from described b the multiplexer that it couples, is selected one of them specific multiplexer according to the second portion of described the first row address signal, and d output terminal of described specific multiplexer is electrically connected to its d output terminal.
8. the fix-up circuit of imitative dual-port static random access memory as claimed in claim 7 is characterized in that, described spare blocks comprises c row address, and described first selects circuit to comprise:
One the 3rd multiplexer, comprise c input end and d output terminal, wherein, the c of described the 3rd a multiplexer input end couples respectively c row address of spare blocks, and according to the first of described the first row address signal, select d row address, a described d row address is electrically connected with its d output terminal;
A the 4th multiplexer, each described the 4th multiplexer comprises control input end, first group of input end, second group of input end and d output terminal, wherein, its first group of input end and second group of input end comprise respectively d input end, first group of input end of u the 4th multiplexer couples d output terminal of u the second multiplexer, and second group of input end of each described the 4th multiplexer couples d output terminal of described the 3rd multiplexer; And
One first control circuit, comprise a control output end, couple respectively the control input end of described the 4th multiplexer, when specified described the first particular row of described the first row address signal, be positioned at y memory cell sub-block of v block of memory cells, and during the memory cell sub-block that y memory cell sub-block of v block of memory cells is described damage, v the 4th multiplexer controlled in v control output end of described first control circuit, make its second group of input be electrically connected to its d output
Wherein, v, y belong to natural number, and v between 0 and a between, y between 0 and b between.
9. the fix-up circuit of imitative dual-port static random access memory as claimed in claim 6, it is characterized in that, described memory cell array comprises that a block of memory cells, each block of memory cells comprise b memory cell sub-block, each memory cell sub-block comprises c row address, and then described the second row address decoding circuit comprises:
A * b the 5th multiplexer, each described the 5th multiplexer comprises c input end and x output terminal, wherein, c input end of the q * r the 5th multiplexer couples respectively c row address of r memory cell sub-block of q block of memory cells;
Wherein, a, b, c, x, q, r belong to natural number; X * a * b=M; Q between 0 and a between, r between 0 and b between; Each described the 5th multiplexer is selected x row address according to described the second row address signal, and a described x row address is electrically connected with its x output terminal.
10. the fix-up circuit of imitative dual-port static random access memory as claimed in claim 9 is characterized in that, described spare blocks comprises c row address, and described second selects circuit to comprise:
One the 6th multiplexer, comprise c input end and x output terminal, wherein, the c of described the 6th a multiplexer input end couples respectively c row address of spare blocks, and according to described the second row address signal, select x row address, a described x row address is electrically connected with its x output terminal;
A the 7th multiplexer, each described the 7th multiplexer comprises control input end, first group of input end, second group of input end and x output terminal, wherein, its first group of input end and second group of input end comprise respectively x input end, first group of input end of u the 7th multiplexer couples x output terminal of u the 5th multiplexer, and second group of input end of each described the 7th multiplexer couples x output terminal of described the 6th multiplexer; And
One second control circuit, comprise a control output end, couple respectively the control input end of described the 7th multiplexer, when specified described the second particular row of described the second row address signal, be positioned at z memory cell sub-block of w block of memory cells, and during the memory cell sub-block that z memory cell sub-block of w block of memory cells is described damage, then w the 7th multiplexer controlled in w control output end of described control circuit, makes its second group of input end be electrically connected to its x output terminal
Wherein, w, z belong to natural number, and w between 0 and a between, z between 0 and b between.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810128097 CN101640074B (en) | 2008-07-29 | 2008-07-29 | Memory repair circuit and imitative dual-port static random access memory using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810128097 CN101640074B (en) | 2008-07-29 | 2008-07-29 | Memory repair circuit and imitative dual-port static random access memory using same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101640074A CN101640074A (en) | 2010-02-03 |
| CN101640074B true CN101640074B (en) | 2013-01-23 |
Family
ID=41615008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810128097 Active CN101640074B (en) | 2008-07-29 | 2008-07-29 | Memory repair circuit and imitative dual-port static random access memory using same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101640074B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1155150A (en) * | 1995-10-31 | 1997-07-23 | 现代电子美国公司 | Storage unit with reduced number of fuse box |
| CN2640134Y (en) * | 2003-09-11 | 2004-09-08 | 北京华控技术有限责任公司 | Live bus network interconnection unit for connecting high-speed Ethernet and PROFIBUS-DP/PA bus |
-
2008
- 2008-07-29 CN CN 200810128097 patent/CN101640074B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1155150A (en) * | 1995-10-31 | 1997-07-23 | 现代电子美国公司 | Storage unit with reduced number of fuse box |
| CN2640134Y (en) * | 2003-09-11 | 2004-09-08 | 北京华控技术有限责任公司 | Live bus network interconnection unit for connecting high-speed Ethernet and PROFIBUS-DP/PA bus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101640074A (en) | 2010-02-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100483557C (en) | Circuit and method for test and repair | |
| US7808847B2 (en) | Memory repair circuit and repairable pseudo-dual port static random access memory | |
| CN100559501C (en) | Has semiconductor storage unit effective and that reliable redundancy is handled | |
| CN1819057B (en) | Dynamic random access memory with public pre-charger | |
| KR20020000836A (en) | Semiconductor memory device | |
| JPS59135700A (en) | Semiconductor storage device | |
| CN1114927C (en) | Storage unit with reduced number of fuse box | |
| US8477547B2 (en) | Semiconductor memory device and method of operating the same | |
| KR100349989B1 (en) | Semiconductor memory arrangement with bist | |
| CN101236791A (en) | Method, circuit and apparatus for multi-segment SRAM | |
| US6490210B2 (en) | Semiconductor memory integrated circuit employing a redundant circuit system for compensating for defectiveness | |
| KR101564848B1 (en) | A memory device comprising tiles with shared read and write circuits | |
| CN1264127A (en) | Semiconductor memory device with redundancy memory circuit | |
| CN101256832A (en) | SRAM design with separated VSS | |
| US7848164B2 (en) | Semiconductor memory device having redundancy memory block and cell array structure thereof | |
| US20210375379A1 (en) | Redundancy analysis circuit and memory system including the same | |
| US20200312423A1 (en) | Memory devices having spare column remap storages and methods of remapping column addresses in the memory devices | |
| WO2021056804A1 (en) | Memory and addressing method therefor | |
| US7605434B2 (en) | Semiconductor memory device to which test data is written | |
| CN101640074B (en) | Memory repair circuit and imitative dual-port static random access memory using same | |
| KR100621265B1 (en) | Storage device with redundant storage cells and method for accessing redundant storage cells | |
| US7196952B1 (en) | Column/sector redundancy CAM fast programming scheme using regular memory core array in multi-plane flash memory device | |
| US7990799B2 (en) | Semiconductor memory device that includes an address coding method for a multi-word line test | |
| US7386769B2 (en) | On chip diagnosis block with mixed redundancy | |
| Pekmestzi et al. | A bisr architecture for embedded memories |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |