CN101630900B - Control circuit for single-inductor multi-output system - Google Patents
Control circuit for single-inductor multi-output system Download PDFInfo
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- CN101630900B CN101630900B CN 200810045583 CN200810045583A CN101630900B CN 101630900 B CN101630900 B CN 101630900B CN 200810045583 CN200810045583 CN 200810045583 CN 200810045583 A CN200810045583 A CN 200810045583A CN 101630900 B CN101630900 B CN 101630900B
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Abstract
The invention provides a control circuit for controlling a single-inductor multi-output system, which adopts a first control loop to realize the peak mode control of system current, and adopts a second control loop to control the duty ratio of each switching device of a main circuit of the system by using the algebraic relation of each output of the system, thereby realizing the control of each output voltage of the system, reducing each output voltage ripple and optimizing the system performance.
Description
Technical field
The present invention relates to power converter, more particularly, the present invention relates to a kind of for single inductance multichannel power output converter circuit.
Background technology
Switching power circuit has obtained good application in a lot of fields.Wherein there are three kinds of circuit topologies the most common: buck, boost and buck-boost.When application requirements had multichannel output, single inductance multichannel power output converter technology was because only need to use an inductance, in that certain improvement is arranged aspect circuit cost, the circuit size, so be widely used.Existing single inductance multichannel output translator technology usually adopts " priority " to control.So-called priority, namely when system detected a certain road output voltage and falls lowlyer, subsequent some cycles were closed the respective switch device that export on other roads, and this road output voltage of separate compensation.This control method makes other outputs owing to continuous several cycles do not have the energy supply bigger ripple to occur easily, makes poor system performance.
Other list inductance multichannel output switch technology adopts digital control, and this control method is very complicated, and has increased cost.
Summary of the invention
Therefore the object of the present invention is to provide the control circuit of the single inductance multichannel of a kind of simple control output translator system, this control circuit comes the duty ratio of each switching device of control system main circuit with the algebraic relation of each output of system, realized the control of each output voltage of system, and reduced each output voltage ripple, optimized systematic function.
For achieving the above object, the invention discloses a kind of control circuit for the control single-induction and multi-output system, comprise first control loop, in order to the peak current of control system; Second control loop is in order to the duty cycle difference of control system main circuit switch device; Wherein said first control loop comprises a peak current controlled quentity controlled variable given circuit, an adder, one first comparator, a ramp signal generator, first logical circuit and second logical circuit; Wherein system multi-channel output sampled value is connected to a plurality of inputs of described peak current controlled quentity controlled variable given circuit respectively, the output of described peak current controlled quentity controlled variable given circuit is connected to an input of described first comparator, the output of described ramp signal generator is connected to an input of described adder, system's inductive current sampled value is connected to another input of described adder, the output of described adder is connected to another input of described first comparator, the output of described first comparator is connected to an input of described first logical circuit, the output of described first logical circuit is connected to first and second inputs of described second logical circuit, and a plurality of outputs of described second logical circuit are connected to the gate pole control end of a plurality of switching devices of system's main circuit respectively; Described second control loop comprises switching device duty cycle difference control circuit and described second logical circuit, wherein system multi-channel output sampled value is connected to a plurality of inputs of described switching device duty cycle difference control circuit, first output of described switching device duty cycle difference control circuit is connected to the four-input terminal of described second logical circuit, second output of described switching device duty cycle difference control circuit is connected to the 3rd input of described second logical circuit, and a plurality of outputs of described second logical circuit are connected to the gate pole control end of a plurality of switching devices of system's main circuit respectively.
A kind of control circuit as described in the present invention, wherein said peak current controlled quentity controlled variable given circuit comprises a plurality of operational amplifiers and a first arithmetic device, the number of operational amplifier is determined by the way of system's output; The sampled value of an input receiving system one tunnel output of described each operational amplifier, its another input receives the reference level of corresponding system output, and its output is connected to an input of described first arithmetic device; The output of described first arithmetic device is connected to another input of described first comparator as the output of described peak current controlled quentity controlled variable given circuit.Wherein said ramp signal generator is an oscillator, and described oscillator is exported a ramp signal and a clock signal, and described ramp signal is connected to an input of described adder, and described clock signal is connected to another input of described logical circuit.
A kind of control circuit as described in the present invention, wherein said first logical circuit is a rest-set flip-flop.
A kind of control circuit as described in the present invention, wherein said second logical circuit comprise one first or the door, one second or the door, one first resistance, one second resistance, one first switch, one second switch, one end of described first resistance be connected to described first or the door an input and an end of described first switch, one end of described second resistance be connected to described second or the door an input and an end of described second switch, the other end ground connection of described first resistance and described second resistance, the other end of described first switch and the other end of described second switch link together as the 3rd input of described second logical circuit, be connected to second output of described switching device duty cycle difference control circuit, the control end of described first switch and the control end of described second switch link together as the four-input terminal of described second logical circuit, are connected to first output of described switching device duty cycle difference control circuit.
A kind of control circuit as described in the present invention, wherein said switching device duty cycle difference control circuit comprises a second arithmetic device, one second operational amplifier, an absolute value circuit, second comparator, the 3rd comparator and a sawtooth generator; The sampled value of wherein said second arithmetic device receiving system multichannel output, its output is connected to an input of described second operational amplifier, another input end grounding of described second operational amplifier, its output is connected to the input of described absolute value circuit and an input of described the 3rd comparator, another input end grounding of described the 3rd comparator, its output is connected to the four-input terminal of second logical circuit as first output of described switching device duty cycle difference control circuit, the output of described absolute value circuit is connected to an input of described second comparator, the output of described first comparator is connected to the input of described sawtooth generator, the output of described sawtooth generator is connected to another input of described second comparator, and the output of described second comparator is connected to the 3rd input of second logical circuit as described second lead-out terminal of described switching device duty cycle difference control circuit.
A kind of control circuit as described in the present invention, wherein said sawtooth generator comprises a current source, an electric capacity and a switch, the control end of described switch is as the input of described sawtooth generator, be connected to the output of described first comparator, the output of described current source is connected to the inverting input of described second comparator as the output of described sawtooth generator, the output of described current source is connected to an end of described electric capacity and an end of described switch, the other end ground connection of the other end of described switch and described electric capacity simultaneously.
A kind of control circuit as described in the present invention, the trailing edge of the sawtooth signal that wherein said sawtooth generator produces and the peak value of system's inductive current are synchronous.
The invention has the advantages that this control circuit comes the duty ratio of each switching device of control system main circuit simply with the algebraic relation of each output of system, realized the control of each output voltage of system, and reduced each output voltage ripple, optimized systematic function.
Description of drawings
Fig. 1 is the main circuit diagram of a typical single inductance two-way output system.
Inductive current waveform and switching device control signal thereof when Fig. 2 (a) is in situation 1 for circuit shown in Figure 1 under the continuous mode.
Inductive current waveform and switching device control signal thereof when Fig. 2 (b) is in situation 2 for circuit shown in Figure 1 under the continuous mode.
Inductive current waveform and switching device control signal thereof when Fig. 2 (c) is in situation 1 for circuit shown in Figure 1 under the discontinuous mode.
Inductive current waveform and switching device control signal thereof when Fig. 2 (d) is in situation 2 for circuit shown in Figure 1 under the discontinuous mode.
Fig. 3 is the control circuit figure of circuit shown in Figure 1 place system.
The oscillogram of corresponding control circuit each point when Fig. 4 (a) is in situation 1 for circuit shown in Figure 1.
The oscillogram of corresponding control circuit each point when Fig. 4 (b) is in situation 2 for circuit shown in Figure 1.
Embodiment
Fig. 1 is the main circuit diagram of a typical single inductance two-way output system.As shown in Figure 1, main circuit comprises input V
IN, output V
PAnd V
N, inductance L, capacitor C
1, C
2, switching device M
1, M
2, and diode D
1, D
2Input V
INBe connected to switching device M
1Drain electrode, switching device M
1Source electrode be connected to an end and the diode D of inductance L
2Negative electrode, the other end of inductance L is connected to diode D
1Anode and switching device M
2Drain electrode, diode D
1Negative electrode be connected to output V
P, diode D
2Anode be connected to output V
N, switching device M
2Source ground, switching device M
1And M
2Gate pole be connected to control circuit, will specifically set forth when this introduces Fig. 4 in the back.At output V
PAnd cross-over connection has capacitor C between the ground
1, at output V
NAnd cross-over connection has capacitor C between the ground
2, output V
PWith output V
NCan connect load.In the present embodiment, switching device M
1With switching device M
2Adopt N-channel MOS FET, but those skilled in the art will appreciate that switching device M
1And M
2Be not limited to such combination, they can be other forms of combinations, even switching device M
1And M
2Be not limited to the MOSFET pipe, they can be other forms of switching devices, as triode, IGBT etc., and while diode D
1With diode D
2Also can replace with these switching devices.And main circuit can multichannel be exported, and is not limited in the two-way output in the present embodiment, also is not limited to the topological structure of present embodiment, can be the topological structure of other single inductance multiplex output circuits.Switching device M
1With diode D
2Complementary open-minded, switching device M
2With diode D
1Complementary open-minded.When circuit working during at continuous mode (CCM), a switch periods can be divided into 3 branch cycles, shown in Fig. 2 (a) and Fig. 2 (b), i.e. and 0～t
0, t
0～t
1, t
1～T.At the 1st fen cycle 0～t
0In, switching device M
1And M
2Conducting simultaneously, diode D
1, D
2Turn-off simultaneously, import V this moment
IN, switching device M
1, inductance L, switching device M
2Form current circuit, inductive current I
LWith V
INThe slope of/L is linear to be increased, input V
INProvide energy to inductance L.At second fen cycle t
0～t
1In, have two kinds of situations: situation 1 is switching device M
1Conducting, diode D
1Afterflow, switching device M
2, diode D
2All close.Import V this moment
IN, switching device M
1, inductance L, diode D
1And capacitor C
1Form current circuit.Shown in Fig. 2 (a), inductive current I
LWith (V
P-V
INThe slope of)/L is linear to descend, input V
INGive capacitor C with inductance L
1Provide energy with load, to obtain the output V of system
PSituation 2 is switching device M
2Conducting, diode D
2Afterflow, switching device M
1, diode D
1All turn-off, at this moment inductance L, switching device M
2, capacitor C
2And diode D
2Form current circuit.Shown in Fig. 2 (b), inductive current I
LWith V
NThe slope of/L is linear to descend, and inductance L is given capacitor C
2Provide energy with load, to obtain the output V of system
NCan see C
2Just, namely export V under negative on the voltage
NBe negative voltage.At the 3rd fen cycle t
1In～the T, switching device M
1, M
2Turn-off diode D simultaneously
1With diode D
2Afterflow, inductance L, diode D at this moment
1, capacitor C
1, diode D
2And capacitor C
2Form current circuit, inductive current I
LWith (V
P-V
NThe slope of)/L is linear to descend, and inductance L continues to capacitor C
1, capacitor C
2Provide energy with load.Above-mentioned three branch cycles constitute the work period of this single inductance two-way output system together.
Fig. 3 is the control circuit figure of single inductance two-way output system for this reason.As shown in Figure 3, control circuit has the two-way control loop, comes control switch device M
1, M
2Conducting and shutoff.First control loop control inductive current I
LPeak value, also namely control first fen cycle 0～t
0Length, second fen cycle t of second control loop control
0～t
1Length, namely control the poor of two switching device duty ratios, and two kinds of situations in second fen cycle selected.First control loop comprises peak current controlled quentity controlled variable given circuit 1, adder 2, first comparator 3, ramp signal generator 4, first logical circuit 5 and second logical circuit 6; In the present embodiment, peak current controlled quentity controlled variable given circuit 1 comprises operational amplifier U
0, U
1With first arithmetic device 11.In the present embodiment, first arithmetic device 11 is adder A
0Adder 2 is adder A
2First comparator 3 is comparator U3; Ramp signal generator 4 is oscillator OSC; First logical circuit 5 is rest-set flip-flop U
8Second logical circuit 6 comprise first or the door U
6, second or the door U
7, first switch S
1, second switch S
2, and first resistance R
1, second resistance R
2Second control loop comprises switching device duty cycle difference control circuit 7 and second logical circuit 6; In the present embodiment, switching device duty cycle difference control circuit 7 comprises adder A
1(being second arithmetic device 71), the second operational amplifier U
2, absolute value circuit ABS, comparator U
4, U
5(i.e. second comparator 73, the 3rd comparator 74), current source Is, capacitor C
0And switch S
3Operational amplifier U
0In-phase input end receive reference level V
Ref_P, inverting input receiving system output V
PSampled value V
P '(the systematic sampling circuit is not shown), the output V of system
PSampled value V
P 'With reference level V
Ref_PError by operational amplifier U
0Deliver to adder A after the amplification
0An input.Operational amplifier U
1Inverting input receive reference level V
Ref_N, in-phase input end receiving system output V
NSampled value V
N ', the output V of system
NSampled value V
N 'With reference level V
Ref_NError by operational amplifier U
1Deliver to adder A after the amplification
0Another input.Adder A
0To operational amplifier U
0And U
1Output carry out after the addition result being delivered to comparator U
3Inverting input.Adder A
2A terminal receiving key device M
2Sample rate current I
M, as can be known at first fen cycle 0～t
0In, switching device M
2Electric current I
MEqual the inductive current I of system
LSo, switching device M
2Electric current I
MPeak value be exactly inductive current I
LPeak value.Those skilled in the art will appreciate that adder A
2Receiving key device M
2Electric current I
MInput also can receiving system inductive current I
LAdder A
2The sawtooth waveforms output of another terminal reception oscillator OSC, adder A
2Both are carried out after the addition result being delivered to comparator U
3In-phase input end.Comparator U
3Output be connected to rest-set flip-flop U
8Reset terminal R and switch S
3Control end.The output of the clock of the set end S reception oscillator OSC of rest-set flip-flop, its output Q is connected to first or door U
6First input end (i.e. the first input end of second logical circuit 6) and second or the door U
7First input end (i.e. second input of second logical circuit 6).Adder A
1Input receiving system output V
PSampled value V
P ', another input receiving system output V
NSampled value V
N ', adder A
1Both are carried out after the addition result being delivered to the second operational amplifier U
2In-phase input end.Those skilled in the art will appreciate that the adder A in the present embodiment
0With adder A
1Can be other arithmetic units, can be β as the output of A1
1* V
P '+ β
2* V
N ', β here
1And β
2Be a coefficient, different values can be set according to different systems, and can get negative value; The operational amplifier number of first control loop is determined by the way of system's output simultaneously, and this embodiment thinks two operational amplifier U for two-way output, institute
0, U
1In second control loop, the second operational amplifier U
2Reverse inter-input-ing ending grounding, its output is connected to input and the comparator U of absolute value circuit ABS
5In-phase input end, comparator U
5Reverse inter-input-ing ending grounding, its output (being first output of switching device duty cycle difference control circuit 7) connects the four-input terminal of second logical circuit 6, is used for control first switch S
1With second switch S
2Closure and shutoff.The output of absolute value circuit ABS is connected to the in-phase input end of comparator U4, comparator U
4Inverting input connect output G and the capacitor C of current source Is
0An end.Capacitor C
0Other end ground connection, the output G of current source Is is connected to switch S simultaneously
3An end, switch S
3Other end ground connection, this current source Is, capacitor C
0And switch S
3Constitute sawtooth generator 75, the trailing edge of the sawtooth signal that this sawtooth generator 75 produces and the peak value of system's inductive current are synchronous.The output of comparator U4 (being second output of switching device duty cycle difference control circuit 7) is connected to first switch S
1With second switch S
2An end (i.e. the 3rd input of second logical circuit 6).First switch S
1The other end be connected to first or the door U
6Second input and first resistance R
1An end; Second switch S
2The other end be connected to second or the door U
7Second input and second resistance R
2An end.First or the door U
6Output G
1Be connected to the main circuit part switching device M of system
1The gate pole control end, in order to control switch device M
1Conducting and shutoff; Second or the door U
7Output G
2Be connected to the main circuit part switching device M of system
2The gate pole control end, in order to control switch device M
2Conducting and shutoff.First resistance R
1With second resistance R
2Other end ground connection.The operation principle of system, control circuit is as follows:
Fig. 4 (a) is the oscillogram of system works control circuit each point when the cycle was in situation 1 in second minute.Fig. 4 (b) is the oscillogram of system works control circuit each point when the cycle was in situation 2 in second minute.Each cycle is when beginning, i.e. t
0Constantly, oscillator OSC clock signal C triggers the set end S of rest-set flip-flop, so the output Q of rest-set flip-flop is put height, namely signal D is put height, and first or door U
6With second or the door U
7Output G
1With G
2Be high level because D puts height, thereby make the switching device M of system's main circuit
1And M
2Be switched on, this moment, main circuit was partly imported V
IN, switching device M
1, inductance L, switching device M
2Form current circuit, inductive current I
LWith V
INThe slope of/L rises, input V
INProvide energy to inductance L, work enters first fen cycle 0～t
0At adder A
2The place, it is with switching device M
2Electric current I
MSampled value and the sawtooth signal of oscillator OSC carry out addition, and export addition result to comparator U
3In-phase input end, the sawtooth signal of oscillator OSC plays the slope-compensation effect herein.At adder A
0The place, it is with operational amplifier U
0With operational amplifier U
1Output signal carry out addition and obtain adder output signal A, as switching device M
2Electric current I
MContinue to increase, so that adder A
2Output signal during greater than signal A, i.e. t
0Constantly, comparator U
3Output signal B becomes height, because peak-current mode, switching device M are adopted in this loop
2Electric current I
MSampled value become decline after contacting the level of signal A, so in fact signal B is a short pulse.This moment, the signal B rest-set flip-flop that resets made the output Q step-down of rest-set flip-flop, also was signal D step-down, so first or door U
6With second or the door U
7Output determined by the input signal of its second input terminal.And as shown in Figure 3, first switch S
1With second switch S
2Control end by signal H control, and first switch S
1Control end is that low level control is open-minded, realizes switch closure; Second switch S
2Control end is that high level control is open-minded, realizes switch closure.Be that both are not open-minded simultaneously, therefore first or door U
6Output G
1With second or the door U
7Output G
2Having only one of them at most is high level, so system works enters second fen cycle t
0～t
1Signal B is simultaneously with switch S
3Closure, current source Is output G is pulled to ground, capacitor C
0The two ends electric charge is discharged rapidly, makes its both end voltage vanishing.And after the short pulse of signal B finishes, during its level step-down, switch S
3Disconnect the capacitor C of current source Is
0Charge, the output G of current source Is is sawtooth waveforms thus, current source Is, capacitor C
0And switch S
3Come down to a sawtooth generator.This output sawtooth waveforms is connected to comparator U
4Inverting input.One skilled in the art would recognize that the sawtooth waveforms production method can be used other sawtooth generators in the present embodiment, and be not limited only to present embodiment by current source Is, capacitor C
0And switch S
3The sawtooth generator of forming.As the output V of system
PSampled value V
P 'Amplitude less than output V
NSampled value V
N 'Amplitude, adder A then
1Be output as negative, the second operational amplifier U
2Output signal E also for negative, cause comparator U
5Output signal H step-down.This moment, signal H was with first switch S
1Closure, second switch S
2Disconnect, so first or door U
6Receive comparator U
4Output signal I, and second or the door U
7With comparator U
4Output signal I disconnect to connect.At absolute value circuit ABS place, its output signal F just becomes behind the negative signal E process absolute value circuit ABS.So at comparator U
4The place, the sawtooth signal that its inverting input receives increases but still during less than signal F, comparator U
4Output signal I is being for just, this moment first or door U
6Output G
1For just, the switching device M of main circuit part
1Conducting, and this moment switching device M
2Turn-off, so system works enters the situation 1 in second fen cycle: i.e. main circuit part switching device M
1Conducting, diode D
1Afterflow, switching device M
2, diode D
2All close, import V this moment
IN, switching device M
1, inductance L, diode D
1And capacitor C
1Form current circuit, inductive current I
LWith (V
P-V
INThe slope of)/L is linear to descend, input V
INGive capacitor C with inductance L
1Provide energy, with the output V of increase system
P, shown in Fig. 4 (a).As the output V of system
PSampled value V
P 'Amplitude greater than output V
NSampled value V
N 'Amplitude, adder A then
1Just be output as the second operational amplifier U
2Output signal E also for just, cause comparator U
5Output signal H uprise.This moment, signal H was with first switch S
1Disconnect second switch S
2So closure is or door U
7Receive comparator U
4Output signal I, and first or the door U
6With comparator U
4Output signal I disconnect to connect.At absolute value circuit ABS place, positive signal E through absolute value circuit ABS after its output signal F also for just.So at comparator U
4The place, the sawtooth signal that its inverting input receives increases but still during less than signal F, and comparator U4 output signal I is being for just, this moment second or a U
7Output G
2For just, the switching device M of main circuit part
2Conducting, and this moment switching device M
1Turn-off, so system works enters the situation 2 in second fen cycle: i.e. main circuit part switching device M
2Conducting, diode D
2Afterflow, switching device M
1, diode D
1All close, at this moment inductance L, switching device M
2, capacitor C
2And diode D
2Form current circuit, inductive current I
LWith V
NThe slope of/L is linear to descend, and inductance L is given capacitor C
2Energy is provided, bears the positive down output V of system to increase to go up
NAmplitude is shown in Fig. 4 (b).When the sawtooth waveforms of signal G continues to increase until greater than signal F the time, i.e. t
1Constantly, comparator U
4The output signal step-down.This moment is first switch S no matter
1Perhaps second switch S
2Closure, first or the door U
6Output G
1With second or the door U
7Output G
2Be low level, so the switching device M of main circuit
1And M
2All be turned off diode D
1, D
2Afterflow, system works enter the 3rd fen cycle t
1～T.This moment inductance L, diode D
1, capacitor C
1, diode D
2And capacitor C
2Form current circuit, inductive current I
LWith (V
P-V
NThe slope of)/L is linear to descend, and inductance L continues to capacitor C
1, capacitor C
2Energy is provided.Until T constantly, oscillator OSC is clock signal C again, and system enters a new cycle, repeats foregoing operating state.When circuit working during in discontinuous mode (DCM), situation 1 and circuit state under the situation 2 as Fig. 2 (c) with shown in Fig. 2 (d): the operating state in first fen cycle and second fen cycle is worked as t with the same down at continuous mode (CCM)
1System works enters the 3rd fen all after date constantly, at t
2Constantly, inductive current I
LDrop to zero, diode D
1, D
2No longer afterflow, and this moment switching device M
1, M
2Disconnect, thus this moment capacitor C
1And C
2Energy is provided for respectively load separately.Until T constantly, oscillator OSC is clock signal C again, and system enters a new cycle, repeats foregoing operating state.
By the said system operating state as seen, at first fen cycle 0～t of system works
0, switching device M
1And M
2All conductings are at second fen cycle t of system works
0～t
1, switching device M
1And M
2One of them conducting, a disconnection is at the 3rd fen cycle t of system works
1～T, switching device M
1And M
2All disconnect.So the present invention has realized controlling with the algebraic relation of each output of single-induction and multi-output system the duty ratio of each switching device, thus realized the control of each output voltage of system, and reduced voltage ripple, optimized systematic function.
What need statement is that foregoing invention content and embodiment are intended to prove the practical application of technical scheme provided by the present invention, should not be construed as the restriction to protection range of the present invention.Those skilled in the art are in spirit of the present invention and principle, when doing various modifications, being equal to and replacing or improve.Protection scope of the present invention is as the criterion with appended claims.
Claims (8)
1. control circuit that is used for single inductance two-way output system comprises:
First control loop is in order to control the peak current of described single inductance two-way output system;
Second control loop is in order to control the duty cycle difference of described single inductance two-way output system main circuit switch device;
It is characterized in that described first control loop comprises
One peak current controlled quentity controlled variable given circuit (1), an adder (2), one first comparator (3), a ramp signal generator (4), first logical circuit (5) and second logical circuit (6);
Wherein said single inductance two-way output system two-way output sampled value is connected to two inputs of described peak current controlled quentity controlled variable given circuit (1) respectively, the output of described peak current controlled quentity controlled variable given circuit (1) is connected to an input of described first comparator (3), the output of described ramp signal generator (4) is connected to an input of described adder (2), described single inductance two-way output system inductive current sampled value is connected to another input of described adder (2), the output of described adder (2) is connected to another input of described first comparator (3), the output of described first comparator (3) is connected to an input of described first logical circuit (5), the output of described first logical circuit (5) is connected to first and second inputs of described second logical circuit (6), and two outputs of described second logical circuit (6) are connected to the gate pole control end of two switching devices of described single inductance two-way output system main circuit respectively;
Described second control loop comprises switching device duty cycle difference control circuit (7) and described second logical circuit (6), wherein said single inductance two-way output system two-way output sampled value is connected to two inputs of described switching device duty cycle difference control circuit (7), first output of described switching device duty cycle difference control circuit (7) is connected to the four-input terminal of described second logical circuit (6), and second output of described switching device duty cycle difference control circuit (7) is connected to the 3rd input of described second logical circuit (6).
2. the control circuit for single inductance two-way output system as claimed in claim 1 is characterized in that, wherein said peak current controlled quentity controlled variable given circuit (1) comprises two operational amplifiers and a first arithmetic device (11); An input of each operational amplifier receives the sampled value of described single inductance two-way output system one tunnel output, its another input receives the reference level of corresponding described single inductance two-way output system output, and its output is connected to an input of described first arithmetic device (11); The output of described first arithmetic device (11) is connected to an input of described first comparator (3) as the output of described peak current controlled quentity controlled variable given circuit (1).
3. the control circuit for single inductance two-way output system as claimed in claim 1, it is characterized in that, wherein said ramp signal generator (4) is an oscillator, described oscillator is exported a ramp signal and a clock signal, described ramp signal is connected to an input of described adder (2), and described clock signal is connected to another input of described first logical circuit (5).
4. the control circuit for single inductance two-way output system as claimed in claim 1 is characterized in that, wherein said first logical circuit (5) is a rest-set flip-flop.
5. the control circuit for single inductance two-way output system as claimed in claim 1, it is characterized in that, wherein said second logical circuit (6) comprise one first or the door, one second or the door, one first resistance, one second resistance, one first switch, one second switch, one end of described first resistance be connected to described first or the door an input and an end of described first switch, one end of described second resistance be connected to described second or the door an input and an end of described second switch, the other end ground connection of described first resistance and described second resistance, the other end of described first switch and the other end of described second switch link together as the 3rd input of described second logical circuit (6), be connected to second output of described switching device duty cycle difference control circuit (7), the control end of described first switch and the control end of described second switch link together as the four-input terminal of described second logical circuit (6), are connected to first output of described switching device duty cycle difference control circuit (7); Described first or another input of door as the first input end of described second logical circuit (6), described second or another input of door as second input of described second logical circuit (6).
6. the control circuit for single inductance two-way output system as claimed in claim 1, it is characterized in that wherein said switching device duty cycle difference control circuit (7) comprises a second arithmetic device (71), one second operational amplifier (72), an absolute value circuit, one second comparator (73), one the 3rd comparator (74) and a sawtooth generator (75); Wherein said second arithmetic device (71) receives the sampled value of described single inductance two-way output system two-way output, its output is connected to an input of described second operational amplifier (72), another input end grounding of described second operational amplifier (72), its output is connected to the input of described absolute value circuit and an input of described the 3rd comparator (74), another input end grounding of described the 3rd comparator (74), its output is connected to the four-input terminal of described second logical circuit (6) as first output of described switching device duty cycle difference control circuit (7), the output of described absolute value circuit is connected to an input of described second comparator (73), the output of described first comparator (3) is connected to the input of described sawtooth generator (75), the output of described sawtooth generator (75) is connected to another input of described second comparator (73), and the output of described second comparator (73) is connected to the 3rd input of described second logical circuit (6) as second output of described switching device duty cycle difference control circuit (7).
7. the control circuit for single inductance two-way output system as claimed in claim 6, it is characterized in that, wherein said sawtooth generator (75) comprises a current source, one electric capacity and a switch (750), the control end of described switch (750) is as the input of described sawtooth generator (75), be connected to the output of described first comparator (3), one end of described electric capacity is connected to another input of described second comparator (73) as the output of described sawtooth generator (75), one end of described electric capacity is connected to the output of described current source and an end of described switch (750), the other end of described switch (750) and the other end ground connection of described electric capacity simultaneously.
8. the control circuit for single inductance two-way output system as claimed in claim 7 is characterized in that, the trailing edge of the sawtooth signal that wherein said sawtooth generator (75) produces and the peak value of described single inductance two-way output system inductive current are synchronous.
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| CN 200810045583 CN101630900B (en) | 2008-07-17 | 2008-07-17 | Control circuit for single-inductor multi-output system |
| US12/505,399 US8164218B2 (en) | 2008-07-17 | 2009-07-17 | Power converters and associated methods of control |
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| CN 200810045583 CN101630900B (en) | 2008-07-17 | 2008-07-17 | Control circuit for single-inductor multi-output system |
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| CN104158399B (en) * | 2014-08-27 | 2017-01-18 | 圣邦微电子（北京）股份有限公司 | Single-inductor positive and negative voltage output device |
| CN104393744B (en) * | 2014-12-05 | 2017-09-29 | 郭智峰 | Digitize peak current control device |
| CN106444951B (en) * | 2016-10-13 | 2018-06-26 | 复旦大学 | Ultrahigh speed heavy current pulse formula constant-current source |
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