CN101630653A - Method of manufacturing microelectronic device and semiconductor device applying the method - Google Patents
Method of manufacturing microelectronic device and semiconductor device applying the method Download PDFInfo
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- CN101630653A CN101630653A CN200910000109.4A CN200910000109A CN101630653A CN 101630653 A CN101630653 A CN 101630653A CN 200910000109 A CN200910000109 A CN 200910000109A CN 101630653 A CN101630653 A CN 101630653A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Element Separation (AREA)
Abstract
The present disclosure provides a method of manufacturing a microelectronic device and a semi-conductor device applying the method. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings. The semi-conductor device includes recessed shallow trench isolation features, a tunnel dielectric feature, a silicon nitride layer, and silicon oxide layer.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, particularly relate to a kind of non-flat semiconductor memory (memory is a memory body, below all be called memory) device and manufacture method thereof.
Background technology
At integrated circuit (Integrated Circuit; IC) in the device, present non-planar NAND gate (NAND) memory architecture is to use shallow trench isolation (the Shallow TrenchIsolation of depression; STI) form finfet-like effect transistor (FinFET-Like) memory cell, use and overcome the yardstick obstacle (ScalingBarrier) that surmounts 45 nm technology node in the plane NAND gate memory.Yet nitride in the finfet-like effect transistor unit stores layer and contact with the oxide material of shallow trench isolation, when the nitride storage layer is being conducted electricity, can increase considering that electric charge keeps.
This shows that above-mentioned existing finfet-like effect transistor memory cell and manufacture method thereof obviously still have inconvenience and defective, and demand urgently further being improved in product structure, method and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product and method do not have appropriate structure and method to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of method of new manufacturing microelectronic device and the semiconductor device of adopting said method, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Therefore, need provide a kind of non-planar memory cell and manufacture method thereof that does not have the improvement of above-mentioned shortcoming.
Summary of the invention
The objective of the invention is to, overcome the defective that existing finfet-like effect transistor memory cell manufacture method exists, and provide a kind of method of new manufacturing microelectronic device, technical problem to be solved is to make it utilize the nitride etching layer to form the nitride opening, by this nitride opening portion remove the shallow trench isolation feature that is positioned under the nitride layer, make and form the gap between the packing material of nitride layer and shallow trench isolation feature, can avoid increasing considering that electric charge keeps, be very suitable for practicality.
Another object of the present invention is to, overcome the defective that existing finfet-like effect transistor memory cell manufacture method exists, and provide a kind of method of new manufacturing microelectronic device, technical problem to be solved is to make it utilize the silicon nitride layer of etching high silicon content to form opening, be positioned at trench isolation feature under the open bottom by this opening etching, contacting between the silicon nitride layer that reduces high silicon content and the packing material of trench isolation feature, can avoid increasing considering that electric charge keeps, thereby be suitable for practicality more.
A further object of the present invention is, overcome the defective that existing finfet-like effect transistor memory cell exists, and provide a kind of semiconductor device of new structure, technical problem to be solved is to make it to be positioned at the silicon oxide layer of shallow-channel isolation region, intert between shallow trench isolation feature and silicon nitride layer, wherein silicon oxide layer isolates the sidewall of silicon nitride layer from semiconductor substrate, forms by this can to reduce electric charge and keep the structure of considering, thereby is suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of method of making microelectronic device according to the present invention's proposition, it may further comprise the steps at least: the shallow trench isolation features that form most depressions in the semiconductor base material, and definition semiconductor district in the shallow trench isolation feature of those depressions adjacent the two; Form one and wear the tunnel dielectric characterization within this semiconductor region; Forming the mononitride layer wears on the tunnel dielectric characterization in the shallow trench isolation feature of those depressions and this; This nitride layer of etching is to form in the shallow trench isolation feature that a plurality of nitride are opened on those depressions; Partly remove the shallow trench isolation feature of those depressions by those nitride openings, and produce most gaps between between the shallow trench isolation feature of this nitride layer and those depressions; And form most the surfaces of one first dielectric material, and seal those nitride openings in this nitride layer.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The method of aforesaid manufacturing microelectronic device comprises more at least: after this partly removes the step of shallow trench isolation feature of those depressions; And before this forms the step of this first dielectric material, form a thin dielectric layer in those surfaces of this nitride layer and most sidewalls of this semiconductor substrate.
The method of aforesaid manufacturing microelectronic device, the step of wherein said formation one thin dielectric layer comprises: use basic root oxidation process to form a thin silicon oxide layer.
The method of aforesaid manufacturing microelectronic device, the step of the shallow trench isolation feature of most depressions of wherein said formation comprises: form most irrigation canals and ditches in this semiconductor substrate; And one second dielectric material is filled in those irrigation canals and ditches with chemical vapour deposition technique; Wherein should comprise with the high density plasma CVD method and form silica with the step that chemical vapour deposition technique is filled in those irrigation canals and ditches with this second dielectric material.
The method of aforesaid manufacturing microelectronic device, the wherein said tunnel dielectric characterization of wearing includes silica.
The method of aforesaid manufacturing microelectronic device, the step of wherein said formation mononitride layer comprises: the silicon nitride layer that forms a high silicon content.
The method of aforesaid manufacturing microelectronic device, the step of wherein said this nitride layer of etching comprises: form a non-conformal polymeric layer on this nitride layer, wherein this non-conformal polymeric layer is a self-aligned shade; Utilize plasma dry etch to cut to wear this nitride layer on the shallow trench isolation feature that is positioned at those depressions; And remove this non-conformal polymeric layer.
The method of aforesaid manufacturing microelectronic device, the wherein said step that partly removes the shallow trench isolation feature of those depressions comprises: impose on the shallow trench isolation feature that wet corrosion is engraved on those depressions by this nitride opening.
The object of the invention to solve the technical problems also realizes by the following technical solutions.A kind of method of making microelectronic device according to the present invention's proposition, it may further comprise the steps at least: a silicon substrate is provided, wherein this silicon substrate has the trench isolation feature of a depression that is arranged in a dielectric regime, and the position is adjacent to the silicon structure feature in the silicon structure district of this dielectric regime; Form one and wear the tunnel dielectric characterization within this silicon structure district on this silicon substrate; The silicon nitride layer that forms a high silicon content is on this silicon substrate; The silicon nitride layer of this high silicon content of etching is opened within this dielectric regime to form one; By this opening etching should depression trench isolation feature to form the gap between the trench isolation feature of the silicon nitride layer of this high silicon content and this depression; And form one first dielectric material, and on the sidewall of this silicon structure feature in the silicon nitride layer of this high silicon content.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The method of aforesaid manufacturing microelectronic device, the step of wherein said formation one first dielectric material comprises: use basic root oxidation process to form a thin silicon oxide layer; And form a high-temperature oxide layer on this thin silicon oxide layer.
The method of aforesaid manufacturing microelectronic device, the step that the tunnel dielectric characterization is worn in wherein said formation one comprises: form one silica layer on this silicon structure feature.
The object of the invention to solve the technical problems realizes in addition more by the following technical solutions.According to a kind of semiconductor device that the present invention proposes, it comprises at least: the shallow trench isolation feature of a depression, be formed on the semiconductor base material, and wherein the shallow trench isolation characterizing definition of this depression goes out a shallow-channel isolation region and semiconductor district; One wears tunnel oxide feature, is located within this semiconductor region on this semiconductor substrate; One silicon nitride layer is located on this semiconductor substrate, and wear on the shallow trench isolation feature of tunnel oxide feature and this depression at this position; And one silica layer, be positioned within this shallow-channel isolation region, and intert between the shallow trench isolation feature and this silicon nitride layer of this depression, wherein this silicon oxide layer isolates the sidewall of this silicon nitride layer from this semiconductor substrate.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid semiconductor device, wherein said silicon oxide layer are that a hole that defines between the shallow trench isolation feature of this silicon oxide layer and this depression is set.
Aforesaid semiconductor device, wherein said silicon nitride layer comprises the silicon nitride of the high silicon content with conductivity.
Aforesaid semiconductor device more comprises: a dielectric characterization, be located on this silicon nitride layer, and wherein this dielectric characterization comprises one of them of silica and aluminium oxide.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, major technique of the present invention thes contents are as follows:
For achieving the above object, the invention provides a kind of method of making microelectronic device, at least comprise: in semiconductor substrate, form the shallow trench isolation feature of a plurality of depressions, define by this semiconductor district in the shallow trench isolation feature of a plurality of depressions adjacent the two; In this semiconductor region, form and wear the tunnel dielectric characterization; Shallow trench isolation feature in depression forms nitride layer with wearing on the tunnel dielectric characterization; The nitride etching layer forms a plurality of nitride openings within the shallow trench isolation feature of depression; Partly remove the shallow trench isolation feature of depression by these a little nitride openings, and between the shallow trench isolation feature of nitride layer and depression, produce a plurality of gaps; And form first dielectric material, and sealing nitride opening on the surface of aforementioned nitride layer.
In addition, in order to achieve the above object, the present invention also provides a kind of method of making microelectronic device, at least comprise: the trench isolation feature with depression and the silicon substrate of silicon structure feature are provided, wherein Ao Xian trench isolation feature and silicon structure feature lay respectively in dielectric regime and the silicon structure district, and the silicon structure district is adjacent with the dielectric regime; Form in the silicon structure district on silicon substrate and wear the tunnel dielectric characterization; On silicon substrate, form the silicon nitride layer of high silicon content; The silicon nitride layer of etching high silicon content is used and form opening within the dielectric regime; By the etching notched trench isolation feature of aforementioned opening, use and between the trench isolation feature of the silicon nitride layer of high silicon content and depression, form a gap; And form on the sidewall of the silicon nitride layer of the first dielectric material high silicon content and silicon structure feature.
Moreover for achieving the above object, the present invention provides a kind of semiconductor device again, comprises at least: the shallow trench isolation feature of depression, wear tunnel oxide feature, silicon nitride layer and silicon oxide layer.Wherein Ao Xian shallow trench isolation feature is formed on the semiconductor substrate, and the shallow trench isolation characterizing definition of depression goes out shallow-channel isolation region and semiconductor region.Be provided in a side of in the semiconductor region on the semiconductor substrate and wear tunnel oxide feature.Silicon nitride layer is provided in a side of on the semiconductor substrate, and is positioned on the shallow trench isolation feature of wearing tunnel oxide feature and depression.Then be positioned at shallow-channel isolation region as for silicon oxide layer, and intert between the shallow trench isolation feature and silicon nitride layer of depression, silicon oxide layer isolates the sidewall of silicon nitride layer from semiconductor substrate.
By technique scheme, the present invention makes the method for microelectronic device and the semiconductor device of adopting said method has following advantage and beneficial effect at least: the present invention is in present non-planar NAND gate memory architecture, by reducing considering that electric charge is kept in the semiconductor device, can improve the performance of semiconductor device whole efficiency.
In sum, the invention relates to a kind of method of microelectronic device and semiconductor device of adopting said method made.The method that this makes microelectronic device comprises: shallow trench isolation (the Shallow Trench Isolation that forms depression; STI) feature is in semiconductor substrate, and the definition semiconductor region in the STI of a plurality of depressions feature adjacent the two; Formation is worn the tunnel dielectric characterization in semiconductor region; Form nitride layer in the STI feature of depression and wear on the tunnel dielectric characterization; The nitride etching layer is opened in the STI feature of depression to form nitride; By the nitride opening portion remove the STI feature of depression, and produce the gap between between the STI of nitride layer and depression feature; And form the surface of first dielectric material in nitride layer, seal the nitride opening.The present invention also provides a kind of semiconductor device of adopting said method.The present invention has obvious improvement technically, has tangible good effect, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 to Fig. 8 is the generalized section of each process stage of the preferred embodiment of semiconductor memory system of the present invention.
100: semiconductor memory system 110: silicon substrate
112: semiconductor ridge (semiconductor island) 114: isolation structure
116: wear tunnel oxide feature 118: nitride stores layer
119: non-conformal polymeric layer 120: opening
122: gap 124a: thin dielectric layer
124b: thin dielectric layer 124c: thin dielectric layer
126: dielectric layer 128: hole
130: polysilicon layer
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, the method of the manufacturing microelectronic device that foundation the present invention is proposed and its embodiment of semiconductor device, method, step, structure, feature and the effect thereof of adopting said method, describe in detail as after.
Relevant aforementioned and other technology contents, characteristics and effect of the present invention can clearly present in the detailed description of graphic preferred embodiment is consulted in following cooperation.For convenience of description, in following embodiment, components identical is represented with identical numbering.
Some embodiments of the present invention will be described in detail as follows.Yet except following description, the present invention can also be widely implements at other embodiment, and protection scope of the present invention is not subjected to the qualification of embodiment, and its protection range with claim is as the criterion.Moreover for clearer description being provided and being more readily understood the present invention, graphic interior each several part is not drawn according to its relative size, and some size is compared with other scale dependents and exaggerated; Incoherent detail section does not show fully yet, in the hope of graphic succinct.
In non-volatile memory device, the NAND gate memory cell has the various benefits that comprise the good and minification of efficient.At present, non-planar NAND gate memory architecture is the structure with a similar fin formula field-effect transistor (FinFET Transistors) in the use, and the shallow slot isolation structure with depression.Yet, directly contact as the silicon nitride layer of the NAND gate memory cell of electric charge acquisition (Charge Trap) with the oxide material of shallow trench isolation, and considering of keeping of increase electric charge.The invention provides a kind of non-planar memory cell and the manufacture method thereof relevant with the problems referred to above.
Fig. 1 to Fig. 8 is the generalized section of each process stage of the preferred embodiment of semiconductor memory system of the present invention.The integral body that non-flat semiconductor storage arrangement 100 and manufacture method thereof see also Fig. 1 to Fig. 8 is described below.
See also shown in Figure 1ly, the semiconductor memory system 100 of preferred embodiment of the present invention comprises silicon substrate 110.In other embodiments, silicon substrate 110 can selectivity or is comprised other semi-conducting materials as germanium (Germanium), GaAs (Gallium Arsenic) and diamond extraly.
See also shown in Figure 1ly equally, semiconductor memory system 100 also can comprise being arranged on and wear tunnel oxide (tunnel oxide) feature 116 on the semiconductor ridge 112.In order to have suitable tunneling effect (Tunneling Effect), wear the preset thickness that tunnel oxide feature 116 includes according to Design of device.In various embodiments, wearing tunnel oxide feature 116 is to utilize thermal oxidation (ThermalOxidation) or basic root oxidation (Radical Oxidation) processing procedure to make, therefore can self-aligned (Self-Aligned) semiconductor ridge.Wearing tunnel oxide feature 116 can utilize lithography method patterning silicon oxide layer to make optionally by the deposition one silica layer then.In other embodiments, for the integrality of optimization tunneling effect and device, wear tunnel oxide feature and include most layers.
See also shown in Figure 4ly, nitride etching stores layer 118 to form opening 120 within the zone of the isolation structure of depression, makes one to be independent of outside another with non-string.In one embodiment, the etch process that is applied in 118 etching of nitride storage layer further comprises the self-aligned etch process that Fig. 2 and Fig. 3 describe.See also shown in Figure 2ly, for etching of silicon nitride, non-conformal polymeric layer (Non-Conformal Polymer Layer) 119 is deposited on the semiconductor memory system 100 to form self-aligned shade (Mask).Then, see also shown in Figure 3ly, use the self-aligned shade, plasma dry etch (plasma dry etching) processing procedure is applied on the semiconductor memory system 100, store layers 118 with the nitride of etching between adjacent and non-string.In one embodiment, the silicon nitride etch processing procedure uses fluorine-containing plasma.Then, divest method (Dry Ashing) by dry type and/or wet-cleaned (Wet Cleaning) removes the self-aligned shade.See also shown in Figure 4ly, form nitride and store opening in the layer 118, with adjacent and non-string by isolating in another.Opening 120 optionally by using little shadow patterning process to form the photoresistance pattern, uses the photoresistance pattern to make as etching shade etches both silicon nitride layer then.
See also shown in Figure 5ly, an etch process (as wet etching) is applied on the semiconductor memory system 100, partly removes the feature of isolation structure 114 by opening 120, flatly forms gap 122 on 112 on semiconductor ridge.In one embodiment, use buffered hydrofluoric acid (BufferedHydrofluoric Acid; HF) isolation characteristic of etch silicon dioxide is to form gap 122.
See also shown in Figure 6ly, form a thin dielectric layer 124 stores layer 118 in nitride surface.More particularly, thin dielectric layer 124a is formed at the upper surface that nitride stores layer 118, and thin dielectric layer 124b is formed at the lower surface that nitride stores layer 118.In addition, thin dielectric layer 124c also is formed at the sidewall of the semiconductor ridge 112 in the gap.In one embodiment, thin dielectric layer 124 includes silica.In embodiment further, the thin dielectric layer of silica is to utilize basic root oxidation process that the nitride of a part is stored layer to be oxidized to silicon oxide layer and to form.
See also shown in Figure 7ly, dielectric layer 126 is to be formed at the surface that nitride stores layer 118.In one embodiment, dielectric layer 126 is to be formed on the thin dielectric layer 124, makes that opening 120 is sealed, and the generation level is between semiconductor ridge 112, and vertical hole (Voids) 128 between nitride storage layer 118 and isolation structure 114.In one embodiment, dielectric layer 126 is to be formed on each different parts of thin dielectric layer 124, comprises thin dielectric layer 124a upper part, thin dielectric layer 124b lower part, and the sidewall sections of thin dielectric layer 124c.Dielectric layer 126 is on the thin dielectric layer 124 that is formed at via opening 120 in opening and the hole.In addition, dielectric layer 126 is formed on the isolation structure 114 simultaneously.In one embodiment, dielectric layer 126 includes high-temperature oxide (HighTemperature Oxide; HTO).In embodiment further, silica is to utilize chemical vapor deposition process, for example low-pressure chemical vapor deposition (Low Pressure CVD; LPCVD) method cooperates temperature high deposition to form.In one embodiment, the temperature essence of chemical vapour deposition technique is higher than 750 ℃.For example, the temperature of chemical vapour deposition technique is that essence is between 750 ℃ and 1100 ℃.
In one embodiment, use basic root oxidation process on semiconductor memory system 100, nitride is stored layer 118 part convert silica to, with as except the dielectric layer 126 of high temperature oxide layer, oxide/nitride/oxide (Oxide-Nitride-Oxide; ONO) part of the upper oxide of structure.Utilize basic root oxidation process to cooperate adjusted processing parameter can make the upper oxide of oxide/nitride/oxide structure reach preset thickness.
See also shown in Figure 8ly, polysilicon layer 130 is to be deposited on the dielectric layer 126 of oxide skin(coating), and further patterning to form gate electrode.In one embodiment, gate electrode can utilize chemical vapour deposition technique to form, and imposes doping after deposition.The formation of gate electrode can comprise that other are as ion implantation that is used for polysilicon doping and/or the annealing process that is used for silicification (Silicidation).In chemical vapor deposition process, polysilicon layer optionally forms with (In-Situ) doping way of coming personally.In other embodiments, distance piece (Spacers) can be adjacent to be formed on by the polysilicon gate electrode.In the deposition process of distance piece, the hole of sealing can completely or partially be filled.
Other processing procedures can be used to form various device characteristics, and for example ion implantation manufacture process can be used to form source electrode and drain feature.In other embodiments, the silicification processing procedure is applied to have the metal silicide of the contact resistance of reduction with formation in source electrode and the drain feature.The silicification processing procedure can be applied in polysilicon gate electrode and the source/drain regions simultaneously.
Therefore, the invention provides a kind of integrated memory circuitry and manufacture method thereof.The storage arrangement that forms comprises the NAND gate memory cell with nitride preservative feature, and wherein the nitride preservative feature is fully packaged by the oxide of high-quality high-temperature oxide dielectric material and/or basic root oxidation process.Can reduce or eliminate by this and store the relevant electric charge of direct contact between the layer with trench isolation feature and nitride and keep and reliability issues.Other various variations in this spirit and scope are all consistent and fall into scope of the present invention with the present invention.For example, use this method to form NAND gate memory cell with low spill and leakage problem.This method also can be used in other application with similar kenel and spill and leakage problem.The present invention can be used to form silicon/oxide/nitride/oxide/silicon (Silicon-Oxide-Nitride-Oxide-Silicon; SONOS) NAND gate memory cell.In other embodiments, the method similarly can be used to form silicon-oxide-nitride silicon-alundum (Al-tantalum nitride (Si-Oxide-SiN-Al
2O
3-TaN; TANOS) NAND gate memory cell.For example, be formed at the upper oxide layer that nitride stores on the layer and comprise alundum (Al, it is one to have the dielectric material of high-dielectric coefficient.In other embodiments, gate electrode comprises the metal or metal alloy that has the high workload function and/or have lower electrons tunnel effect in word line is erased process (tantalum nitride for example; TaN).Gate electrode can be additionally or is optionally comprised other suitable electric conducting materials as tungsten and tungsten nitride.
In another embodiment, silicon substrate 110 can comprise composite semiconductor material, for example carborundum, GaAs, indium arsenide and indium phosphide.Silicon substrate 110 can comprise the alloy semiconductor material, for example SiGe, silicon germanium carbide (Silicon Germanium Carbide), gallium arsenide phosphide (Gallium ArsenicPhosphide) and gallium indium phosphorus compound (Gallium Indium Phosphide).Silicon substrate 110 also can comprise the semi-conducting material that is positioned on the insulation system, for example silicon-on-insulator (Silicon-On-Insulator; SOI) base material.In another embodiment, silicon substrate 110 comprises the structure of comprehensive silicon structure or MULTILAYER COMPOSITE semi-conducting material.Semiconductor device more can comprise other functional devices and/or pseudo-characteristic (Dummy Features).For example, semiconductor device comprises the transistor of metal oxide semiconductcor field effect transistor (MOSFET) or other patterns, as fin formula field-effect transistor (FinFET), and Laterally Diffused Metal Oxide Semiconductor (Lateral Diffused MOS; LDMOS), vertical proliferation metal-oxide semiconductor (MOS) (Vertical Diffused MOS; And/or stress metal oxide semiconductor (Strained MOS) structure VDMOS).In another embodiment, can be in base material dry ecthing one irrigation canals and ditches, establish aforesaid irrigation canals and ditches with the thermal oxide lining, then with as the aforesaid irrigation canals and ditches of the filling insulating material of silica, silicon nitride or silicon oxynitride, with the formation shallow slot isolation structure.The irrigation canals and ditches of filling can have sandwich construction, for example high density plasma CVD (High Density Plasma CVD; HDPCVD) silica and undoped silicon glass (Undoped Silica Glass; USG).
Semiconductor device of the present invention comprises that more configuration and combination form the various conductive features of integrated circuit.In one embodiment, semiconductor device comprises as the contact hole of vertical connection and interlayer hole, and as the metal wire of horizontal wiring, integral body is called the multiple layer inner connection line.In one embodiment, the multiple layer inner connection line can comprise the combination of the aluminium, aluminium/silicon/copper alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide or the previous materials that are used in 0.18mm or larger sized technology node.The aluminium intraconnections can utilize the combination of sputter (Sputtering) method, chemical vapour deposition technique or aforementioned techniques to deposit.Other are made processing procedure (comprising little shadow and etching) and can be used to patterning conductive material to be communicated with (call wire) as vertical (interlayer hole and contact hole) and level.Also have other manufacturing processing procedures to can be used to form metal silicide as thermal annealing.In other embodiments, can use copper multiple layer inner connection line, wherein copper multiple layer inner connection line comprises the combination of copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide or the previous materials of the technology node that is used in 0.18mm or smaller szie.Copper multiple layer inner connection line can use existing known dual damascene (Dual Damascene) processing procedure to form.
Therefore, the invention provides a kind of method of making microelectronic device.The method comprises: form irrigation canals and ditches and semiconductor ridge on semiconductor substrate, wherein each irrigation canals and ditches is to intert between two semiconductor ridges; Fill irrigation canals and ditches with first dielectric material and form the isolation characteristic of depression in irrigation canals and ditches; Use second dielectric material to form and wear tunnel dielectric characterization (Tunnel Dielectric Features) on the semiconductor ridge; Form nitride layer in the isolation characteristic of depression with wear on the tunnel dielectric characterization; The nitride etching layer forms the mononitride opening, to expose the isolation characteristic of corresponding depression in the irrigation canals and ditches on each irrigation canals and ditches; By the nitride opening portion remove the isolation characteristic of depression, under irrigation canals and ditches and nitride layer, produce the gap; And form the 3rd dielectric material in the surface of nitride layer and the sidewall of semiconductor ridge, sealing nitride opening.
In one embodiment of this invention, the method more comprises: behind the isolation characteristic that partly removes depression, form the 3rd dielectric material before, form thin dielectric layer in the surface of nitride layer and the sidewall of semiconductor ridge.The formation of thin dielectric layer can comprise uses basic root oxidation process to form thin silicon oxide layer.In other embodiments, the step with first dielectric material filling irrigation canals and ditches comprises the use chemical vapour deposition technique.The step of filling irrigation canals and ditches with first dielectric material can comprise utilizes the high density plasma CVD method to form silica.Second dielectric material can comprise silica.The formation of nitride layer can comprise the silicon nitride layer that forms high silicon content.The etching of nitride layer can comprise uses the self-aligned etch process.In one embodiment, the self-aligned etch process comprises: form non-conformable polymer material layer (Non-Conformal Polymeric Material Layer) as the self-aligned shade on nitride layer; In irrigation canals and ditches, utilize plasma dry etch to cut and wear nitride layer; And remove non-conformable polymer material layer.Partly remove and to comprise in the step of isolation characteristic of depression by the nitride opening and imposing on the isolation characteristic that wet corrosion is engraved on depression.Form in the step of the 3rd dielectric material and can comprise the formation high-temperature oxide.
The present invention also provides a kind of other embodiment that make the microelectronic device method.The method comprises: the silicon nitride layer that forms high silicon content is on the semiconductor substrate with silicon structure and dielectric regime, and wherein each silicon structure is to intert between adjacent dielectric regime, and the dielectric regime includes first dielectric material; The silicon nitride layer of etching high silicon content is opened within the dielectric regime with the silicon nitride layer that forms high silicon content; By first dielectric material in the opening etching dielectric regime, to form the gap between the silicon structure; And form second dielectric material on the sidewall of the silicon nitride layer of high silicon content and silicon structure.
In an embodiment of said method, the step that forms second dielectric material comprises uses basic root oxidation process to form thin silicon oxide layer; And form high-temperature oxide on thin silicon oxide layer.In other embodiments, the method more comprises: before the silicon nitride layer that forms high silicon content, form and wear the tunnel dielectric characterization on silicon structure.
The present invention also provides a kind of semiconductor device.This semiconductor device comprises: be formed at most characteristic of semiconductor on the base material; Be formed at most isolation characteristics on the base material, wherein each characteristic of semiconductor is to intert between adjacent two isolation characteristics, and most isolation characteristics are that top surface by characteristic of semiconductor is to lower recess; Silicon nitride layer is located on characteristic of semiconductor and the isolation characteristic; And silicon oxide layer, interting between silicon nitride layer and isolation characteristic, silicon oxide layer is to be used for isolating from silicon nitride layer adjacent characteristic of semiconductor.
In the various embodiment of semiconductor device of the present invention, silicon oxide layer can comprise the high-temperature oxide layer.Silicon oxide layer can comprise that the more basic root oxidation process of use is formed at the thin silicon oxide layer between high-temperature oxide layer and the silicon nitride layer.Silicon oxide layer can be provided with the hole that is used for defining between a silicon oxide layer and an isolation characteristic.Silicon nitride layer can comprise the silicon nitride of the high silicon content with conductivity.Semiconductor device more can comprise the dielectric characterization that is located on the silicon nitride layer, wherein dielectric characterization comprise silica and aluminium oxide one of them.Semiconductor device more can comprise the gate electrode that is located on the dielectric characterization, wherein gate electrode comprise doped polycrystalline silicon (Doped Poly-Silicon), titanium nitride, tungsten and tungsten nitride one of them.In other embodiments, semiconductor device comprises finfet-like effect transistor memory cell.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be not break away from the technical solution of the present invention content, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (15)
1, a kind of method of making microelectronic device is characterized in that it may further comprise the steps at least:
The shallow trench isolation features that form most depressions in the semiconductor base material, and definition semiconductor district in the shallow trench isolation feature of those depressions adjacent the two;
Form one and wear the tunnel dielectric characterization within this semiconductor region;
Forming the mononitride layer wears on the tunnel dielectric characterization in the shallow trench isolation feature of those depressions and this;
This nitride layer of etching is opened in the shallow trench isolation feature of those depressions to form most nitride;
Partly remove the shallow trench isolation feature of those depressions by those nitride openings, and produce most gaps between between the shallow trench isolation feature of this nitride layer and those depressions; And
Form most the surfaces of one first dielectric material, and seal those nitride openings in this nitride layer.
2, the method for manufacturing microelectronic device according to claim 1 is characterized in that comprising more at least: after this partly removes the step of shallow trench isolation feature of those depressions; And before this forms the step of this first dielectric material, form a thin dielectric layer in those surfaces of this nitride layer and most sidewalls of this semiconductor substrate.
3, the method for manufacturing microelectronic device according to claim 2 is characterized in that the step of wherein said formation one thin dielectric layer comprises: use basic root oxidation process to form a thin silicon oxide layer.
4, the method for manufacturing microelectronic device according to claim 1 is characterized in that the wherein said step that forms the shallow trench isolation feature of most depressions comprises:
Form most irrigation canals and ditches in this semiconductor substrate; And
With chemical vapour deposition technique one second dielectric material is filled in those irrigation canals and ditches;
Wherein should comprise with the high density plasma CVD method and form silica with the step that chemical vapour deposition technique is filled in those irrigation canals and ditches with this second dielectric material.
5, the method for manufacturing microelectronic device according to claim 1 is characterized in that the wherein said tunnel dielectric characterization of wearing includes silica.
6, the method for manufacturing microelectronic device according to claim 1 is characterized in that the step of wherein said formation mononitride layer comprises: the silicon nitride layer that forms a high silicon content.
7, the method for manufacturing microelectronic device according to claim 1 is characterized in that the step of wherein said this nitride layer of etching comprises:
Form a non-conformal polymeric layer on this nitride layer, wherein this non-conformal polymeric layer is a self-aligned shade;
Utilize plasma dry etch to cut to wear this nitride layer on the shallow trench isolation feature that is positioned at those depressions; And
Remove this non-conformal polymeric layer.
8, the method for manufacturing microelectronic device according to claim 1 is characterized in that the wherein said step that partly removes the shallow trench isolation feature of those depressions comprises: impose on the shallow trench isolation feature that wet corrosion is engraved on those depressions by this nitride opening.
9, a kind of method of making microelectronic device is characterized in that it may further comprise the steps at least:
One silicon substrate is provided, and wherein this silicon substrate has the trench isolation feature of a depression that is arranged in a dielectric regime, and the position is adjacent to the silicon structure feature in the silicon structure district of this dielectric regime;
Form one and wear the tunnel dielectric characterization within this silicon structure district on this silicon substrate;
The silicon nitride layer that forms a high silicon content is on this silicon substrate;
The silicon nitride layer of this high silicon content of etching is opened within this dielectric regime to form one;
By this opening etching should depression trench isolation feature to form the gap between the trench isolation feature of the silicon nitride layer of this high silicon content and this depression; And
Form one first dielectric material in the silicon nitride layer of this high silicon content, and on the sidewall of this silicon structure feature.
10, the method for manufacturing microelectronic device according to claim 9 is characterized in that the step of wherein said formation one first dielectric material comprises:
Use basic root oxidation process to form a thin silicon oxide layer; And
Form a high-temperature oxide layer on this thin silicon oxide layer.
11, the method for manufacturing microelectronic device according to claim 9 is characterized in that the step that the tunnel dielectric characterization is worn in wherein said formation one comprises: form one silica layer on this silicon structure feature.
12, a kind of semiconductor device is characterized in that it comprises at least:
The shallow trench isolation feature of one depression is formed on the semiconductor base material, and wherein the shallow trench isolation characterizing definition of this depression goes out a shallow-channel isolation region and semiconductor district;
One wears tunnel oxide feature, is located within this semiconductor region on this semiconductor substrate;
One silicon nitride layer is located on this semiconductor substrate, and wear on the shallow trench isolation feature of tunnel oxide feature and this depression at this position; And
One silica layer is positioned within this shallow-channel isolation region, and interts between the shallow trench isolation feature and this silicon nitride layer of this depression, and wherein this silicon oxide layer isolates the sidewall of this silicon nitride layer from this semiconductor substrate.
13, semiconductor device according to claim 12 is characterized in that wherein said silicon oxide layer is that a hole that defines between the shallow trench isolation feature of this silicon oxide layer and this depression is set.
14, semiconductor device according to claim 12 is characterized in that wherein said silicon nitride layer comprises the silicon nitride of the high silicon content with conductivity.
15, semiconductor device according to claim 12 is characterized in that more comprising: a dielectric characterization, be located on this silicon nitride layer, and wherein this dielectric characterization comprises one of them of silica and aluminium oxide.
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| US12/172,687 US7910453B2 (en) | 2008-07-14 | 2008-07-14 | Storage nitride encapsulation for non-planar sonos NAND flash charge retention |
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| CN105990324A (en) * | 2015-02-15 | 2016-10-05 | 华邦电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN106252351A (en) * | 2015-06-08 | 2016-12-21 | 三星电子株式会社 | Semiconductor device |
| US10505010B2 (en) | 2015-06-08 | 2019-12-10 | Samsung Electronics Co., Ltd. | Semiconductor device blocking leakage current and method of forming the same |
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| US7910453B2 (en) | 2011-03-22 |
| TW201003854A (en) | 2010-01-16 |
| US20100006974A1 (en) | 2010-01-14 |
| TWI377650B (en) | 2012-11-21 |
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