CN101626361B - Demodulator and demodulating method for high-speed data packet access system - Google Patents

Abstract

The invention discloses a demodulating method for a high-speed data packet access system, which is suitable for demodulating a signal modulated by a 16QAM mode and includes: confirming soft bit according to the received signal, wherein b3 is equal to I, b2 is equal to Q, b1 is the difference of 2a minus absolute value of I, b0 is the difference of 2a minus the absolute value of Q; I and Q are respectively the same-phase signal and the quadrature-phase signal of the high-speed physical downlink shared channel, which are transformed from the received signal, 2a is a judging line as the below formula, wherein P is the multi-code channel number, and N is the averaging symbolic number. The symbol of a high speed downlink shared channel (HS-DSCH) is directly used in the technical scheme of the invention to estimate the amplitude, thus the demodulation performance can be improved. The prioritization scheme further provides an easy and accurate judging line acquirement method for the 16QAM demodulation without estimating two channels nor filtering, thereby facilitates to the hardware implementation.

Description

Demodulation method in the high-speed data packet access system and demodulator

Technical field

The present invention relates to the communications field, be specifically related to demodulation method and demodulator in a kind of HSDPA (high-speed data packets access) system.

Background technology

In the HSDPA system,, adopted Adaptive Modulation and coding (AMC) technology for the throughput and the availability of frequency spectrum that improves the sub-district.This technology makes base station node-B to adjust modulation system and code efficiency in time according to the current wireless channel conditions of user equipment (UE) feedback, thereby the message transmission rate of making and channel conditions are complementary.Two kinds of modulation system: QPSK (QPSK) and 16QAM (quadrature amplitude modulation) are arranged in the HSDPA of current version.

The planisphere of 16QAM modulation is as shown in Figure 1.

Can find out that by Fig. 1 16QAM modulation is a kind of amplitude quadrature amplitude modulation that combines with phase place, thus if the signal that correct demodulation 16QAM mode is modulated, not only want correct compensation to go out the phase place of signal, also will the correct amplitude that estimates signal.

Based on the phase place that channel estimating and the channel compensation of CPICH Common Pilot Channel CPICH can draw current demand signal, estimate the amplitude reference is provided also can for the HS-DSCH (high-speed data shared channel) in HSDPA based on the power of CPICH equally.Generally speaking, the 16QAM demodulation all is based on the phase place of CPICH and symbol that power magnitude is adjudicated data, adopts soft-decision usually, and what promptly provide is the confidence level of the multi bit quantization of data symbol.

In addition, from figure, also can find out, adopt the 16QAM modulation, each that is mapped to the 16QAM modulation symbol is than peculiar different confidence level, and preceding two bits have higher confidence level than latter two bit.General patent all lays particular emphasis on the confidence level of improving latter two bit, to improve whole decoding performance, still also the estimation of amplitude judgement line is not provided the method for improvement.

In HSDPA, the power bias of CPICH and HS-DSCH is seen formula (1).

P _HS-PDSCH＝P _CPICH+ψ+δ(1)

Wherein ψ is the measurement power excursion of RRC (Radio Resource control) signaling configuration, and δ is tabled look-up according to the capability class of UE by UE and obtains, and this form is exactly CQI (channel quality indication) mapping table, sees table one.

Table one, CQI mapping table (the UE capability class is 1 to 6)

Because the CQI reflection is the signal to noise ratio of HS-DSCH,, see formula (2) so, can draw method based on CPICH signal-to-noise ratio (snr) estimation CQI according to formula (1).

CQI＝(E _c/N _o) _CPICH*ψ*δ+16 (2)

[0014]Can find out that by formula (1) power bias of HS-DSCH and CPICH changes with CQI, and the CQI variation is very frequent.In addition; Carry out the signal to noise ratio that CQI estimates also to be based on CPICH by formula (2); Be that the δ value is based on the CPICH signal to noise ratio and draws, use formula (1) to carry out to cause the multistage amplification of evaluated error like this, thereby reduced demodulation performance based on the amplitude Estimation of CPICH power.

Summary of the invention

The technical problem that the present invention will solve provides demodulation method and the demodulator in a kind of high-speed data packet access system, and the signal to adopting the 16QAM mode to modulate can improve demodulation performance.

In order to address the above problem, the invention provides the demodulation method in a kind of high-speed data packet access system, be applicable to the signal that demodulation 16QAM mode is modulated, comprising:

Signal according to receiving is confirmed soft bit: b3 equals I, and b2 equals Q, b1 be 2a deduct I thoroughly deserve poor; B0 be 2a deduct Q thoroughly deserve poor;

I, Q are respectively and receive in-phase signal and the quadrature-phase that signal transforms the High-Speed Physical Downlink Shared Channel that obtains, and 2a is the judgement line:

$2a=\frac{2}{\sqrt{10}}\sqrt{\frac{1}{P\×N}\stackrel{P}{\mathrm{\Σ}}\stackrel{N}{\mathrm{\Σ}}(I^2+Q^2)}$

Wherein, P is the multiple code channel number; N is used for average symbolic number.

Further, described demodulation method also comprises:

Make the power estimated value and be x: $x=\stackrel{P}{\mathrm{\Σ}}\stackrel{N}{\mathrm{\Σ}}(I^2+Q^2)$

Then $2a=\sqrt{\frac{2x}{5\×P\×N}};$

The method that adopts piecewise linear approximation is approximately the plurality of sections straight line with the relation curve of this 2a and x, and the value of x obtains the slope A and the side-play amount B of each section straight line at different straight lines corresponding to different sections when interval, then 2a equal A multiply by x product and B's and.

Further, described demodulation method also comprises:

Preserve with different P, N, x location between corresponding A and B, when calculating 2a, find corresponding A and B between according to P, N and x location, obtain 2a according to x.

Further, described demodulation method also comprises:

Confirm the estimation interval of 2a according to channel condition, confirm to be used for average symbol quantity N according to the estimation interval of 2a.

Further, confirming to be used for average symbol quantity N according to the estimation interval of 2a is meant:

When a time slot was estimated X 2a value, N equaled the total number of symbol in this time slot divided by X;

When a time slot was estimated a 2a value, N equaled a total number of the symbol in the time slot;

When a plurality of time slots were estimated a 2a value, N equaled the total number of symbol in a plurality of time slots.

The present invention also provides the demodulator in a kind of high-speed data packet access system, comprising:

Memory module is used to preserve by receiving the I that signal transforms the High-Speed Physical Downlink Shared Channel that obtains, Q symbol data;

Judgement line computation module is used for according to I, Q symbol data, and multiple code channel is counted P, is used for the value that average symbolic number N calculates judgement line 2a:

$2a=\frac{2}{\sqrt{10}}\sqrt{\frac{1}{P\×N}\stackrel{P}{\mathrm{\Σ}}\stackrel{N}{\mathrm{\Σ}}(I^2+Q^2)}$

Soft bit calculation module, the value of the I that is used for preserving according to memory, Q symbol data and judgement line 2a generates soft bit: b3 equals I, and b2 equals Q, b1 be 2a deduct I thoroughly deserve poor; B0 be 2a deduct Q thoroughly deserve poor.

Further, judgement line computation module comprises:

The unit that square adds up is used for I, the Q symbol data preserved according to memory module, and multiple code channel count P, be used for that average symbolic number N obtains the power estimated value with x be:

$x=\stackrel{P}{\mathrm{\Σ}}\stackrel{N}{\mathrm{\Σ}}(I^2+Q^2)$

Judgement line computation unit, be used for calculating judgement line: 2a and be product that A multiply by x with B's and; Wherein, A and B are respectively: the relation curve of 2a and x adopts the slope and the side-play amount of the approximate straight line that forms of piecewise linear approximation method.

Further, judgement line computation module also comprises:

Memory cell, be used to preserve with different P, N, x location between corresponding A and B;

Said judgement line computation unit calculates the judgement line and is meant: judgement line computation unit is counted P according to x, multiple code channel and is used for average symbolic number N and finds corresponding A and B in memory cell, calculates the judgement line then.

Further, described demodulator also comprises:

The estimation interval adjusting module is used for confirming according to channel condition the estimation interval of 2a, confirms to be used for average symbol quantity N according to the estimation interval of 2a.

Further, the estimation interval adjusting module is confirmed to be used for average symbol quantity N according to the estimation interval of 2a and is meant:

When a time slot was estimated X 2a value, N equaled the total number of symbol in this time slot divided by X;

When a time slot was estimated a 2a value, N equaled a total number of the symbol in the time slot;

When a plurality of time slots were estimated a 2a value, the symbol that N equals in a plurality of time slots was total

Technical scheme of the present invention directly uses the symbol of HS-DSCH channel to carry out amplitude Estimation, can improve demodulation performance; Its prioritization scheme is further adjudicated the line preparation method for the 16QAM demodulation provides simply accurately, need not to estimate two kinds of channels, also without filtering, therefore is easier to hardware and realizes.

Description of drawings

Fig. 1 is the 16QAM modulation constellation;

Fig. 2 is the sketch map of a kind of 2a valuation scope among the present invention;

Fig. 3 is the practical implementation block diagram of the demodulator in the high-speed data packet access system of the present invention.

Embodiment

To combine accompanying drawing and embodiment that technical scheme of the present invention is explained in more detail below.

The invention provides the demodulation method in a kind of high-speed data packet access system, be applicable to the signal that demodulation 16QAM mode is modulated, comprising:

Signal according to receiving confirms that soft bit is following:

b3＝re(r)＝I

b2＝im(r)＝Q

b1＝2a-|re(r)|＝2a-|I|(3)

b0＝2a-|im(r)|＝2a-|Q|

Wherein r is the symbol that receives data, and 2a is the value of judgement line, and I, Q are respectively and receive in-phase signal and the quadrature-phase that signal transforms the HS-PDSCH (High-Speed Physical Downlink Shared Channel) that obtains, and be as shown in Figure 1.

After soft bit generates, send to the HS-DSCH channel decoder and be for further processing.

Wherein, 2a directly estimates 2a based on the symbol behind the HS-DSCH channel compensation by following method, is easier to hardware like this and realizes; In the method below, P is the multiple code channel number; N is used for average symbolic number, decides based on the real system situation.

The average power of elder generation's estimated signal is calculated 2a again:

$2a=2\sqrt{\frac{\mathrm{Power}\_\mathrm{est}}{10}}---\left(4\right)$

Wherein Power_est is the average power of signal, $\mathrm{Power}\_\mathrm{Est}=\frac{1}{P\×N}\stackrel{P}{\mathrm{\Σ}}\stackrel{N}{\mathrm{\Σ}}(I^2+Q^2);$

Can derive:

$2a=\frac{2}{\sqrt{10}}\sqrt{\frac{1}{P\×N}\stackrel{P}{\mathrm{\Σ}}\stackrel{N}{\mathrm{\Σ}}(I^2+Q^2)}---\left(5\right)$

If each power estimated value and do $x=\stackrel{P}{\mathrm{\Σ}}\stackrel{N}{\mathrm{\Σ}}(I^2+Q^2)---\left(6\right)$

Then (5) formula can be write as

$2a=\sqrt{\frac{2}{5\×P\×N}x}=f\left(x\right)\≈\mathrm{Ax}+B---\left(7\right)$

That is to say that 2a changes with x, form a relation curve, adopting the method for piecewise linear approximation is the plurality of sections straight line with this curve approximation, and the value of x is at different straight lines corresponding to different sections when interval; Can obtain the slope A and the side-play amount B of each section straight line, thereby can be beneficial to hardware and realize according to the value of x approximate calculation 2a.(7) in the formula; A and B are the known constant that decides by between P, N and x location; To be kept in the memory (MEMORY) with corresponding A and B between different P, N, x location; When calculating 2a, can find corresponding A and B between according to P, N, x location, thereby obtain 2a according to x, simple and easy quick.The relation curve of not getting rid of 2a and x in the practical application is approximately straight line, and A, the B of this moment all only have a kind of value, can not consider the interval of x.

Wherein, when obtaining 2a, can change the estimation interval of 2a, thereby adjustment is used for average symbol quantity N according to channel condition; Find out optimum estimation,, reduce the value of N such as when channel variation is very fast; Go out 2a with Fast estimation, and when channel does not change basically, then can increase the value of N; Can one estimate a plurality of values (suppose that a time slot estimates X value, then N equals the total number of symbol in this time slot divided by X, gets the situation of aliquot usually) in the time slot, as shown in Figure 2; Also can estimate a value (this moment, N equaled the total number of symbol in this time slot) by a time slot, or a plurality of time slot is estimated a value (this moment, N equaled the total number of symbol in a plurality of time slots).Generally speaking, can be defaulted as a time slot and estimate that once performance is also good.

The method of the invention is not limited to hardware or software is realized.

The present invention also provides the demodulator in a kind of high-speed data packet access system, is applicable to the signal that demodulation 16QAM mode is modulated, and is as shown in Figure 3, comprising:

Memory module is used to preserve by receiving the I that signal transforms the HS-PDSCH (High-Speed Physical Downlink Shared Channel) that obtains, Q symbol data; The receiver here is generally Rake receiver or senior receiver (like Equalizer); Can set up corresponding working area for each channel, preserve reception is converted in this channel I, Q symbol data;

Judgement line computation module, be used for I, the Q symbol data preserved according to memory module, and multiple code channel is counted P, is used for the value that average symbolic number N calculates judgement line 2a:

$2a=\frac{2}{\sqrt{10}}\sqrt{\frac{1}{P\×N}\stackrel{P}{\mathrm{\Σ}}\stackrel{N}{\mathrm{\Σ}}(I^2+Q^2)}$

Soft bit calculation module, the value of the I that is used for preserving according to memory, Q symbol data and judgement line 2a generates soft bit b0, b1, b2 and b3:

b3＝re(r)＝I

b2＝im(r)＝Q

b1＝2a-|re(r)|＝2a-|I|

b0＝2a-|im(r)|＝2a-|Q|

Wherein, Demodulator can also comprise the estimation interval adjusting module; Be used for estimation interval, thereby adjustment is used for average symbol quantity N, can one estimates that a plurality of values (suppose that a time slot estimates X value in the time slot according to the variation of channel condition change 2a; Then N equals the total number of symbol in this time slot divided by X; Usually get the situation of aliquot), also can estimate a value (this moment, N equaled the total number of symbol in this time slot) by a time slot, or a plurality of time slot is estimated a value (this moment, N equaled the total number of symbol in a plurality of time slots).Generally speaking, can give tacit consent to N and equal the total number of symbol in this time slot.

Wherein, judgement line computation module can specifically comprise:

Memory cell, be used to preserve with different P, N, x location between corresponding A and B; Wherein A and B are respectively: the relation curve of 2a and x adopts the slope and the side-play amount of the approximate straight line that forms of piecewise linear approximation method.During practical application, this memory cell physically can be integrated in other module of demodulator.

The unit that square adds up is used for I, the Q symbol data preserved according to memory module, and multiple code channel count P, be used for that average symbolic number N obtains the power estimated value with x be:

$x=\stackrel{P}{\mathrm{\Σ}}\stackrel{N}{\mathrm{\Σ}}(I^2+Q^2)$

Judgement line computation unit is used for counting P and being used for average symbolic number N according to x, multiple code channel finding corresponding A and B in memory cell, calculates the value of judgement line 2a then:

$2a=\sqrt{\frac{2}{5\×P\×N}x}=f\left(x\right)\≈\mathrm{Ax}+B$

Further explain with an application example of the present invention below.

Should comprise with example:

At first Rake receiver or senior receiver end are seen the symbol data behind the channel compensation off, and this symbol data is for changing into the I of HS-PDSCH (High-Speed Physical Downlink Shared Channel), the Q symbol data, and deposit memory in.

As shown in Figure 2, soft bit demodulation circuit reads I earlier, the Q symbol, and to I, the Q symbol is asked respectively square and is added up, and asks 2a with piecewise linear approximatioss again.The number of times that adds up is to measure N by physical channel number P and estimated data to decide.After 2a calculated, soft bit generative circuit read I once more, the Q symbol, and calculate soft bit b3, b2, b1, b0 according to formula (3).

To calculate that soft bit b3, b2, b1, b0 deliver the HS-DSCH decoding and Turbo decoding is for further processing.

Certainly; The present invention also can have other various embodiments; Under the situation that does not deviate from spirit of the present invention and essence thereof; Those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of claim of the present invention.

Claims (10)

1. the demodulation method in the high-speed data packet access system is applicable to the signal that demodulation 16QAM mode is modulated, and comprising:

Signal according to receiving is confirmed soft bit: b3 equals I, promptly equals to receive the real part of data symbol, and b2 equals Q, promptly equals to receive the imaginary part of data symbol, b1 be 2a deduct b3 thoroughly deserve poor; B0 be 2a deduct b2 thoroughly deserve poor;

I, Q are respectively and receive in-phase signal and the quadrature-phase that signal transforms the High-Speed Physical Downlink Shared Channel that obtains, and 2a is the judgement line:

$2a=\frac{2}{\sqrt{10}}\sqrt{\frac{1}{P\×N}\stackrel{P}{\mathrm{\Σ}}\stackrel{N}{\mathrm{\Σ}}(I^2+Q^2)}$

Wherein, P is the multiple code channel number; N is used for average symbolic number.

2. demodulation method as claimed in claim 1 is characterized in that, also comprises:

Make the power estimated value and be x: $x=\stackrel{P}{\mathrm{\Σ}}\stackrel{N}{\mathrm{\Σ}}(I^2+Q^2)$

Then $2a=\sqrt{\frac{2x}{5\×P\×N}};$

The method that adopts piecewise linear approximation is approximately the plurality of sections straight line with the relation curve of this 2a and x, and the value of x obtains the slope A and the side-play amount B of each section straight line at different straight lines corresponding to different sections when interval, then 2a equal A multiply by x product and B's and.

3. demodulation method as claimed in claim 2 is characterized in that, also comprises:

Preserve with different P, N, x location between corresponding A and B, when calculating 2a, find corresponding A and B between according to P, N and x location, obtain 2a according to x.

4. like each described demodulation method in the claim 1 to 3, it is characterized in that, also comprise:

Confirm the estimation interval of 2a according to channel condition, confirm to be used for average symbol quantity N according to the estimation interval of 2a.

5. demodulation method as claimed in claim 4 is characterized in that, confirms to be used for average symbol quantity N according to the estimation interval of 2a and is meant:

When time slot was estimated X 2a value, N equaled the total number of symbol in this time slot divided by X;

When a time slot was estimated a 2a value, N equaled a total number of the symbol in the time slot;

When a plurality of time slots were estimated a 2a value, N equaled the total number of symbol in a plurality of time slots.

6. the demodulator in the high-speed data packet access system is characterized in that, comprising:

Memory module is used to preserve by receiving the I that signal transforms the High-Speed Physical Downlink Shared Channel that obtains, Q symbol data;

Judgement line computation module is used for according to I, Q symbol data, and multiple code channel is counted P, is used for the value that average symbolic number N calculates judgement line 2a:

$2a=\frac{2}{\sqrt{10}}\sqrt{\frac{1}{P\×N}\stackrel{P}{\mathrm{\Σ}}\stackrel{N}{\mathrm{\Σ}}(I^2+Q^2)}$

Soft bit calculation module; The value of the I that is used for preserving according to memory, Q symbol data and judgement line 2a generates soft bit: b3 equals I, promptly equals to receive the real part of data symbol, and b2 equals Q; Promptly equal to receive the imaginary part of data symbol, b1 be 2a deduct b3 thoroughly deserve poor; B0 be 2a deduct b2 thoroughly deserve poor.

7. demodulator as claimed in claim 6 is characterized in that, judgement line computation module comprises:

The unit that square adds up is used for I, the Q symbol data preserved according to memory module, and multiple code channel count P, be used for that average symbolic number N obtains the power estimated value with x be:

$x=\stackrel{P}{\mathrm{\Σ}}\stackrel{N}{\mathrm{\Σ}}(I^2+Q^2)$

Judgement line computation unit, be used for calculating judgement line: 2a and be product that A multiply by x with B's and; Wherein, A and B are respectively: the relation curve of 2a and x adopts the slope and the side-play amount of the approximate straight line that forms of piecewise linear approximation method.

8. demodulator as claimed in claim 7 is characterized in that, judgement line computation module also comprises:

Memory cell, be used to preserve with different P, N, x location between corresponding A and B;

Said judgement line computation unit calculates the judgement line and is meant: judgement line computation unit is counted P according to x, multiple code channel and is used for average symbolic number N and finds corresponding A and B in memory cell, calculates the judgement line then.

9. like each described demodulator in the claim 6 to 8, it is characterized in that, also comprise:

The estimation interval adjusting module is used for confirming according to channel condition the estimation interval of 2a, confirms to be used for average symbol quantity N according to the estimation interval of 2a.

10. demodulator as claimed in claim 9 is characterized in that, the estimation interval adjusting module is confirmed to be used for average symbol quantity N according to the estimation interval of 2a and is meant:

When time slot was estimated X 2a value, N equaled the total number of symbol in this time slot divided by X;

When a time slot was estimated a 2a value, N equaled a total number of the symbol in the time slot;

When a plurality of time slots were estimated a 2a value, N equaled the total number of symbol in a plurality of time slots.

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