CN101625521A - Optical proximity correction method - Google Patents
Optical proximity correction method Download PDFInfo
- Publication number
- CN101625521A CN101625521A CN200810040372A CN200810040372A CN101625521A CN 101625521 A CN101625521 A CN 101625521A CN 200810040372 A CN200810040372 A CN 200810040372A CN 200810040372 A CN200810040372 A CN 200810040372A CN 101625521 A CN101625521 A CN 101625521A
- Authority
- CN
- China
- Prior art keywords
- edge placement
- placement error
- electronic circuit
- process window
- correction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The invention relates to an optical proximity correction method, which considers edge placement errors and process window related parameters such as the light intensity slope while correcting a circuit diagram, performs directed corrections by selecting a sub circuit diagram correcting step which is sensitive to the edge placement errors, and performing process window related parameter directed corrections on another sub circuit diagram. The optical proximity correction method has obvious benefit for a process window.
Description
Technical field
The present invention relates to the photoetching process in the semiconductor manufacturing, the optical adjacent correction method in the particularly bipolar exposure.
Background technology
Along with integrated circuit develops to deep submicron process, its critical size is also more and more littler.Because the exposure light source exposure wavelength that can provide has been close to the limit, traditional method that only reduces critical size by the exposure wavelength that reduces exposure light source has presented the problem of lack of resolution.In order to increase the resolution of photoetching process, developed for example, optical proximity correction (OPC, Optical Proximity Correction), bipolar exposure (DDL, Double Dipole Lithography) etc. resolution enhance technology (RET, Resolution Enhancement Technology) is assisted.Described optical proximity correction promptly is by the circuitous pattern on the photomask being proofreaied and correct the resolution that improves photoetching before photoetching.For example, in Chinese patent 02141166.2, disclose a kind of method of optical proximity correction, by increase on original circuitous pattern auxiliary pattern form correction pattern implement photomask on the correction of circuitous pattern.Described bipolar exposure then is by the circuitous pattern on the photomask is resolved into two parts, and respectively described two parts circuitous pattern is exposed successively and finally synthesize complete exposure figure.For example, in being the Chinese patent application of 200510084996.x, application number just mentioned a kind of method of bipolar exposure, by mask graph being resolved into two times mask graph, described mask graph has the mask graph of about half, form two phase shift masks according to described mask graph then, and successively expose, the inferior mask graph on two phase shift masks is transferred in the photographic layer.
In the present photoetching process optical proximity correction is combined with bipolar exposure, comprise mask manufacture stage and exposure stage, the described mask manufacture stage comprises: according to circuit pattern data circuitous pattern is resolved into the X utmost point and Y utmost point two parts electronic circuit figure, exposure environment when simulation exposes described two parts electronic circuit figure respectively, described two parts electronic circuit figure is carried out optical proximity correction respectively, make mask respectively through two parts electronic circuit figure of revising according to described.Described exposure stage comprises: load described X utmost point mask or Y utmost point mask; position alignment before the exposure; by exposure the circuitous pattern on the described mask is transferred in the photographic layer on the wafer; load another mask; position alignment before exposing is once more transferred to the circuitous pattern on described another mask in the photographic layer on the wafer by exposure.
Wherein, described optical proximity correction process, with reference to shown in Figure 1, execution in step s1 at first, respectively to the emulation that exposes of X utmost point electronic circuit figure and Y utmost point electronic circuit figure, the edge placement error of the synthesising pattern of the X utmost point and Y utmost point electronic circuit figure (EPE, Edge Placement Error) behind the calculation exposure; Execution in step s2, the edge placement error according to step s1 obtains moves described X utmost point electronic circuit figure; Execution in step s3 is once more to the circuitous pattern emulation that exposes, edge calculation placement error; Execution in step s4, the edge placement error according to step s3 obtains moves described Y utmost point electronic circuit figure; Execution in step s5 is once more to the circuitous pattern emulation that exposes; Execution in step s6 judges whether the edge placement error of described circuitous pattern is 0, if 0, then finish optical proximity correction, if be not 0, then return step s1.
Certainly, emulation and the adjustment order to the X utmost point or Y polar circuit figure also can be changed in the said process.Can see that from said process the purpose of optical proximity correction is in order to make the edge placement error of final simulation figure be reduced to 0 as far as possible, to strengthen resolution with this.Yet, only adopt the edge placement error data to carry out optical proximity correction at present as index, the process window (processwindow) of bipolar exposure technology there be not benefiting clearly.
Summary of the invention
The problem that the present invention solves is, the prior art optical adjacent correction method only adopts the edge placement error data to carry out optical proximity correction as index, and the process window of bipolar exposure technology is not had benefiting clearly.
For addressing the above problem, the invention provides a kind of optical adjacent correction method, comprise the following steps:
According to the initial edge placement error that is obtained, carry out the first electronic circuit figure correction step, obtain first edge placement error;
According to described first edge placement error, carry out the second electronic circuit figure correction step, obtain second edge placement error;
The difference of the difference of comparison first edge placement error, initial edge placement error and second edge placement error, first edge placement error is to determine the electronic circuit figure correction step to the edge placement error sensitivity;
Execution is to the electronic circuit figure correction step of edge placement error sensitivity;
Obtain described to the process window correlation parameter after the electronic circuit figure correction step of edge placement error sensitivity;
To another electronic circuit figure, carry out electronic circuit figure correction step based on described process window correlation parameter.
Optionally, described process window correlation parameter is light intensity slope (image intensity slope).
Compared with prior art, above-mentioned disclosed optical adjacent correction method has the following advantages: above-mentioned optical adjacent correction method is while CONSIDERING EDGE placement error and process window correlation parameter to the circuitous pattern correction time, light intensity slope for example, and choose the electronic circuit figure correction step of edge placement error sensitivity is carried out the specific aim correction, and the correction of process window correlation parameter specific aim is carried out in another electronic circuit figure correction.Because the correction of described process window correlation parameter has obviously for process window and benefits, thereby when described process window correlation parameter and edge placement error all reached designing requirement, described optical proximity correction will have obviously process window to be benefited.
Description of drawings
Fig. 1 is a prior art optical adjacent correction method process flow diagram;
Fig. 2 is a kind of embodiment process flow diagram of optical adjacent correction method of the present invention;
Fig. 3 is the refinement step process flow diagram of step s30 in the optical adjacent correction method shown in Figure 2.
Embodiment
Optical adjacent correction method disclosed in this invention is while CONSIDERING EDGE placement error and process window correlation parameter to the circuitous pattern correction time, choose the electronic circuit figure correction step of edge placement error sensitivity is carried out the specific aim correction, and the correction of process window correlation parameter specific aim is carried out in another electronic circuit figure correction.
With reference to shown in Figure 2, a kind of embodiment of optical adjacent correction method of the present invention comprises:
Step s10 according to the initial edge placement error (EPE0) that is obtained, carries out the first electronic circuit figure correction step, obtains first edge placement error (EPE1);
Step s20 according to described first edge placement error, carries out the second electronic circuit figure correction step, obtains second edge placement error (EPE2);
Step s30, the difference of the difference of comparison first edge placement error, initial edge placement error and second edge placement error, first edge placement error is to determine the electronic circuit figure correction step to the edge placement error sensitivity;
Step s40 carries out the electronic circuit figure correction step to the edge placement error sensitivity;
Step s50 obtains described to the process window correlation parameter after the electronic circuit figure correction step of edge placement error sensitivity;
Step s60 to another electronic circuit figure, carries out the electronic circuit figure correction step based on described process window correlation parameter;
Step s70, edge placement error and process window correlation parameter after the described electronic circuit figure of the acquisition step s60 correction step;
Step s80 judges whether described edge placement error and process window correlation parameter all reach setting value, if, then finish, if not, then return step s40.
In the concrete enforcement of said method, described process window correlation parameter can be the light intensity slope.
With reference to shown in Figure 3, in the concrete enforcement of said method, step s30 can also comprise the following steps:
Step s31, whether the difference of judging first edge placement error and initial edge placement error greater than the difference of second edge placement error and first edge placement error, i.e. (EPE1-EPE0)＞(EPE2-EPE1) is if execution in step s32 then, if not, execution in step s33 then;
Step s32, the first electronic circuit figure correction step is to the edge placement error sensitivity;
Step s33, the second electronic circuit figure correction step is to the edge placement error sensitivity.
Be described further for said method below in conjunction with accompanying drawing.
As previously mentioned, in bipolar exposure technology, in order to carry out optical proximity correction for circuitous pattern, at first can be earlier respectively for the expose emulation of environment of the electronic circuit figure after decomposing, compare by simulation figure and the targeted graphical that will be obtained, determine the mode of optical proximity correction.Therefore, at first simulation figure and targeted graphical are compared in this example, obtain to carry out the edge placement error of simulation figure and targeted graphical before the optical proximity correction, i.e. the initial edge placement error.Described edge placement error reflected simulation figure on dimension of picture with the gap of targeted graphical.
Because in bipolar exposure technology, earlier circuitous pattern is decomposed, for example resolve into X utmost point electronic circuit figure and Y utmost point electronic circuit figure, described edge placement error can obtain by following method: respectively to the emulation that exposes of X utmost point electronic circuit figure and Y utmost point electronic circuit figure; X utmost point electronic circuit figure and Y utmost point electronic circuit figure after the exposure emulation are synthesized complete circuitous pattern; Calculate the edge placement error of described circuitous pattern and corresponding targeted graphical.Described edge placement error is calculated by for example following formula: edge placement error=(targeted graphical size-simulation figure size)/2.Can simulation figure and targeted graphical be pressed the same way as segmentation by common used in industry software in this example, and calculate the difference in size of each segment figure of simulation figure and targeted graphical respectively, and use described formula and finally obtain edge placement error as initial edge placement error (EPE0).
After having obtained the initial edge placement error, just need determine that any electronic circuit figure correction step is more responsive for edge placement error by twice different electronic circuit figure correction step.Thereby, continuing with reference to shown in Figure 2, execution in step s10 according to the initial edge placement error that is obtained, carries out the first electronic circuit figure correction step, obtains first edge placement error.The described first electronic circuit figure can be an X utmost point electronic circuit figure, also can be Y utmost point electronic circuit figure.This sentences the first electronic circuit figure is that X utmost point electronic circuit figure is an example, promptly carries out X utmost point electronic circuit figure correction step according to the initial edge placement error that is obtained.Described X utmost point electronic circuit figure correction step is that X utmost point electronic circuit figure is carried out moving of certain distance in fact, displacement can be for example product of initial edge placement error and multiplier, described multiplier is with reference to used model of emulation and mask error enhancer (MEEF, MaskError-Enhancement Factor) decide, described mask error enhancer has reflected the influence of mask graph change in size for dimension of picture on the wafer of exposure back.Multiplier described in this example can be 0.1-0.6, for example 0.1,0.2,0.3,0.4,0.5,0.6 etc.After having obtained displacement,, the mobile respectively displacement that is obtained of each section of described X utmost point electronic circuit figure is come the correction of described X utmost point electronic circuit figure according to picture segmentation before.And if EPE for negative, represents that then the simulation figure size is bigger than targeted graphical size, the then adjustment in direction that figure should be reduced toward size.
After to the correction of X utmost point electronic circuit figure, respectively to the emulation that exposes of revised described X utmost point electronic circuit figure and uncorrected Y utmost point electronic circuit figure; X utmost point electronic circuit figure and Y utmost point electronic circuit figure after the exposure emulation are synthesized complete circuitous pattern; The edge placement error of calculating described circuitous pattern and corresponding targeted graphical is as first edge placement error (EPE1).
Next, execution in step s20 according to described first edge placement error, carries out the second electronic circuit figure correction step, obtains second edge placement error.Continue after having obtained first edge placement error, then to carry out Y utmost point electronic circuit figure correction step as described above.Similarly, described Y utmost point electronic circuit figure correction step also is that Y utmost point electronic circuit figure is carried out moving of certain distance in fact, displacement can be for example product of first edge placement error and multiplier, and described multiplier is with reference to used model of emulation and mask error enhancer.Multiplier described in this example can be 0.1-0.6, for example 0.1,0.2,0.3,0.4,0.5,0.6 etc.After having obtained displacement,, the mobile respectively displacement that is obtained of each section of described Y utmost point electronic circuit figure is come the correction of described Y utmost point electronic circuit figure according to picture segmentation before.
After to the correction of Y utmost point electronic circuit figure, respectively to the emulation that exposes of revised described X utmost point electronic circuit figure and revised described Y utmost point electronic circuit figure; X utmost point electronic circuit figure and Y utmost point electronic circuit figure after the exposure emulation are synthesized complete circuitous pattern; The edge placement error of calculating described circuitous pattern and corresponding targeted graphical is as second edge placement error (EPE2).
After respectively X utmost point electronic circuit figure and Y utmost point electronic circuit figure are revised and obtained respective edges placement error data, just can determine that then any electronic circuit figure correction step is for the more responsive step of edge placement error.Execution in step s30, the difference of the difference of comparison first edge placement error, initial edge placement error and second edge placement error, first edge placement error is to determine the electronic circuit figure correction step to the edge placement error sensitivity.Detailed process is as follows:
Continue with reference to shown in Figure 3, execution in step s31, whether the difference of judging first edge placement error and initial edge placement error greater than the difference of second edge placement error and first edge placement error, i.e. (EPE1-EPE0)＞(EPE2-EPE1).If the difference of first edge placement error and initial edge placement error is greater than the difference of second edge placement error and first edge placement error, the correction step that X utmost point electronic circuit figure then is described is bigger for the edge placement error variable effect of integrated circuit figure, the correction step that is to say X utmost point electronic circuit figure is more responsive for edge placement error, promptly as the judgement of step s32.And if the difference of second edge placement error and first edge placement error greater than the difference of first edge placement error and initial edge placement error, the correction step that Y utmost point electronic circuit figure then is described is bigger for the edge placement error variable effect of integrated circuit figure, the correction step that is to say Y utmost point electronic circuit figure is more responsive for edge placement error, promptly as the judgement of step s33.
Execution in step s40 carries out the electronic circuit figure correction step to the edge placement error sensitivity.The correction step of supposing X utmost point electronic circuit figure is then carried out X utmost point electronic circuit figure correction step once more to the edge placement error sensitivity.Described method is same as described above, and the edge placement error data that adopt are second edge placement error (EPE2).
Because X utmost point electronic circuit figure is to the edge placement error sensitivity, thereby finish by X utmost point electronic circuit figure correction step based on the correction of edge placement error, and also need consider by Y utmost point electronic circuit figure correction step, carry out correction based on the process window correlation parameter.Execution in step s50 obtains the process window correlation parameter after the described electronic circuit figure correction step.Described process window correlation parameter is chosen usually with numerical value change influences bigger parameter to process window, for example chooses the light intensity slope in this example.Described light intensity slope obtains by following method: respectively to revised X utmost point electronic circuit figure once more and above-mentioned through the emulation that exposes of revised Y utmost point electronic circuit figure once; X utmost point electronic circuit figure and Y utmost point electronic circuit figure after the exposure emulation are synthesized complete circuitous pattern; Obtain the light intensity value of each point on the simulation figure, then with each point position on the simulation figure as horizontal ordinate, corresponding light intensity value obtains the relation curve of light intensity and position as ordinate, calculates described slope of a curve then, is described light intensity slope.
Execution in step s60 according to described process window correlation parameter, carries out another electronic circuit figure correction step.As described above, after having obtained described light intensity slope, then carry out Y utmost point electronic circuit figure correction step.Described Y utmost point electronic circuit figure correction step also can be implemented by for example mobile Y utmost point electronic circuit figure.For example, the desired value of setting described light intensity slope is 0.15, then calculates the poor of current light intensity slope value and desired value, and multiply by certain coefficient, and for example critical size (CD) value obtains displacement.Described coefficient and desired value are determined according to the technology that reality adopts.
Execution in step s70 obtains edge placement error and process window correlation parameter after described another electronic circuit figure correction step.After finishing Y utmost point electronic circuit figure correction step, then respectively to the emulation that exposes of described X utmost point electronic circuit figure and Y utmost point electronic circuit figure; X utmost point electronic circuit figure and Y utmost point electronic circuit figure after the exposure emulation are synthesized complete circuitous pattern; Recomputate simulation figure and the edge placement error of targeted graphical and the light intensity slope of simulation figure of this moment.The computing method of described edge placement error and light intensity slope have just repeated no more with reference to explanation before herein.
After having regained edge placement error and light intensity slope, execution in step s80 judges whether described edge placement error and process window correlation parameter all reach setting value.In this example to the requirement of edge placement error be by revise make the value of the edge placement error that finally calculates be 0 or the limit approach 0, and be to make value＞0.08 of the light intensity slope that finally calculates by revising to the requirement of light intensity slope, need to prove that the desired value of light intensity slope only is an empirical value herein, as previously mentioned, desired value still needs to decide according to technology.And if both have arbitrary requirement that do not reach, then the correction step based on the two all will be carried out again, return step s40.And, think that then this correction has achieved the goal if both all reach requirement, can proceed the step of other optical proximity correction or make mask after revising with the circuitous pattern that obtain this moment.
In sum, above-mentioned optical adjacent correction method is while CONSIDERING EDGE placement error and process window correlation parameter to the circuitous pattern correction time, light intensity slope for example, and choose the electronic circuit figure correction step of edge placement error sensitivity is carried out the specific aim correction, and the correction of process window correlation parameter specific aim is carried out in another electronic circuit figure correction.Because the correction of described process window correlation parameter has obviously for process window and benefits, thereby when described process window correlation parameter and edge placement error all reached designing requirement, described optical proximity correction will have obviously process window to be benefited.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (6)
1. an optical adjacent correction method is characterized in that, comprises the following steps:
According to the initial edge placement error that is obtained, carry out the first electronic circuit figure correction step, obtain first edge placement error;
According to described first edge placement error, carry out the second electronic circuit figure correction step, obtain second edge placement error;
The difference of the difference of comparison first edge placement error, initial edge placement error and second edge placement error, first edge placement error is to determine the electronic circuit figure correction step to the edge placement error sensitivity;
Execution is to the electronic circuit figure correction step of edge placement error sensitivity;
Obtain described to the process window correlation parameter after the electronic circuit figure correction step of edge placement error sensitivity;
To another electronic circuit figure, carry out electronic circuit figure correction step based on described process window correlation parameter.
2. optical adjacent correction method as claimed in claim 1 is characterized in that, described optical adjacent correction method also comprises:
Edge placement error and the process window correlation parameter of acquisition after based on the electronic circuit figure correction step of described process window correlation parameter;
If described edge placement error or process window correlation parameter do not reach setting value, then repeat to the electronic circuit figure correction step of edge placement error sensitivity with based on the electronic circuit figure correction step of described process window correlation parameter, all reach setting value up to described edge placement error and process window correlation parameter.
3. optical adjacent correction method as claimed in claim 1 is characterized in that, described process window correlation parameter is the light intensity slope.
4. optical adjacent correction method as claimed in claim 1 is characterized in that, the described first electronic circuit figure and the second electronic circuit figure are respectively X utmost point electronic circuit figure and Y utmost point electronic circuit figure or Y utmost point electronic circuit figure and X utmost point electronic circuit figure.
5. optical adjacent correction method as claimed in claim 4, it is characterized in that, the difference of the difference of comparison first edge placement error, initial edge placement error and second edge placement error, first edge placement error comprises with definite electronic circuit figure correction step to the edge placement error sensitivity:
If the difference of first edge placement error, initial edge placement error, determines then that the first electronic circuit figure correction step is to the edge placement error sensitivity greater than the difference of second edge placement error, first edge placement error;
If the difference of first edge placement error, initial edge placement error, determines then that the second electronic circuit figure correction step is to the edge placement error sensitivity less than the difference of second edge placement error, first edge placement error.
6. optical adjacent correction method as claimed in claim 1, it is characterized in that, repeat to the electronic circuit figure correction step of edge placement error sensitivity with based on the electronic circuit figure correction step of described process window correlation parameter, all reach setting value up to described edge placement error or process window correlation parameter and comprise:
Execution is to the electronic circuit figure correction step of edge placement error sensitivity;
Obtain the process window correlation parameter;
To another electronic circuit figure, carry out electronic circuit figure correction step based on described process window correlation parameter;
Obtain edge placement error and process window correlation parameter;
If described edge placement error or process window correlation parameter do not reach setting value, then repeat above-mentioned steps;
If described edge placement error and process window correlation parameter all reach setting value, then stop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100403721A CN101625521B (en) | 2008-07-08 | 2008-07-08 | Optical proximity correction method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100403721A CN101625521B (en) | 2008-07-08 | 2008-07-08 | Optical proximity correction method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101625521A true CN101625521A (en) | 2010-01-13 |
| CN101625521B CN101625521B (en) | 2011-07-13 |
Family
ID=41521406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100403721A Expired - Fee Related CN101625521B (en) | 2008-07-08 | 2008-07-08 | Optical proximity correction method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101625521B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103186030A (en) * | 2011-12-27 | 2013-07-03 | 无锡华润上华科技有限公司 | Optical proximity correction method |
| US8541147B2 (en) | 2010-03-05 | 2013-09-24 | Semiconductor Manufacturing International (Shanghai) Corporation | System and method of selective optical pattern enhancement for semiconductor manufacturing |
| CN103744265A (en) * | 2014-01-29 | 2014-04-23 | 上海华力微电子有限公司 | Optical proximity correction method for improving process window |
| CN104570585A (en) * | 2013-10-23 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Optical proximity correction method |
| CN104950568A (en) * | 2014-03-25 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Optical proximity correction method and double patterning exposure method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7281222B1 (en) * | 2004-06-02 | 2007-10-09 | Advanced Micro Devices, Inc. | System and method for automatic generation of optical proximity correction (OPC) rule sets |
| US6996797B1 (en) * | 2004-11-18 | 2006-02-07 | International Business Machines Corporation | Method for verification of resolution enhancement techniques and optical proximity correction in lithography |
-
2008
- 2008-07-08 CN CN2008100403721A patent/CN101625521B/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8541147B2 (en) | 2010-03-05 | 2013-09-24 | Semiconductor Manufacturing International (Shanghai) Corporation | System and method of selective optical pattern enhancement for semiconductor manufacturing |
| CN103186030A (en) * | 2011-12-27 | 2013-07-03 | 无锡华润上华科技有限公司 | Optical proximity correction method |
| CN103186030B (en) * | 2011-12-27 | 2015-07-01 | 无锡华润上华科技有限公司 | Optical proximity correction method |
| CN104570585A (en) * | 2013-10-23 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Optical proximity correction method |
| CN103744265A (en) * | 2014-01-29 | 2014-04-23 | 上海华力微电子有限公司 | Optical proximity correction method for improving process window |
| CN103744265B (en) * | 2014-01-29 | 2016-09-07 | 上海华力微电子有限公司 | Improve the optical proximity correction method of process window |
| CN104950568A (en) * | 2014-03-25 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Optical proximity correction method and double patterning exposure method |
| CN104950568B (en) * | 2014-03-25 | 2020-02-07 | 中芯国际集成电路制造(上海)有限公司 | Optical proximity correction method and double pattern exposure method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101625521B (en) | 2011-07-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8762900B2 (en) | Method for proximity correction | |
| US6745372B2 (en) | Method and apparatus for facilitating process-compliant layout optimization | |
| Liebmann et al. | TCAD development for lithography resolution enhancement | |
| CN100465971C (en) | Method for improving optical proximity correction | |
| US8397182B2 (en) | Pattern verifying method, pattern verifying device, program, and manufacturing method of semiconductor device | |
| US7926002B2 (en) | Selective optical proximity layout design data correction | |
| CN110456610B (en) | Auxiliary graph and method for optimizing process window of through hole layer | |
| US7451068B2 (en) | Method and apparatus for generating an OPC segmentation based on modeled intensity gradients | |
| US20130239071A1 (en) | Method and apparatus for enhanced optical proximity correction | |
| WO2008055195A2 (en) | Closed-loop design for manufacturability process | |
| CN101625521B (en) | Optical proximity correction method | |
| US20120054694A1 (en) | Aerial Image Signatures | |
| US9779186B2 (en) | Methods for performing model-based lithography guided layout design | |
| JP2006292941A (en) | Optical proximity effect correction method and apparatus therefor | |
| US8533637B2 (en) | Retargeting based on process window simulation | |
| US8910098B1 (en) | Neighbor-aware edge fragment adjustment for optical proximity correction | |
| KR102570888B1 (en) | Method for correcting a mask layout and method of fabricating a semiconductor device using the same | |
| CN106707681B (en) | A method of enhancing OPC processing accuracy | |
| CN102117010A (en) | Optical adjacent correcting method | |
| Chiou et al. | Development of layout split algorithms and printability evaluation for double patterning technology | |
| Jia et al. | Robust mask design with defocus variation using inverse synthesis | |
| KR100688893B1 (en) | A method for forming a mask pattern of a semiconductor device | |
| US8250495B2 (en) | Mask decomposition for double dipole lithography | |
| US9811615B2 (en) | Simultaneous retargeting of layout features based on process window simulation | |
| WO2007048442A1 (en) | Method for forming a semiconductor device using optical proximity correction for the optical lithography |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110713 Termination date: 20190708 |