CN101621247B - Power factor correction circuit - Google Patents

Abstract

The invention discloses a power factor correction circuit which comprises a first inductor, a second inductor, a first multimodal switch, a second multimodal switch and a first capacitor, wherein the first inductor is connected between the first end of an alternating current power supply and the first end of the first multimodal switch, the second end and the third end of the first multimodal switch is connected to two ends of the first capacitor in a spanned way, the second inductor is connected between the second end of the alternating current power supply and the first end of the second multimodal switch, and the second end and the third end of the second multimodal switch are connected to two ends of the first capacitor in a spanned way. In the invention, a boost PFC circuit provided with the multimodal switches can improve the efficiency and the power density simultaneously. The invention can also reduce ripple waves of the inductors and the capacitor, the switching loss and the on-state loss of a power switch tube as well as the THD, and improve the PF of the circuit.

Description

A kind of circuit of power factor correction

Technical field

The present invention relates to a kind of circuit of power factor correction.

Background technology

In the rectification of AC-to DC (AC/DC) is used except realizing the translation function of voltage; Also need satisfy various standards to power factor PF (Power Factor), the requirement of total harmonic distortion THD (TotalHarmonics Distortion) and electromagnetic interference EMI (Electromagnetic Inference).Yet, along with the continuous increase of high power density high performance-price ratio product demand, need improve constantly switching frequency to reduce the volume of passive device, the result who improves frequency makes switching loss also increase simultaneously, so efficient is difficult to again guarantee.

Summary of the invention

Technical problem to be solved by this invention is exactly in order to overcome above deficiency, has proposed a kind of circuit of power factor correction that can raise the efficiency simultaneously with power density.

Technical problem of the present invention solves through following technical scheme:

A kind of circuit of power factor correction; Comprise first inductance, second inductance, the first polymorphic switch, the second polymorphic switch and first electric capacity; Said first inductance is connected between AC power first end and first polymorphic switch first end; Said first polymorphic switch second end and the 3rd end span are connected on the first electric capacity two ends, and said second inductance is connected between AC power second end and second polymorphic switch first end, and said second polymorphic switch second end and the 3rd end span are connected on the first electric capacity two ends.

The beneficial effect of the present invention and prior art contrast is: the boost pfc circuit that the present invention proposes with polymorphic switch, can raise the efficiency simultaneously and power density.The present invention can also reduce the ripple of inductance, electric capacity, reduces the switching loss and the on-state loss of power switch pipe, improves the PF of circuit, reduces THD.

Description of drawings

Fig. 1 is the structural representation of first kind of tri-state switch;

Fig. 2 is the structural representation of first kind of four attitude switch;

Fig. 3 is a kind of structural representation of five attitude switches;

Fig. 4 is the structural representation of second kind of tri-state switch;

Fig. 5 is the structural representation of second kind of four attitude switch;

Fig. 6 is the structural representation of the embodiment of the invention 1;

Fig. 7 is S1 among Fig. 6, S3 conducting, S2, the current direction sketch map when S4 turn-offs;

Fig. 8 is that S1 among Fig. 6, S3 turn-off the current direction sketch map when S2, S4 conducting;

Fig. 9 is S1 among Fig. 6, S2, S3, the S4 current direction sketch map when all turn-offing;

Current direction sketch map when Figure 10 is the whole conducting of S1 among Fig. 6, S3, S2, S4;

Figure 11 is the structural representation of the embodiment of the invention 2;

Figure 12 is S1 among Figure 11, S3 conducting, S2, the current direction sketch map when S4 turn-offs;

Figure 13 is that S1 among Figure 11, S3 turn-off the current direction sketch map when S2, S4 conducting;

Figure 14 is S1 among Figure 11, S2, S3, the S4 current direction sketch map when all turn-offing;

Current direction sketch map when Figure 15 is the whole conducting of S1 among Figure 11, S3, S2, S4;

Figure 16 is the structural representation of the embodiment of the invention 3;

Figure 17 is the structural representation of the embodiment of the invention 4;

Figure 18 is the structural representation of the embodiment of the invention 5;

Figure 19 is the structural representation of the embodiment of the invention 6;

Figure 20 is the structural representation of the embodiment of the invention 7;

Figure 21 is the structural representation of the embodiment of the invention 8;

Figure 22 is the structural representation of the embodiment of the invention 9;

Figure 23 is the structural representation of the embodiment of the invention 10;

Figure 24 is the structural representation of the embodiment of the invention 11;

Figure 25 is the structural representation of the embodiment of the invention 12;

Figure 26 is traditional no bridge boost pfc circuit structural representation;

Figure 27 is the traditional no bridge boost PFC and the inductive current comparison sketch map of the ternary no bridge boost PFC simulation waveform of the present invention;

Figure 28 is the traditional no bridge boost PFC and the inductive current ripple comparison sketch map of the ternary no bridge boost PFC simulation waveform of the present invention;

Figure 29 is the traditional no bridge boost PFC and the switching tube drive signal comparison sketch map of the ternary no bridge boost PFC simulation waveform of the present invention;

Figure 30 is the traditional no bridge boost PFC and the inductive drop comparison sketch map of the ternary no bridge boost PFC simulation waveform of the present invention;

Figure 31 is the sketch map that the metal-oxide-semiconductor among Fig. 6 is replaced to IGBT.

Embodiment

Below through concrete execution mode and combine accompanying drawing that the present invention is explained further details.

At first the definition to polymorphic switch (Multi-state Switching Cell is called for short MSSC) describes.Shown in Fig. 1-3, realize that the structure of polymorphic switch needs a transformer and a brachium pontis of being made up of switching tube, diode etc.If there are two windings on the former limit of transformer, then switching tube is two brachium pontis structures, and that realized is tri-state switch TSSC (Three-state Switching Cell); If there are three windings on the former limit of transformer, then brachium pontis is three brachium pontis structures, realization be four attitude switch FSSC (Four-state Switching Cell).There is N winding on former by that analogy limit, and switching tube is a N brachium pontis structure, realization be (N+1) attitude switch.

Like Fig. 4, shown in 5, the diode in Fig. 1, the polymorphic switch shown in 2 is replaced with FET.The difference of two kinds of structures is can only one-way flow with diode current; Can two-way flow with the field effect tube current, therefore can be used in all-wave power factor correction and the inverter circuit.

In the tri-state switch as shown in Figure 4, an end of the same name of transformer links to each other with a different name end.The different conducting combinations of four switching tubes have three operating states, promptly go up pipe and a pipe conducting simultaneously down for one, go up pipe conducting simultaneously and two pipe conductings simultaneously down for two, and this also is the principle of tri-state switch name.In the four attitude switches as shown in Figure 5, the secondary of transformer is linked to be triangular structure (being that each winding of secondary joins end to end), does the electric current that can make in three windings in former limit like this and equates that operation principle is similar with tri-state switch.By that analogy, (N+1) structure of attitude switch (N is the integer more than or equal to 4) and the structural similarity of four attitude switches, the number of windings of transformer is increased to N, and the brachium pontis number of switching tube also is increased to N simultaneously.Shown in Fig. 1-5, the b end among the figure is first end of polymorphic switch, and the c end among the figure is second end of polymorphic switch, and a end among the figure is the 3rd end of polymorphic switch.

With embodiment the present invention is further specified below:

Embodiment 1

As shown in Figure 6; A kind of circuit of power factor correction; Comprise first inductance L 1, second inductance L, 2, the first polymorphic switch, the second polymorphic switch and the first capacitor C o; Said first inductance L 1 is connected between AC power first end and first polymorphic switch first end; Said first polymorphic switch second end and the 3rd end span are connected on the first capacitor C o two ends, and said second inductance L 2 is connected between AC power second end and second polymorphic switch first end, and said second polymorphic switch second end and the 3rd end span are connected on the first capacitor C o two ends.

The said first polymorphic switch comprises the first transformer T1, the first diode D1, the second diode D2, the first FET S1, the second FET S2.

The former limit of said first transformer T1 winding first end all links to each other with first inductance L 1 with secondary winding first end; The former limit of said first transformer T1 winding second end links to each other with the first diode D1 anode, first FET S1 drain electrode; The first diode D1 negative electrode links to each other with the first capacitor C o is anodal; The said first FET S1 source electrode links to each other with the first capacitor C o negative pole, and the said first FET S1 gate coupled has control signal.

The said first transformer T1 secondary winding, second end links to each other with the second diode D2 anode, second FET S2 drain electrode; The second diode D2 negative electrode links to each other with the first capacitor C o is anodal; The said second FET S2 source electrode links to each other with the first capacitor C o negative pole; The said second FET S2 gate coupled has control signal, the said first transformer T1 former limit winding first end and secondary winding second end end of the same name each other.

The said second polymorphic switch comprises the second transformer T2, the 3rd diode D3, the 4th diode D4, the 3rd FET S3, the 4th FET S4.

The former limit of said second transformer T2 winding first end all links to each other with second inductance L 2 with secondary winding first end; The former limit of said second transformer T2 winding second end links to each other with the 3rd diode D3 anode, the 3rd FET S3 drain electrode; The 3rd diode D3 negative electrode links to each other with the first capacitor C o is anodal; Said the 3rd FET S3 source electrode links to each other with the first capacitor C o negative pole, and said the 3rd FET S3 gate coupled has control signal.

The said second transformer T2 secondary winding, second end links to each other with the 4th diode D4 anode, the 4th FET S4 drain electrode; The 4th diode D4 negative electrode links to each other with the first capacitor C o is anodal; Said the 4th FET S4 source electrode links to each other with the first capacitor C o negative pole; Said the 4th FET S4 gate coupled has control signal, the said second transformer T2 former limit winding first end and secondary winding second end end of the same name each other.

Fig. 6 is single-phase no bridge boost pfc circuit.AC is the input power supply in the circuit, and L1 and L2 are inductor rectifiers, and Co is an output capacitance, and Load is load, forms a tri-state switch by transformer T1, diode D1, diode D2 and FET S1, FET S2; Transformer T2, diode D3, diode D4 and FET S3, FET S4 form another tri-state switch.

The driving pulse of FET S1 and S3 is identical; The driving pulse of FET S2 and S4 is identical; The certain angle of driving pulse phase shift of S1 and S2 can any number of degrees of phase shift, and is best to the neutralization effect of harmonic wave during usually to 180 ° of tri-state switch structure phase shifts.If the former limit number of windings of transformer is N (N >=2), then phase shift angle is got 360 °/N usually.

The circuit of power factor correction operation principle is narrated as follows:

With AC power supplies is that positive half cycle is an example; Be that the terminal that AC links to each other with L1 is a positive voltage, the terminal that AC links to each other with L2 is a negative voltage, when the duty ratio D of switching tube＜0.5; Because 180 ° of the driving pulse phase shifts of S1 and S2; Therefore S1 and not conducting simultaneously of S2, that is S1, S3 conducting S2, S4 shutoff, the current direction under this mode of operation is as shown in Figure 7.Path one: the flow through winding → inductance L 2 that links to each other with FET S3 → the flow back into AC of the winding that links to each other with FET S1 → FET S1 → FET S3 → transformer T2 of inductance L 1 → transformer T1 of the electric current of power supply AC; Path two: the electric current of the power supply AC winding that links to each other with FET S2 → diode D2 → capacitor C 1 of inductance L 1 → transformer T1 and the winding → inductance L 2 that links to each other with FET S4 of load Load → FET S4 → transformer T2 → the flow back into AC that flows through.

When S1, S3 turn-off; When S2, S4 conducting; Mode of operation and S1, S3 conducting; S2, S4 are similar when turn-offing, and flowing to of electric current is as shown in Figure 8, path one: the flow through winding → inductance L 2 that links to each other with FET S4 → the flow back into AC of the winding that links to each other with FET S2 → FET S2 → FET S4 → transformer T2 of inductance L 1 → transformer T1 of the electric current of power supply AC; Path two: the flow through winding → inductance L 2 that links to each other with FET S3 → the flow back into AC of the winding that links to each other with FET S1 → diode D1 → capacitor C 1 → FET S3 → transformer T2 of inductance L 1 → transformer T1 of the electric current of power supply AC.

When S1, S2, S3, S4 all are in off state; Flowing to of electric current is as shown in Figure 9, path one: the electric current of the power supply AC winding that links to each other with FET S1 → diode D1 → capacitor C 1 of inductance L 1 → transformer T1 and the winding → inductance L 2 that links to each other with FET S3 of load Load → FET S3 → transformer T2 → the flow back into AC that flows through; Path two: the electric current of the power supply AC winding that links to each other with FET S2 → diode D2 → capacitor C 1 of inductance L 1 → transformer T1 and the winding → inductance L 2 that links to each other with FET S4 of load Load → FET S4 → transformer T2 → the flow back into AC that flows through.

When the duty ratio D of switching tube＞0.5, because 180 ° of the driving pulse phase shifts of S1 and S2, so S1, S2, S3, S4 have the moment of while conducting.Current direction when S1, S2, S3, S4 conducting simultaneously is shown in figure 10.Path one: the flow through winding → inductance L 2 that links to each other with FET S3 → the flow back into AC of the winding that links to each other with FET S1 → FET S1 → FET S3 → transformer T2 of inductance L 1 → transformer T1 of the electric current of power supply AC.Path two: the flow through winding → inductance L 2 that links to each other with FET S4 → the flow back into AC of the winding that links to each other with FET S2 → FET S2 → FET S4 → transformer T2 of inductance L 1 → transformer T1 of the electric current of power supply AC.

Embodiment 2

Shown in figure 11; The difference of present embodiment and embodiment 1 is: increased by second capacitor C 2 and the 3rd capacitor C 3; Said second capacitor C, 2 one ends are connected between the AC power and second inductance L 2, the coupling of the other end and the first capacitor C o negative pole, and said the 3rd capacitor C 3 one ends are connected between AC power and first inductance L 1, the other end and the first capacitor C o negative pole are coupled.High-frequency signal flows through from C2, C3 after increasing capacitor C 2, C3, and power frequency component flows through from FET, therefore can solve the EMI problem that possibly exist among the embodiment 1.Than more than 1 two filter capacitors of embodiment, other parts are all the same at input for present embodiment, and its drive pattern also is the same with embodiment 1.

The course of work of present embodiment is following, is that sinusoidal wave positive half cycle is an example with the AC power supplies, and promptly the terminal that links to each other with L1 of AC is a positive voltage, and the terminal that AC links to each other with L2 is a negative voltage.When the duty ratio D of switching tube＜0.5, because 180 ° of the driving pulse phase shifts of S1 and S2, so S1 and S2 can the while conductings, that is S1, S3 conducting S2, S4 shutoff, and the current direction under this mode of operation is shown in figure 12.Path one: the flow through winding → inductance L 2 that links to each other with FET S3 → the flow back into AC of the winding that links to each other with FET S1 → FET S1 → FET S3 → transformer T2 of inductance L 1 → transformer T1 of the electric current of power supply AC; Path two: the electric current of the power supply AC winding that links to each other with FET S1 → switching tube S1 → capacitor C 2 of inductance L 1 → transformer T1 → flow back into AC that flows through; Path three: the flow through winding → inductance L 2 that links to each other with FET S4 → the flow back into AC of the winding that links to each other with FET S2 → diode D2 → capacitor C 1 → FET S4 → transformer T2 of inductance L 1 → transformer T1 of the electric current of power supply AC; Path four: the electric current of the power supply AC winding that links to each other with FET S2 of inductance L 1 → transformer T1 → diode D2 → capacitor C 1 and load Load → capacitor C 2 → the flow back into AC that flows through.

As S1, when S3 turn-offs S2, S4 conducting; Pattern is similar with S1, S3 conducting S2, S4 when turn-offing; Flowing to of electric current is shown in figure 13, path one: the flow through winding → inductance L 2 that links to each other with FET S4 → the flow back into AC of the winding that links to each other with FET S2 → FET S2 → FET S4 → transformer T2 of inductance L 1 → transformer T1 of the electric current of power supply AC; Path two: the electric current of the power supply AC winding that links to each other with FET S2 → FET S2 → capacitor C 2 of inductance L 1 → transformer T1 → flow back into AC that flows through; Path three: the electric current of the power supply AC winding that links to each other with FET S1 → diode D1 → capacitor C 1 of inductance L 1 → transformer T1 and the winding → inductance L 2 that links to each other with FET S3 of load Load → FET S3 → transformer T2 → the flow back into AC that flows through; Path four: the electric current of the power supply AC winding that links to each other with FET S1 of inductance L 1 → transformer T1 → diode D1 → capacitor C 1 and load Load → capacitor C 2 → the flow back into AC that flows through.

When S1, S2, S3, S4 all are in off state; Flowing to of electric current is shown in figure 14, path one: the electric current of the power supply AC winding that links to each other with FET S1 → diode D1 → capacitor C 1 of inductance L 1 → transformer T1 and the winding → inductance L 2 that links to each other with FET S3 of load Load → FET S3 → transformer T2 → the flow back into AC that flows through; Path two: the electric current of the power supply AC winding that links to each other with FET S1 of inductance L 1 → transformer T1 → diode D1 → capacitor C 1 and load Load → capacitor C 2 → the flow back into AC that flows through; Path three: the electric current of power supply AC the flow through winding that links to each other with FET S2 → diode D2 → capacitor C 1 of inductance L 1 → transformer T1 and the winding → inductance L 2 that links to each other with FET S4 of load Load → FET S4 → transformer T2 → flow back into AC, path four: the electric current of the power supply AC winding that links to each other with FET S2 → diode D2 → capacitor C 1 and the load Load → capacitor C 2 of inductance L 1 → transformer T1 → the flow back into AC that flows through.

When the duty ratio D of switching tube＞0.5, because 180 ° of the driving pulse phase shifts of S1 and S2, so S1, S2, S3, S4 have the moment of conducting simultaneously, and the current direction when S1, S2, S3, S4 while conducting is shown in figure 15.Path one: the flow through winding → inductance L 2 that links to each other with FET S3 → the flow back into AC of the winding that links to each other with FET S1 → FET S1 → FET S3 → transformer T2 of inductance L 1 → transformer T1 of the electric current of power supply AC; Path two: the electric current of the power supply AC winding that links to each other with FET S1 → switching tube FET S1 → capacitor C 2 of inductance L 1 → transformer T1 → flow back into AC that flows through; Path three: the flow through winding → inductance L 2 that links to each other with FET S4 → the flow back into AC of the winding that links to each other with FET S2 → FET S2 → FET S4 → transformer T2 of inductance L 1 → transformer T1 of the electric current of power supply AC; Path four: the electric current of the power supply AC winding that links to each other with FET S2 → switching tube S2 → capacitor C 2 of inductance L 1 → transformer T1 → flow back into AC that flows through.

Embodiment 3

Shown in figure 16, the difference of present embodiment and embodiment 1 is: increased the 7th diode D7 and the 8th diode D8, can solve the EMI problem that possibly exist among the embodiment 1.Said the 7th diode D7 one end is connected between the AC power and second inductance L 2, the coupling of the other end and the first capacitor C o negative pole, and said the 8th diode D8 one end is connected between AC power and first inductance L 1, the other end and the first capacitor C o negative pole are coupled.

Embodiment 4

Shown in figure 17, the difference of present embodiment and embodiment 3 is: increased by the 3rd inductance L 3, said the 3rd inductance L 3 first ends link to each other with the anode of the 7th diode D7 and the 8th diode D8, the other end links to each other with the first capacitor C o negative pole.

Embodiment 5

Shown in figure 18, the difference of present embodiment and embodiment 1 is: the concrete structure of polymorphic switch.

In the present embodiment, the said first polymorphic switch comprises the first transformer T1, the 5th FET S5, the 6th FET S6, the first FET S1, the second FET S2.

The former limit of said first transformer T1 winding first end all links to each other with first inductance L 1 with secondary winding first end; The former limit of said first transformer T1 winding second end links to each other with the 5th FET S5 source electrode, first FET S1 drain electrode; The 5th FET S5 drain electrode links to each other with the first capacitor C o is anodal; The said first FET S1 source electrode links to each other with the first capacitor C o negative pole, and the said first FET S1, the 5th FET S5 gate coupled have control signal.

The said first transformer T1 secondary winding, second end links to each other with the 6th FET S6 source electrode, second FET S2 drain electrode; The 6th FET S6 drain electrode links to each other with the first capacitor C o is anodal; The said second FET S2 source electrode links to each other with the first capacitor C o negative pole; The said second FET S2, the 6th FET S6 gate coupled have control signal, the said first transformer T1 former limit winding first end and secondary winding second end end of the same name each other.

The said second polymorphic switch comprises the second transformer T2, the 7th field effect utmost point pipe S7, the 8th FET S8, the 3rd FET S3, the 4th FET S4.

The former limit of said second transformer T2 winding first end all links to each other with second inductance L 2 with secondary winding first end; The former limit of said second transformer T2 winding second end links to each other with the 7th field effect utmost point pipe S7 source electrode, the 3rd FET S3 drain electrode; The 7th field effect utmost point pipe S7 drain electrode links to each other with the first capacitor C o is anodal; Said the 3rd FET S3 source electrode links to each other with the first capacitor C o negative pole, and said the 3rd FET S3, the 7th field effect utmost point pipe S7 gate coupled have control signal.

The said second transformer T2 secondary winding, second end links to each other with the 8th field effect utmost point pipe S8 source electrode, the 4th FET S4 drain electrode; The 8th field effect utmost point pipe S8 drain electrode links to each other with the first capacitor C o is anodal; Said the 4th FET S4 source electrode links to each other with the first capacitor C o negative pole; Said the 4th FET S4, the 8th field effect utmost point pipe S8 gate coupled have control signal, the said second transformer T2 former limit winding first end and secondary winding second end end of the same name each other.

Embodiment 6

Shown in figure 19, the difference of present embodiment and embodiment 3 is: the concrete structure of polymorphic switch.The concrete structure of polymorphic switch is identical with embodiment 5 in the present embodiment.

Embodiment 7

Shown in figure 20, the difference of present embodiment and embodiment 1 is: the concrete structure of polymorphic switch.The present embodiment said first polymorphic switch comprises the first transformer T1, the first diode D1, the second diode D2, the 3rd diode D3, the first FET S1, the second FET S2, the 3rd FET S3, and said first transformer comprises the first former limit winding A1, the second former limit winding B1 and the 3rd former limit winding C1, the first secondary winding A2, the second secondary winding B2 and the 3rd secondary winding C2.

The first former limit winding A1, the second former limit winding B1 and the 3rd former limit winding C1 first end all link to each other with first inductance L 1; The said first former limit winding A1 links to each other with the first diode D1 anode, first FET S1 drain electrode; The first diode D1 negative electrode links to each other with the first capacitor C o is anodal; The said first FET S1 source electrode links to each other with the first capacitor C o negative pole, and the said first FET S1 gate coupled has control signal.

Said second former limit winding B1 second end links to each other with the second diode D2 anode, second FET S2 drain electrode; The second diode D2 negative electrode links to each other with the first capacitor C o is anodal; The said second FET S2 source electrode links to each other with the first capacitor C o negative pole, and the said second FET S2 gate coupled has control signal.

The said the 3rd former limit winding C1 second end links to each other with the 3rd diode D3 anode, the 3rd FET S3 drain electrode, the 3rd diode D3 negative electrode links to each other with the first capacitor C o is anodal; Said the 3rd FET S3 source electrode links to each other with the first capacitor C o negative pole; Said the 3rd FET S3 gate coupled has control signal, and each secondary winding of first transformer links to each other successively.

The said second polymorphic switch comprises the second transformer T2, the 4th diode D4, the 5th diode D5, the 6th diode D6, the 4th FET S4, the 5th FET S5, the 6th FET S6, and said second transformer comprises the 4th former limit winding A3, limit, Wuyuan winding B3 and the 6th former limit winding C3, fourth officer limit winding A4, the 5th secondary winding B4 and the 6th secondary winding C4.

The said the 4th former limit winding A3, limit, Wuyuan winding B3 and the 6th former limit winding C3 first end all link to each other with second inductance L 2; The said the 4th former limit winding A3 links to each other with the 4th diode D4 anode, the 4th FET S4 drain electrode; The 4th diode D4 negative electrode links to each other with the first capacitor C o is anodal; Said the 4th FET S4 source electrode links to each other with the first capacitor C o negative pole, and said the 4th FET S4 gate coupled has control signal.

Limit, said Wuyuan winding B3 second end links to each other with the 5th diode D5 anode, the 5th FET S5 drain electrode; The 5th diode D5 negative electrode links to each other with the first capacitor C o is anodal; Said the 5th FET S5 source electrode links to each other with the first capacitor C o negative pole, and said the 5th FET S5 gate coupled has control signal.

The said the 6th former limit winding C3 second end links to each other with the 6th diode D6 anode, the 6th FET S6 drain electrode; The 6th diode D6 negative electrode links to each other with the first capacitor C o is anodal; Said the 6th FET S6 source electrode links to each other with the first capacitor C o negative pole; Said the 6th FET S6 gate coupled has control signal, and each secondary winding of second transformer links to each other successively.

Embodiment 8

Shown in figure 21, present embodiment is with the difference of embodiment 3: the concrete structure of polymorphic switch is identical with embodiment 7 in the present embodiment.

Embodiment 9

Shown in figure 22, present embodiment is with the difference of embodiment 4: the concrete structure of polymorphic switch is identical with embodiment 7 in the present embodiment.

Embodiment 10

Shown in figure 23, the difference of present embodiment and embodiment 1 is: the concrete structure of polymorphic switch.The present embodiment said first polymorphic switch comprises the first transformer T1, the 7th FET S7, the 8th FET S8, the 9th FET S9, the first FET S1, the second FET S2, the 3rd FET S3, and said first transformer comprises the first former limit winding A1, the second former limit winding B1 and the 3rd former limit winding C1, the first secondary winding A2, the second secondary winding B2 and the 3rd secondary winding C2.

The first former limit winding A1, the second former limit winding B1 and the 3rd former limit winding C1 first end all link to each other with first inductance L 1; The said first former limit winding A1 links to each other with the 7th FET S7 source electrode, first FET S1 drain electrode; The 7th FET S7 drain electrode links to each other with the first capacitor C o is anodal; The said first FET S1 source electrode links to each other with the first capacitor C o negative pole, and the said first FET S1, the 7th FET S7 gate coupled have control signal.

Said second former limit winding B1 second end links to each other with the 8th FET S8 source electrode, second FET S2 drain electrode; The 8th FET S8 drain electrode links to each other with the first capacitor C o is anodal; The said second FET S2 source electrode links to each other with the first capacitor C o negative pole, and the said second FET S2, the 8th FET S8 gate coupled have control signal.

The said the 3rd former limit winding C1 second end links to each other with the 9th FET S9 source electrode, the 3rd FET S3 drain electrode; The 9th FET S9 drain electrode links to each other with the first capacitor C o is anodal; Said the 3rd FET S3 source electrode links to each other with the first capacitor C o negative pole; Said the 3rd FET S3, the 9th FET S9 gate coupled have control signal, and each secondary winding of first transformer links to each other successively; The said second polymorphic switch comprises the second transformer T2, the tenth FET S10, the 11 field effect utmost point pipe S11, the 12 FET S12, the 4th FET S4, the 5th FET S5, the 6th FET S6, and said second transformer comprises the 4th former limit winding A3, limit, Wuyuan winding B3 and the 6th former limit winding C3, fourth officer limit winding A4, the 5th secondary winding B4 and the 6th secondary winding C4.

The said the 4th former limit winding A3, limit, Wuyuan winding B3 and the 6th former limit winding C3 first end all link to each other with second inductance L 2; The said the 4th former limit winding A3 links to each other with the tenth FET S10 source electrode, the 4th FET S4 drain electrode; The tenth FET S10 drain electrode links to each other with the first capacitor C o is anodal; Said the 4th FET S4 source electrode links to each other with the first capacitor C o negative pole, and said the 4th FET S4, the tenth FET S10 gate coupled have control signal.

Limit, said Wuyuan winding B3 second end links to each other with the 11 FET S11 source electrode, the 5th FET S5 drain electrode, the 11 FET S11 drain electrode links to each other with the first capacitor C o is anodal; Said the 5th FET S5 source electrode links to each other with the first capacitor C o negative pole, and said the 5th FET S5, the 11 FET S11 gate coupled have control signal.

The said the 6th former limit winding C3 second end links to each other with the 12 FET S12 source electrode, the 6th FET S6 drain electrode, the 12 FET S12 drain electrode links to each other with the first capacitor C o is anodal; Said the 6th FET S6 source electrode links to each other with the first capacitor C o negative pole; Said the 6th FET S6, the 12 FET S12 gate coupled have control signal, and each secondary winding of second transformer links to each other successively.

Embodiment 11

Shown in figure 24, present embodiment is with the difference of embodiment 3: the concrete structure of polymorphic switch is identical with embodiment 10 in the present embodiment.

Embodiment 12

Shown in figure 25, present embodiment is with the difference of embodiment 4: the concrete structure of polymorphic switch is identical with embodiment 10 in the present embodiment.

The advantage of the topology that proposes in order to verify among the present invention is not carried out emulation relatively with the no bridge boost pfc circuit of traditional no bridge boost pfc circuit topological sum band tri-state switch of polymorphic switch to shown in Figure 26 respectively, and simulation result is shown in Figure 27-30.The bearing power that keeps two circuit, input, output voltage and input current ripple frequency be identical carries out parameter designing and emulation, and the main circuit parameter provides in table one.

Table one: the comparison of the no bridge boost PFC of tradition and the no bridge boost pfc circuit parameter of band tri-state switch

Figure 27 is the input inductance current waveform of the no bridge boost PFC of tradition and the no bridge boost PFC of band tri-state switch, and the two input current effective value is basic identical, and Figure 28 is the ripple of inductive current.Because two local differences that the maximum ripple of topology occurs, so can't obtain maximum ripple value simultaneously in the same moment accurately, the ripple with place, inductive current summit compares here.Though can find out that by Figure 28 the switching frequency of ternary no bridge boost PFC switching tube is merely the half the of the no bridge boostPFC of tradition; But the operating frequency of inductance is identical with the ripple frequency of the no bridge boost PFC of tradition; This also is that ternary no bridge boost PFC has one of more high efficiency reason; The switching tube frequency is different when being identical ripple frequency, and the switching loss of ternary no bridge boost PFC is littler than traditional no bridge boostPFC.

Figure 29 is switching tube drive signal waveform figure, can be found out that by the frequency values of measuring the frequency of the no bridge boost PFC of tradition is 200kHz, and the switching frequency of ternary no bridge boost PFC is 100kHz.Figure 30 is the oscillogram of inductive drop; The inductive drop of ternary no bridge boost PFC has more ripples in the same cycle be zero; This is of value to the PF value that improves circuit and reduces THD, and withstand voltage the half the of the no bridge boost PFC of tradition that be merely, and can reduce the volume of inductance like this.

Can find out if keep identical inductive current ripple size and frequency that from comparative result the switching frequency that needs is different, thereby make the switching frequency of polymorphic no bridge boost PFC reduce, corresponding efficient improves.Since this moment ternary no bridge boost PFC also corresponding the reducing of inductance value, the size sum of inductance and transformer does not have increase, and is basic identical with the inductance size of traditional no bridge boost PFC.

In addition,, adopt identical switching frequency if only keep the inductive current ripple of identical size, the increase that the inductive current ripple frequency of then ternary no bridge boost PFC can be at double, the volume of inductance and transformer can significantly reduce at this moment.The inductance value of the no bridge boost of single-phase three-state PFC is that the inductance value that 1/4, four attitude of the no bridge boost PFC of tradition does not have a bridge boost PFC is about 1/9 of traditional no bridge boost PFC, and its THD is also less than traditional circuit.

Common inductor design process is following:

If inductance value is L

The maximum current peak that flows through inductance is Io

The windows of magnetic cores utilance is Kw

Current in wire density is Jc

Peakflux density is Bmax

The needed product of areas of inductance is AP

Design principle according to inductance can draw:

$\mathrm{AP}=\frac{L*{\mathrm{<figure-callout\; id="2"\; label="Io"\; filenames="H2009101091276E00013.png,H2009101091276E00024.png"\; state="\{\{state\}\}">Io</figure-callout>}}^2}{\mathrm{Kw}*B\max *\mathrm{Jc}}$

Order

$K=\frac{{\mathrm{<figure-callout\; id="2"\; label="Io"\; filenames="H2009101091276E00013.png,H2009101091276E00024.png"\; state="\{\{state\}\}">Io</figure-callout>}}^2}{\mathrm{Kw}*B\max *\mathrm{Jc}}$

Can draw

AP＝K*L

AP is the product of magnetic core window area and magnetic core sectional area, if select identical K for use, then the size of inductance volume becomes certain proportional relationship with inductance value, and why Here it is uses ternary no bridge boostPFC can obviously reduce the reason of inductor size.

This shows that ternary no bridge boost PFC can improve circuit characteristic, and design the size that significantly improves efficient or significantly reduce passive device as required.

The present invention proposes the multiple polymorphic no bridge boost pfc circuit structure that can improve circuit characteristic, and the advantage of using this structure is following:

1) polymorphic no bridge boost pfc converter does not need special flow equalizing circuit, because transformer can natural current-sharing.

2) stress of reduction passive device such as electric capacity (dc-link capacitance, filter capacitor) and inductance (filter inductance, buck inductance).

3) reduce the on-state and the switching loss (can use the P cock pipe under the equal-wattage grade) of switching tube.

4) improve system dynamic characteristic.

5) improve systematic function, so can improve PF reduction THD because the zero crossing of inductive drop increases.

6) design the size that can significantly improve efficient or reduce passive device as required.

Above content is to combine concrete preferred implementation to the further explain that the present invention did, and can not assert that practical implementation of the present invention is confined to these explanations.Those of ordinary skill for technical field under the present invention; Under the prerequisite that does not break away from the present invention's design; Can also make some simple deduction or replace; For example the polymorphic construction of switch among the embodiment 2 use embodiment 5 perhaps changes polymorphic switch into four attitude switches or N (N >=5) attitude switch or the like, all should be regarded as belonging to protection scope of the present invention.Above-mentioned in addition all FETs replace also being regarded as belonging to protection scope of the present invention with the switching tube of insulated gate bipolar transistor IGBT (Insulated Gate Bipolar Transistor) (please refer to Figure 31) or other types.

Claims (9)

1. circuit of power factor correction; It is characterized in that: comprise first inductance (L1), second inductance (L2), the first polymorphic switch, the second polymorphic switch and first electric capacity (Co); Said first inductance (L1) is connected between AC power first end and first polymorphic switch first end; Said first polymorphic switch second end and the 3rd end span are connected on first electric capacity (Co) two ends; Said second inductance (L2) is connected between AC power second end and second polymorphic switch first end, and said second polymorphic switch second end and the 3rd end span are connected on first electric capacity (Co) two ends; The said first polymorphic switch and the said second polymorphic switch are N+1 attitude switch, and N is the integer more than or equal to 2;

When N=2, be tri-state switch, comprise a transformer and two brachium pontis, said transformer has a former limit winding and a secondary winding, and first end of said former limit winding links to each other with secondary winding first end, and the end that links to each other is first end of said tri-state switch; Second end of said former limit winding connects the middle-end of a brachium pontis, and second end of said secondary winding connects the middle-end of another brachium pontis; The lower ends of said two brachium pontis, the end that links to each other is second end of said tri-state switch; The upper end of said two brachium pontis links to each other, and the end that links to each other is the 3rd end of said tri-state switch; Second end end of the same name each other of first end of said former limit winding and said secondary winding;

When N＞2, be N+1 attitude switch, comprise a transformer and N brachium pontis, said transformer comprises N former limit winding and N secondary winding, and the end of the same name of said N former limit winding links to each other, and continuous the end is first end of said N+1 attitude switch; Said N secondary winding joins end to end, and the end of the same name of each secondary winding links to each other with the different name end of adjacent secondary winding; The connect one to one middle-end of N brachium pontis of the different name end of said N former limit winding, the lower ends of a said N brachium pontis, the continuous end is second end of said N+1 attitude switch; The upper end of a said N brachium pontis links to each other, and the end that links to each other is the 3rd end of said N+1 attitude switch.

2. circuit of power factor correction according to claim 1; It is characterized in that: also comprise second electric capacity (C2) and the 3rd electric capacity (C3); Said second electric capacity (C2) end is connected between AC power and second inductance (L2), the coupling of the other end and first electric capacity (Co) negative pole, and said the 3rd electric capacity (C3) end is connected between AC power and first inductance (L1), the other end and first electric capacity (Co) negative pole are coupled.

3. circuit of power factor correction according to claim 1; It is characterized in that: also comprise the 7th diode (D7) and the 8th diode (D8); Said the 7th diode (D7) negative electrode is connected between AC power and second inductance (L2), the coupling of anode and first electric capacity (Co) negative pole, and said the 8th diode (D8) negative electrode is connected between AC power and first inductance (L1), anode and first electric capacity (Co) negative pole are coupled.

4. circuit of power factor correction according to claim 3; It is characterized in that: also comprise the 3rd inductance (L3), said the 3rd inductance (L3) first end links to each other with the anode of the 7th diode (D7) and the 8th diode (D8), the other end links to each other with first electric capacity (Co) negative pole.

5. according to the arbitrary described circuit of power factor correction of claim 1-4, it is characterized in that: the said first polymorphic switch comprises first transformer (T1), first diode (D1), second diode (D2), first FET (S1), second FET (S2);

The former limit of said first transformer (T1) winding first end all links to each other with first inductance (L1) with secondary winding first end; The former limit of said first transformer (T1) winding second end links to each other with first diode (D1) anode, first FET (S1) drain electrode; First diode (D1) negative electrode links to each other with first electric capacity (Co) is anodal; Said first FET (S1) source electrode links to each other with first electric capacity (Co) negative pole, and said first FET (S1) gate coupled has control signal;

Said first transformer (T1) secondary winding second end links to each other with second diode (D2) anode, second FET (S2) drain electrode; Second diode (D2) negative electrode links to each other with first electric capacity (Co) is anodal; Said second FET (S2) source electrode links to each other with first electric capacity (Co) negative pole; Said second FET (S2) gate coupled has control signal, the former limit of said first transformer (T1) winding first end and secondary winding second end end of the same name each other;

The said second polymorphic switch comprises second transformer (T2), the 3rd diode (D3), the 4th diode (D4), the 3rd FET (S3), the 4th FET (S4);

The former limit of said second transformer (T2) winding first end all links to each other with second inductance (L2) with secondary winding first end; The former limit of said second transformer (T2) winding second end links to each other with the 3rd diode (D3) anode, the 3rd FET (S3) drain electrode; The 3rd diode (D3) negative electrode links to each other with first electric capacity (Co) is anodal; Said the 3rd FET (S3) source electrode links to each other with first electric capacity (Co) negative pole, and said the 3rd FET (S3) gate coupled has control signal;

Said second transformer (T2) secondary winding second end links to each other with the 4th diode (D4) anode, the 4th FET (S4) drain electrode; The 4th diode (D4) negative electrode links to each other with first electric capacity (Co) is anodal; Said the 4th FET (S4) source electrode links to each other with first electric capacity (Co) negative pole; Said the 4th FET (S4) gate coupled has control signal, the former limit of said second transformer (T2) winding first end and secondary winding second end end of the same name each other.

6. according to the arbitrary described circuit of power factor correction of claim 1-4, it is characterized in that: the said first polymorphic switch comprises first transformer (T1), the 5th FET (S5), the 6th FET (S6), first FET (S1), second FET (S2);

The former limit of said first transformer (T1) winding first end all links to each other with first inductance (L1) with secondary winding first end; The former limit of said first transformer (T1) winding second end links to each other with the 5th FET (S5) source electrode, first FET (S1) drain electrode; The 5th FET (S5) drain electrode links to each other with first electric capacity (Co) is anodal; Said first FET (S1) source electrode links to each other with first electric capacity (Co) negative pole, and said first FET (S1), the 5th FET (S5) gate coupled have control signal;

Said first transformer (T1) secondary winding second end links to each other with the 6th FET (S6) source electrode, second FET (S2) drain electrode; The 6th FET (S6) drain electrode links to each other with first electric capacity (Co) is anodal; Said second FET (S2) source electrode links to each other with first electric capacity (Co) negative pole; Said second FET (S2), the 6th FET (S6) gate coupled have control signal, the former limit of said first transformer (T1) winding first end and secondary winding second end end of the same name each other;

The said second polymorphic switch comprises second transformer (T2), the 7th field effect utmost point pipe (S7), the 8th FET (S8), the 3rd FET (S3), the 4th FET (S4);

The former limit of said second transformer (T2) winding first end all links to each other with second inductance (L2) with secondary winding first end; The former limit of said second transformer (T2) winding second end links to each other with the 7th field effect utmost point pipe (S7) source electrode, the 3rd FET (S3) drain electrode; The drain electrode of the 7th field effect utmost point pipe (S7) links to each other with first electric capacity (Co) is anodal; Said the 3rd FET (S3) source electrode links to each other with first electric capacity (Co) negative pole, and said the 3rd FET (S3), the 7th field effect utmost point pipe (S7) gate coupled have control signal;

Said second transformer (T2) secondary winding second end links to each other with the 8th field effect utmost point pipe (S8) source electrode, the 4th FET (S4) drain electrode; The drain electrode of the 8th field effect utmost point pipe (S8) links to each other with first electric capacity (Co) is anodal; Said the 4th FET (S4) source electrode links to each other with first electric capacity (Co) negative pole; Said the 4th FET (S4), the 8th field effect utmost point pipe (S8) gate coupled have control signal, the former limit of said second transformer (T2) winding first end and secondary winding second end end of the same name each other.

7. according to the arbitrary described circuit of power factor correction of claim 1-4; It is characterized in that: the said first polymorphic switch comprises first transformer (T1), first diode (D1), second diode (D2), the 3rd diode (D3), first FET (S1), second FET (S2), the 3rd FET (S3), and said first transformer comprises the first former limit winding (A1), the second former limit winding (B1) and the 3rd former limit winding (C1), the first secondary winding (A2), the second secondary winding (B2) and the 3rd secondary winding (C2);

The first former limit winding (A1), the second former limit winding (B1) and the 3rd former limit winding (C1) first end all link to each other with first inductance (L1); The said first former limit winding (A1) second end links to each other with first diode (D1) anode, first FET (S1) drain electrode; First diode (D1) negative electrode links to each other with first electric capacity (Co) is anodal; Said first FET (S1) source electrode links to each other with first electric capacity (Co) negative pole, and said first FET (S1) gate coupled has control signal; First end of the said first former limit winding (A1), the second former limit winding (B1) and the 3rd former limit winding (C1) is an end of the same name;

The said second former limit winding (B1) second end links to each other with second diode (D2) anode, second FET (S2) drain electrode; Second diode (D2) negative electrode links to each other with first electric capacity (Co) is anodal; Said second FET (S2) source electrode links to each other with first electric capacity (Co) negative pole, and said second FET (S2) gate coupled has control signal;

The said the 3rd former limit winding (C1) second end links to each other with the 3rd diode (D3) anode, the 3rd FET (S3) drain electrode, the 3rd diode (D3) negative electrode links to each other with first electric capacity (Co) is anodal; Said the 3rd FET (S3) source electrode links to each other with first electric capacity (Co) negative pole; Said the 3rd FET (S3) gate coupled has control signal; Each secondary winding of first transformer links to each other successively, and the end of the same name of each secondary winding links to each other with the different name end of adjacent secondary winding;

The said second polymorphic switch comprises second transformer (T2), the 4th diode (D4), the 5th diode (D5), the 6th diode (D6), the 4th FET (S4), the 5th FET (S5), the 6th FET (S6), and said second transformer comprises the 4th former limit winding (A3), limit, Wuyuan winding (B3) and the 6th former limit winding (C3), fourth officer limit winding (A4), the 5th secondary winding (B4) and the 6th secondary winding (C4);

The said the 4th former limit winding (A3), limit, Wuyuan winding (B3) and the 6th former limit winding (C3) first end all link to each other with second inductance (L2); The said the 4th former limit winding (A3) second end links to each other with the 4th diode (D4) anode, the 4th FET (S4) drain electrode; The 4th diode (D4) negative electrode links to each other with first electric capacity (Co) is anodal; Said the 4th FET (S4) source electrode links to each other with first electric capacity (Co) negative pole, and said the 4th FET (S4) gate coupled has control signal; First end of the said the 4th former limit winding (A3), limit, Wuyuan winding (B3) and the 6th former limit winding (C3) is an end of the same name;

Limit, said Wuyuan winding (B3) second end links to each other with the 5th diode (D5) anode, the 5th FET (S5) drain electrode; The 5th diode (D5) negative electrode links to each other with first electric capacity (Co) is anodal; Said the 5th FET (S5) source electrode links to each other with first electric capacity (Co) negative pole, and said the 5th FET (S5) gate coupled has control signal;

The said the 6th former limit winding (C3) second end links to each other with the 6th diode (D6) anode, the 6th FET (S6) drain electrode; The 6th diode (D6) negative electrode links to each other with first electric capacity (Co) is anodal; Said the 6th FET (S6) source electrode links to each other with first electric capacity (Co) negative pole; Said the 6th FET (S6) gate coupled has control signal, and each secondary winding of second transformer links to each other successively, and the end of the same name of each secondary winding links to each other with the different name end of adjacent secondary winding.

8. according to the arbitrary described circuit of power factor correction of claim 1-4; It is characterized in that: the said first polymorphic switch comprises first transformer, the 7th FET (S7), the 8th FET (S8), the 9th FET (S9), first FET (S1), second FET (S2), the 3rd FET (S3), and said first transformer comprises the first former limit winding (A1), the second former limit winding (B1) and the 3rd former limit winding (C1), the first secondary winding (A2), the second secondary winding (B2) and the 3rd secondary winding (C2);

The first former limit winding (A1), the second former limit winding (B1) and the 3rd former limit winding (C1) first end all link to each other with first inductance (L1); The said first former limit winding (A1) second end links to each other with the 7th FET (S7) source electrode, first FET (S1) drain electrode; The 7th FET (S7) drain electrode links to each other with first electric capacity (Co) is anodal; Said first FET (S1) source electrode links to each other with first electric capacity (Co) negative pole, and said first FET (S1), the 7th FET (S7) gate coupled have control signal; First end of the said first former limit winding (A1), the second former limit winding (B1) and the 3rd former limit winding (C1) is an end of the same name;

The said second former limit winding (B1) second end links to each other with the 8th FET (S8) source electrode, second FET (S2) drain electrode; The 8th FET (S8) drain electrode links to each other with first electric capacity (Co) is anodal; Said second FET (S2) source electrode links to each other with first electric capacity (Co) negative pole, and said second FET (S2), the 8th FET (S8) gate coupled have control signal;

The said the 3rd former limit winding (C1) second end links to each other with the 9th FET (S9) source electrode, the 3rd FET (S3) drain electrode; The 9th FET (S9) drain electrode links to each other with first electric capacity (Co) is anodal; Said the 3rd FET (S3) source electrode links to each other with first electric capacity (Co) negative pole; Said the 3rd FET (S3), the 9th FET (S9) gate coupled have control signal; Each secondary winding of first transformer links to each other successively, and the end of the same name of each secondary winding links to each other with the different name end of adjacent secondary winding;

The said second polymorphic switch comprises second transformer, the tenth FET (S10), the 11 field effect utmost point pipe (S11), the 12 FET (S12), the 4th FET (S4), the 5th FET (S5), the 6th FET (S6), and said second transformer comprises the 4th former limit winding (A3), limit, Wuyuan winding (B3) and the 6th former limit winding (C3), fourth officer limit winding (A4), the 5th secondary winding (B4) and the 6th secondary winding (C4);

The said the 4th former limit winding (A3), limit, Wuyuan winding (B3) and the 6th former limit winding (C3) first end all link to each other with second inductance (L2); The said the 4th former limit winding (A3) second end links to each other with the tenth FET (S10) source electrode, the 4th FET (S4) drain electrode; The tenth FET (S10) drain electrode links to each other with first electric capacity (Co) is anodal; Said the 4th FET (S4) source electrode links to each other with first electric capacity (Co) negative pole, and said the 4th FET (S4), the tenth FET (S10) gate coupled have control signal; The said the 4th former limit winding (A3), limit, Wuyuan winding (B3) and the 6th former limit winding (C3) first end are end of the same name;

Limit, said Wuyuan winding (B3) second end links to each other with the 11 FET (S11) source electrode, the 5th FET (S5) drain electrode, the 11 FET (S11) drain electrode links to each other with first electric capacity (Co) is anodal; Said the 5th FET (S5) source electrode links to each other with first electric capacity (Co) negative pole, and said the 5th FET (S5), the 11 FET (S11) gate coupled have control signal; The said the 6th former limit winding (C3) second end links to each other with the 12 FET (S12) source electrode, the 6th FET (S6) drain electrode, the 12 FET (S12) drain electrode links to each other with first electric capacity (Co) is anodal; Said the 6th FET (S6) source electrode links to each other with first electric capacity (Co) negative pole; Said the 6th FET (S6), the 12 FET (S12) gate coupled have control signal; Each secondary winding of second transformer links to each other successively, and the end of the same name of each secondary winding links to each other with the different name end of adjacent secondary winding.

9. according to the arbitrary described circuit of power factor correction of claim 1-4, it is characterized in that: the said first polymorphic switch comprises first transformer (T1), first diode (D1), second diode (D2), IGBT pipe, the 2nd IGBT pipe;

The former limit of said first transformer (T1) winding first end all links to each other with first inductance (L1) with secondary winding first end; The former limit of said first transformer (T1) winding second end links to each other with first diode (D1) anode, an IGBT pipe collector; First diode (D1) negative electrode links to each other with first electric capacity (Co) is anodal; Said IGBT pipe emitter-base bandgap grading links to each other with first electric capacity (Co) negative pole, and a said IGBT tube grid is coupled with control signal;

Said first transformer (T1) secondary winding second end links to each other with second diode (D2) anode, the 2nd IGBT pipe collector; Second diode (D2) negative electrode links to each other with first electric capacity (Co) is anodal; Said the 2nd IGBT pipe emitter-base bandgap grading links to each other with first electric capacity (Co) negative pole; Said the 2nd IGBT tube grid is coupled with control signal, the former limit of said first transformer (T1) winding first end and secondary winding second end end of the same name each other;

The said second polymorphic switch comprises second transformer (T2), the 3rd diode (D3), the 4th diode (D4), the 3rd IGBT pipe, the 4th IGBT pipe;

The former limit of said second transformer (T2) winding first end all links to each other with second inductance (L2) with secondary winding first end; The former limit of said second transformer (T2) winding second end links to each other with the 3rd diode (D3) anode, the 3rd IGBT pipe collector; The 3rd diode (D3) negative electrode links to each other with first electric capacity (Co) is anodal; Said the 3rd IGBT pipe emitter-base bandgap grading links to each other with first electric capacity (Co) negative pole, and said the 3rd IGBT tube grid is coupled with control signal;

Said second transformer (T2) secondary winding second end links to each other with the 4th diode (D4) anode, the 4th IGBT pipe collector; The 4th diode (D4) negative electrode links to each other with first electric capacity (Co) is anodal; Said the 4th IGBT pipe emitter-base bandgap grading links to each other with first electric capacity (Co) negative pole; Said the 4th IGBT tube grid is coupled with control signal, the former limit of said second transformer (T2) winding first end and secondary winding second end end of the same name each other.

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