CN101621062A - Device structure and method for improving schottky breakdown voltage without effect of mosfet-schottky integration - Google Patents
Device structure and method for improving schottky breakdown voltage without effect of mosfet-schottky integration Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
Abstract
The present invention provides a device structure and method for improving a Schottky breakdown voltage without effect of MOSFET-Schottky integration, the structure includes an active unit region having a plurality of power transistor units. Each power transistor unit has a plane Schottky diode having a Schottky junction barrier metal covering on a rabbet between the separated body regions of two neighboring power transistor units, wherein the separated bode region plays a function of adjusting the Schottky diode drain current of each power transistor unit. Each plane Schottky diode also has a Shannon implantation region locating in the rabbet and between the separated body regions of the two neighboring power transistor units to further adjust the drain current of the Schottky diode. The separated body region of each power transistor unit also includes a heavy body doping region locating nearby a source electrode region and enclosing the Schottky diode to form a junction barrier Schottky pocket region.
Description
Technical field
The present invention relates to a kind of semiconductor power devices, be meant a kind of manufacturing process improvement, novel especially with mos field effect transistor (MOSFET) device of schottky source node, and the configuration of device.
Background technology
For power consumption, the increase switch speed that reduces semiconductor power devices, need more be devoted to reduce conducting resistance (on-resistance) and grid capacitance, Schottky diode is integrated in the semiconductor power devices just like mos field effect transistor.The mos field effect transistor that is depicted as standard as Figure 1A and 1B is crossed body diode and the device integrated with Schottky diode, with the performance of improvement mos field effect transistor.In the improvement of mos field effect transistor usefulness, can improve the application usefulness of H bridge and synchronous rectification, especially shown in Figure 1A, mos field effect transistor and Junction Barrier Controlled Schottky (Junction Barriercontrolled Schottky, JBS) Regional Integration, the Junction Barrier Controlled Schottky (JBS) that is integrated can be a schottky diode array and a PN junction net and intersperse among in some Schottky nodes.PN junction can be nipped off the channel region under (pinch-off) Schottky node, in case when arriving critical reverse biased value to suppress the formation of a large amount of reverse leakage currents.The protection effect (shielding effect) that depletion layer (depletion layer) is produced also can improve puncture voltage, yet, the resistance of series connection increases also can produce adverse effect (tradeoff), in addition, in Junction Barrier Controlled Schottky (JBS), integrate PN junction and can roll up surface area, consider with practicality, need to reduce the Schottky node zone that is used for forward conduction comprehensively.In the case, the forward voltage drop of conducting state can increase because of the minimizing in comprehensive Schottky node zone.Figure 1B is depicted as groove type metal oxide Schottky (the trench MOS barrierSchottky of integration, TMBS), this integrates groove type metal oxide Schottky and comprises that schottky diode array is interted and intersperse among in the metal oxide partial groove, and the metal of coupling of the electric charge between the most charged carriers of the terrace part of extension/drift region (majority charge carrier) and trench isolations sidewall can cause the electric field of Schottky node to redistribute, and improves puncture voltage and reduces reverse leakage current.
A kind of method of utilizing source electrode schottky junctions face as body node in the semiconductor power devices of No. 4675713 patent disclosure of the U.S.; The U.S. the 4th, 983, the manufacture method of No. 535 a kind of production of patent disclosure depletion MOSs (DMOS), it is the top that source electrode and a refractory metal Schottky barrier (refractory metal Schottky barrier) is arranged at body regions.Yet these devices still have the restricted of the high barrier height metal of use, and device usefulness can't satisfy present application about reducing the demand of impedance and high drive current.
A kind of improved production depletion MOS of invention for this reason shown in Figure 2, it has the configuration of improvement, adjacent trench and be provided with a source electrode-body node groove in abutting connection with the source electrode place particularly, it sees through to produce to resist along the implantation of trenched side-wall wears function (anti-punch).See through in high barrier height metal of bottom deposit of source electrode-body node groove and integrate Schottky diode to form one, reach the function of integrating the Schottky node, more above high barrier height metal, cover low barrier height metal of deposition, so that ohm node (ohmic contact) of source electrode and body to be provided.The advantage that production depletion MOS device as shown in Figure 2 provides is for being integrated in Schottky in each unit and not losing crystal grain active region (die active area) to form the Schottky as older target.Yet, for reaching the required high barrier height metal of permissible in off position low-leakage current, can deposit high barrier height metal and low barrier height metal simultaneously to satisfy the demand of Schottky and source electrode-body nurse node difficult to understand, this is expensive shortcoming.
In addition, the said apparatus configuration is as Figure 1A, Figure 1B and the puncture vulnerability (breakdown vulnerability) that still is confined to the bottom corner of P+ type pocket area shown in Figure 2, shown in Fig. 1 C and Fig. 1 D, the puncture vulnerability of the bottom corner of this build alloy (P+ type pocket) is because the minor radius of the curvature of the face that connects on P+ type pocket area bottom corner next door; And, the dopant profiles curve chart shown in Fig. 1 D, it has compared among Fig. 1 C along the curve chart of junction barrier schottky P+ type pocket area and the mos field effect transistor P type body regions of tangent line A-A ' and B-B '.
Therewith the identical inventor of patent application case another the 11/413rd, No. 249 a kind of improvement semiconductor power devices of patent disclosure, the 11/413rd, disclosed semiconductor power devices system and Schottky diode are integrated in No. 249 patents, to increase the puncture voltage of device, under the situation of the usefulness that does not change whole and the mos field effect transistor device that Schottky diode is integrated, solve the puncture vulnerability of P+ type pocket area bottom corner.Semiconductor power devices more forms some Junction Barrier Controlled Schottky (JBS) rectifier in schottky area, this schottky area system improvement doping curve is to increase puncture voltage under the prerequisite that does not influence mos field effect transistor unit usefulness.In addition, Junction Barrier Controlled Schottky (JBS) rectifier system is implemented in the configuration of some long and narrow square closed cell, round sealed unit and hexagon closed cells, and Junction Barrier Controlled Schottky (JBS) rectifier in the schottky area also has maximum schottky area, and its grid running (gate runner) formation honeycomb grid that ties up to bottom periphery refers to (gate finger) and do not operate around grid bus (peripheralgate bus) around the crystal grain.The details of various configurations is specified in the 11/413rd, No. 249 patent, regard it as herein with reference to and part be used for following this patent and use.
As mentioned above, device with integration Schottky diode of multiple improved arrangement needs the schottky area of a separation, the diverse schottky area manufacture process in this and active cell zone is numerous and diverse, need customized configuration, and the schottky area of separating also needs the Schottky diode of big crystallite dimension in order to the integrating semiconductor power device.
Therefore, the present invention promptly proposes a kind of design configurations and manufacture method of semiconductor power devices, and effectively to overcome above-mentioned these problems, concrete framework and execution mode thereof will be specified in down.
Summary of the invention
Main purpose of the present invention is at the semiconductor power devices that a kind of new-type improvement is provided, integrates with Schottky diode, it forms the Schottky node in each unit, as the plane node of mos field effect transistor device, to simplify manufacturing process and to reduce the required regional space of special schottky area in the semiconductor power devices.
Another object of the present invention is at the semiconductor power devices that a kind of new-type improvement is provided, integrates with Schottky diode, it forms the Schottky node in each unit, and utilizing the P type Shannon (Shannon) of boron or boron difluoride ion to implant the leakage current of coordinating Schottky diode, the ion flow of this boron or boron difluoride ion is within 2e11～1e13 scope and implant energy between 10～80keV.
Another object of the present invention is at the semiconductor power devices that a kind of new-type improvement is provided, integrates with Schottky diode, it forms the Schottky node in each unit, wherein install usefulness significantly promote main cause be diode oppositely recapture feature (reverse recovery characteristics) and, and silicon usefulness is significantly improved.
Another object of the present invention is at the semiconductor power devices that a kind of new-type improvement is provided, integrates with Schottky diode, form the Schottky node in its each unit between the nick shaped body regions, wherein, body regions is formed at the edge of Schottky node, high dose bulk doped thing is implanted in the Schottky node zone, normal to guarantee the Schottky diode function that is formed in each active transistor unit.
In order to achieve the above object, the invention provides a kind of semiconductor power devices, it comprises the active cell zone (active cell area) with some power transistor cell, each power transistor cell has a planer schottky diode, comprise a Schottky junction barrier metal (Schottky junction barriermetal), it covers the zone of breach top, this breach is separated the body regions of adjacent two power transistor cell, the body regions that wherein is separated also comprises the some heavy body doped region (heavy body doped regions) around Schottky diode, so that the function of regulating the leakage current of Schottky diode in each power transistor cell to be provided.Each planer schottky diode also comprises a Shannon implantation zone (Shannon implant region) that is arranged in breach, and this breach is separated the body regions of adjacent two power transistor cell, to regulate the leakage current of Schottky diode.Each power transistor cell also comprises some heavy body doped regions, be arranged in the body regions that is separated and in abutting connection with the source region, this heavy body doped region is around Schottky diode, to form junction barrier schottky (junction barrier Schottky, JBS) pocket area.
The above-mentioned institute of foundation says that the present invention discloses a kind of manufacture method of semiconductor power devices, to form an active cell zone with some power transistor cell.At first, form power transistor cell in the active cell zone, it has some body regions of being separated by breach, and this breach is between two adjacent power transistors.This method also comprises step, deposit Schottky junction barrier metal is on the breach between this body regions that is being separated, with in each power transistor cell, form a planer schottky diode, make be arranged in the body regions that is separated and around the leakage current of heavy each power transistor cell Schottky diode of body doped region scalable of Schottky diode.In one embodiment, the step that forms planer schottky diode comprises that also finishing a shallow-layer Shannon implants with the formation of the indentation, there between the separated body zone of two adjacent power transistor units Shannon implantation zone, regulates the leakage current of Schottky diode.
Semiconductor power devices provided by the invention has having a few of high-breakdown-voltage, can improve the performance that high frequency power switching, H bridge circuit (H-bridge) and synchronous rectification are used, and does not influence the device layout of metal-oxide semiconductor (MOS)-Schottky integrating apparatus.
Description of drawings
Figure 1A is conventional groove mos field effect transistor power device and cutaway view of integrating the Junction Barrier Controlled schottky area in the prior art.
Figure 1B is another kind of conventional groove mos field effect transistor power device and integration groove metal oxide semiconductor potential barrier control Schottky (Trench MOSBarrier controlled Schottky, cutaway view TMBS) in the prior art.
Fig. 1 C is the cutaway view that conventional groove mos field effect transistor power device and has the integration Junction Barrier Controlled schottky area that punctures rapid wear point in the prior art on the regional bottom corner of this build alloy (P+ type pocket).
Fig. 1 D is the doping content curve chart at the tangent line position of P+ type pocket area among Figure 1A and Figure 1B and mos field effect transistor body regions, to show the puncture vulnerability.
Fig. 2 is and the cutaway view of the present invention with the Improvement type production depletion MOS in inventor's the co-applications case.
Fig. 3 A and Fig. 3 B for mos field effect transistor device among the present invention before diffusion and the side sectional view after the diffusion.
Fig. 3 C and Fig. 3 D are the alloy curve chart of mos field effect transistor device among the present invention before and after slight this build alloy diffusing step.
Fig. 3 E is the side sectional view of mos field effect transistor of the present invention, and improvement has the puncture voltage of the schottky area of metal-oxide semiconductor (MOS) land regions.
Fig. 4 A for can improve among the present invention between the puncture voltage every the cutaway view of mos field effect transistor, Fig. 4 B is the alloy curve chart of Fig. 4 A.
Fig. 5 A to Fig. 5 K is the cutaway view of the manufacturing process of the groove metal oxide semiconductor field effect transistor device of a series of description manufacturings as shown in Fig. 4 A.
Fig. 6 A is the side sectional view of junction barrier schottky (JBS) rectifier, and Fig. 6 B to Fig. 6 E is that junction barrier schottky rectifiers is the vertical view of long and narrow square closed cell, round sealed unit and the configuration of hexagon closed cell.
Fig. 7 is the vertical view of mos field effect transistor device, wherein has maximized schottky area, to refer to realize in the running of bottom periphery grid around grid bus and honeycomb grid around the non-running of crystal grain.
Fig. 8 is the vertical view of mos field effect transistor device, and wherein schottky area is formed in the huge cellular construction.
Fig. 8 A is the vertical view of mos field effect transistor device, and wherein schottky area is formed in each mos field effect transistor cellular construction.
Fig. 9 is the cutaway view in each unit that among the present invention mos field effect transistor is integrated in Schottky.
Figure 10 A to Figure 10 J is the cutaway view of the manufacturing process of a series of description manufacturings groove metal oxide semiconductor field effect transistor device as shown in Figure 9.
Embodiment
Fig. 3 A and 3B are that (picture provides the side sectional view of the rectification function of mos field effect transistor device to junction barrier schottky for junction barrier Schottky, JBS) zone.Fig. 3 A is the blank implant of this build of low dosage dopant ions, for N channel mos field effect transistor devices, and can be with every square centimeter 5 * 10 of concentration
11～5 * 10
12The boron ion be implanted in the epitaxial loayer with the energy of 40～500KeV, preferable energy is 80～300KeV, the blank implant of this build dopant ions be for the doping content that compensates and reduce the epitaxial loayer some to increase the puncture voltage of epitaxial loayer.Shown in Fig. 3 B, bulk doped thing in rising diffusion temperature 1000～1150 degree 1～3 hour then so that this build alloy be diffused into than after the more shallow degree of depth of mos field effect transistor body regions that forms.Implant this build dopant ions in order to compensate a part of epi dopant thing, and in epitaxial loayer, produce N type zone, this does not influence puncture voltage or other effectiveness parameters of mos field effect transistor, because P type implant can not exceed the P type body regions boundary line of doping content and mos field effect transistor, P type body regions has higher this build ion concentration.This build doping implant also can be after clear clean schottky area, the implantation of promptly mixing after the Schottky junction structure oxide etch; Be inclined to multiple energy in this embodiment to create broad and smooth counter-doping (counter-doped) n type zone on the surface, just stretch P type doped region with the lower temperature step as the follow up device manufacturing.Be depicted as the alloy curve chart that spreads preceding tangent line C-C ' as Fig. 3 C, Fig. 3 D is the alloy curve chart after this build alloy diffusion flow process.After diffusion, N type zone is at the alloy that has a lower and smooth variation on the vertical direction in the zone that forms Schottky junction barrier, and the low epi dopant concentration in N type zone has partly improved the puncture voltage in N type zone.Fig. 3 E is depicted as after the operation shown in Fig. 3 A and Fig. 3 B, the cutaway view that has the Schottky connection surface zone on the mos field effect transistor, the Schottky junction barrier periphery is around light dope N type dopant area, and the upper section of epitaxial loayer forms N type zone, and this regional puncture voltage increases because of lower concentration of medium.And although it is still very precipitous to cross over the alloy curve chart in P+ type schottky pocket zone, the low concentration in N type zone can help really to reduce and pass the electric field that P+ type or N type connect face, and therefore comprehensive puncture voltage of schottky area can increase.This build of light dope doping implant can not influence mos field effect transistor active cell zone, because the alloy curve chart in this platform-like zone can not be affected; The counter-doping object area that is configured in the junction barrier schottky zone has the epi dopant substrate concentration and descends, and the decline scope is from 20～80 percentages, and its effectiveness parameters of the power transistor cell in the active cell zone can not be affected.
Be depicted as the cutaway view of another preferred embodiment among the present invention as Fig. 4 A.A kind of rank, energy position of implant of light dope high-energy P type dopant ion are approximately 240～360kev, finish when the node implant sees through the implantation of node opening.Mix enough gently to overcome epi dopant for example every square centimeter 0.1～2 * 10
12The boron ion, and the P-type or the N-type that are enough to create shown in Fig. 4 A connect face, these are enough to promote the puncture voltage in junction barrier schottky zone around P+ type schottky pocket zone and the P-zone of being located at epitaxial loayer top surface next door, and meanwhile, the doping of high-energy bulk doped implant is enough light, for example this physique of 1/10 is gone into the agent amount, is not affected except the Schottky puncture voltage as threshold voltage to keep in the mos field effect transistor device.Fig. 4 B is the comparison of the doping curve chart of the mos field effect transistor device mixes along the vertical direction of this build dopant area after puncture voltage is adjusted implant curve chart and mos field effect transistor body regions, shown in Fig. 4 B, in Schottky P+ type pocket area, the gradient of P type concentration of dopant has huge variation, change into gently from precipitous, this variation falls sharply the electric field of the PN junction of crossing over the schottky pocket zone, and it significantly reduces fringe field (fringing electric field); So precipitous alloy scatters and sharp corner is excluded because of too early puncture.
Fig. 5 A to 5k is the cutaway view of the manufacturing process of the groove metal oxide semiconductor field effect transistor device of a series of description manufacturings shown in Fig. 4 A.The trench mask (not shown) that provides among Fig. 5 A, removes to generate oxide hard mask 206 then as the ground floor mask; Please refer to Fig. 5 B, it finishes the groove etchant flow to offer the some grooves 209 on the epitaxial loayer 210 that is supported on the substrate 205; Among Fig. 5 C, oxide etch is realized sacrificial oxidation (sacrificial oxidation) afterwards so that ruined surface on the trench wall is removed with smooth side wall; Then carry out gate oxidation to grow grid oxic horizon 215, oxide layer 215 grows after the doped polysilicon layer 220 in groove.
Cover the step at polysilicon etching back for realizing in Fig. 5 D, etch away with the back with polysilicon layer 220, polysilicon layer 220 does not use mask to carry out etching, till the top surface below that is etched to oxide hard mask 206; Among Fig. 5 E, hardmask 206 is etched after oxidation again, to form an oxide layer 225 at top surface; A body mask (not shown) is provided among Fig. 5 F, to follow the diffusion flow process bulk doped thing is implanted in the body regions, and body regions 230 is diffused in the epitaxial loayer 210; In Fig. 5 G, provide source mask 232 to implant source dopant, form source region 240; In 5H figure, source mask 232 is removed with source drive, make by body regions 230 around source region 240 be diffused in the epitaxial loayer 210, then, low temperature oxide (LTO)/boron-phosphorosilicate glass (BorophosphosilicateGlass, insulating barrier 245 BPSG) are formed on the top at the mos field effect transistor device; In Fig. 5 I, provide node mask (not shown) to offer some node openings 249, then with about every square centimeter 1～3 * 10
13Implant a build heavy doping thing, in schottky area, form node-increase bulk doped object area 250 and some junction barrier schottky P+ type pocket area 260; Again a low-doped high-energy P type dopant ions is implanted with the rank, energy position of about 240～360kev and passed node opening 249, to form the light dope body regions 270 shown in Fig. 4 A around P+ type pocket area 260, this light dope is enough gently to overcome epi dopant, for example every square centimeter 0.1～2 * 10
12The boron ion, and be enough to create the P-type or the N-type connects face.
Fig. 5 J provides the active mask of Schottky (activation mask) on schottky area partial insulating layer 245 is removed; Shown in Fig. 5 K; form metal level 280 at top surface; and provide the metal mask (not shown), and then form protective layer (passivation layer) to finish the manufacturing process of mos field effect transistor device so that metal level forms a source metal 280-S and a gate metal 280-G.
Junction barrier schottky can be formed in the zone or several regions of mos field effect transistor crystal grain, also can be formed in the huge cellular construction, wherein each huge unit comprises number of metal oxide semiconductor field effect transistor unit and a junction barrier schottky zone, as shown in Figure 8, each junction barrier schottky zone more can form some junction barrier schottky diodes in different layouts.Fig. 6 A is a side sectional view of the present invention, and Fig. 6 B to 6E is the vertical view of the layout of junction barrier schottky P+ type pocket area 160 among the present invention, the P+ type pocket area that intersperses on the Schottky barrier connection surface zone in the mos field effect transistor device is different shape, among Fig. 6 B to 6E, the schottky junction barrier regions territory can form long and narrow square closed cell, round sealed unit, reach the configuration of hexagon closed cell.
Fig. 7 is the vertical view of mos field effect transistor device 300, wherein has maximized schottky area, to refer to that around grid bus and honeycomb grid around the non-running of crystal grain 282-G realizes in the running of bottom periphery grid.Fig. 8 is the vertical view of mos field effect transistor device, and wherein schottky area system is formed in the huge cellular construction; Fig. 8 A is the closed cell layout of a mos field effect transistor active cell, wherein each by groove around the mos field effect transistor unit have a Schottky node zone, the P+ type doped region institute that this Schottky node zone is used as the schottky pocket zone around, because it has the circulation symmetry, therefore the mos field effect transistor unit can be defined as by groove around or in the middle of groove (in cutaway view, can understand easily).
Please refer to Fig. 9, the side sectional view of the mos field effect transistor device that it produces for the flow process shown in foundation Figure 10 of the present invention A to Figure 10 J.Mos field effect transistor device 100 can be the closed cell structure shown in Fig. 8 A, mos field effect transistor device 100 is formed on the semi-conductive substrate 105 to support epitaxial loayer 110, and the lower surface of epitaxial loayer 110 act as a drain electrode; Mos field effect transistor device 100 comprises some trench-gates 120 of being located in the grid oxic horizon 115, also comprise some body regions 125 of being located at borderline region (termination area) and be located at body regions 125 ' jaggy in the active cell zone that body regions 125 and breach body regions 125 ' are coated on the inside in the periphery and the breach body regions 125 ' of trench-gate 120 with source region 130.Insulating barrier 135 covers the top surface of node opening to form source electrode node metal level 160-S and breach metal 160-G, the part of source electrode node metal level 160-S contact source region 130 and breach body regions 125 ' forms the Schottky node, and it is at metal level and between the bottom semiconductor between the breach body regions 125 '.Mos field effect transistor device 100 also comprises the heavy doping body regions 145 as bulk doped node zone, and it is positioned between the outer rim of the outer rim of source region 130 and breach body regions 125 '; Heavy doping body regions 145 has more the effect in the heavy doping schottky pocket zone that is looped around the Schottky diode periphery, with form the Junction Barrier Controlled Schottky (Junction Barrier Controlled Schottky, JBS).In an embodiment, 130 outer rim extends to the outer rim of breach body regions 125 ' from the source region for heavy doping body regions 145; In another embodiment, heavy doping body regions 145 directly is located at by the outer rim of source region 130, in the body regions 125 ', and extends near the next door of the breach between breach body regions 125 ' outer rim and the breach body regions 125 '.Around heavy doping schottky pocket zone 145, it can improve the puncture voltage in the junction barrier schottky zone at this build light dope of breach body regions 125 ' outer rim; Heavy doping body regions 145 is to extend to the degree of depth darker than the source region, makes device firmer to provide resistance to wear function (anti-punch) through its function.Schottky node zone 150 more can comprise a barrier height regulating course (barrier height adjustment layer), it is formed in the open area between the breach body regions 125 ' with Shannon implant (Shannon implant), in order to regulate the leakage current of Schottky diode.The trench-gate 120 that the borderline region of gate metal 160-G contact trench grid 120, wherein all trench-gates include in the source unit zone all sees through the inner mutually connection of groove opening in the Semiconductor substrate that is full of the polysilicon gate material; Mos field effect transistor device 100 comprises that also the part that a protective layer 170 exposes with the top surface at source metal 160-S covers breach metal (gap metal) and preparation surface connection.
Shown in Figure 10 A to Figure 10 J, be the cutaway view of the manufacturing process of a series of description manufacturings groove metal oxide semiconductor field effect transistor device as shown in the figure 9.In 10A figure, provide the trench mask (not shown) to offer some grooves according to the flow process that gate oxidation forms, to form grid oxic horizon 315, and in groove, fill polysilicon, to form some trench-gates 320 in the epitaxial loayer 310 that is supported in Semiconductor substrate 305; Provide a photoresist layer 321 to implant, form body regions 325 around trench-gate 320 to finish the bulk doped thing as the body mask; The configuration of body mask only directly is implanted to the trench-gate 320 of a breach institute adjacency of the mid portion of 320 of trench-gates particularly when arriving between the grid 320 the borderline region next door continuously when body regions 325 implanted extensions in the body regions 325 ' in the active cell zone.In Figure 10 B, body mask 321 is removed and finishes bulk diffusion with body regions 325 and 325 ' diffusion, in the active cell zone, still have breach between the body regions 325 '.Optional build implant can the implanted and flow process of diffusion shown in Fig. 3 A to Fig. 3 B, just and do not need mask can create doping curve chart shown in Fig. 3 D before body regions forms.
Provide a source mask 326 to carry out the source electrode implant among Figure 10 C to form by body regions 325 ' around the source region 330 that surrounds, then, remove source mask 326 and provide ascending temperature (anelevated temperature) with the activation source region 330; Be that (Borophosphosilicate Glass, BPSG) flow process form covered dielectric layer 335 with the top surface at device to the boron phosphorus doped silex glass shown in Figure 10 D; In Figure 10 E, provide a node mask (not shown) to offer the node opening of particular arrangement, node opening 340-G is arranged above the trench-gate 320 in borderline region, and form the gate metal node at this place, above the source/body zone, then be formed with source/body node opening 340-SB; Provide a heavy doping body node implant between the outer rim of source region 330 and body regions 325 ', to form node doped region 345; This source/body node opening 340-SB more has a kind of configuration, and node implant doped region 345 does not wherein extend to the outer rim of body regions 325 '.Some implants form a degree of depth heavy doping body implant and do not have the expansion of too much side with different energy stratum.In one embodiment, the heavy doping body is implanted system and is carried out first implantation with the boron difluoride of the 40～80kev of energy stratum, every square centimeter of 1～3E15 earlier, then carries out second with the boron ion of the 40～80kev of energy stratum, every square centimeter of 1～3E15 and implants; In another embodiment, only with the 40～120kev of energy stratum, every square centimeter of single implantation boron difluoride of 1～5E15.In Figure 10 F, node mask (not shown) is removed, and utilize node implant activation flow process according to implanting state and activation temperature in the temperature of 800～1100 degree through 30 seconds～30 minutes.The preferred approach of node being implanted activation is that (rapid thermal process is RTP) to minimize side diffusion for the use rapid thermal treatment.
In Figure 10 G, provide a Schottky mask 342 to carry out oxide etch, insulating barrier 335 is removed from the top surface between the breach of body regions 325 ', follow shallow Shannon doping implant to have 2e11～1e13 scope, implanting intensity is the boron ion or the realization of boron difluoride ion of the ion flow of 10～80keV, shallow ion is implanted epitaxial loayer 310 tops that are treated between body regions 325 ' and is formed a Shannon implantation zone 350, and it acts on as a schottky barrier height layer in each active mos field effect transistor unit.Removing Schottky mask 342 also in Figure 10 H, doping metals provides the metal mask (not shown) to form metal level in gate metal 360-G, and source/body metal 360-S directly contacts with source region 330, body regions 325 ' and node heavily doped region 345, and the next door then is that source electrode and shallow Shannon are implanted zone 350.In Figure 10 I, on the surface of whole device, establish a protective layer 370, and in Figure 10 J, provide a protective layer (not shown) to remove partial protection layer 370, expose source metal 360-S.
In sum, the present invention discloses a kind of semiconductor power devices, this semiconductor power devices comprises an active cell zone with some power transistor cell, each power transistor cell has a Schottky diode, this Schottky diode comprises a Schottky junction barrier metal (Schottkyjunction barrier metal), its Shannon that is arranged in breach is implanted on the zone, described breach is separated the body regions of adjacent two power transistor cell, to regulate the leakage current of Schottky diode.In another embodiment, semiconductor power devices also comprises some heavy body doped regions, it is arranged in the body regions that is separated and in abutting connection with the source region, this heavy body doped region is around Schottky diode, to form junction barrier schottky (junction barrier Schottky, JBS) pocket area.Among another embodiment, each heavy body doped region is outer also around the body lightly doped region as a body regions part that is separated, to improve the puncture (breakdown) of junction barrier schottky (JBS) pocket area, in another embodiment, the body regions that is separated also comprises a heavy doping body regions, extend its bottom along body regions, wears function (anti-punch) so that the resistance of passing semiconductor power devices to be provided, and improves the device steadiness.Among another embodiment, each power transistor cell also comprises some heavy body doped regions, it is arranged in the body regions that is separated and in abutting connection with the source region, this heavy body doped region extends from the source region, and extend to the outer rim of described body regions, to form junction barrier schottky (junction barrier Schottky, JBS) zone around Schottky diode.Among another embodiment, each power transistor cell also comprises some heavy body doped regions, be arranged in the body regions that is separated and in abutting connection with the source region, this heavy body doped region extends to close body regions outer rim and still is arranged in the position of this body regions, to form junction barrier schottky (junction barrier Schottky, JBS) zone around Schottky diode.Among another embodiment, Shannon is implanted and is comprised a boron Shannon implantation zone in the zone.
Above-described embodiment is preferred embodiment of the present invention only, is not to be used for limiting scope of the invention process.So all equalizations of doing according to described feature of the present patent application scope and spirit change or modify, and all should be included in the claim of the present invention.
Claims (25)
1. a semiconductor power devices includes the source unit zone, and the active cell zone comprises some power transistor cell, it is characterized in that:
Each described power transistor cell has a Schottky diode, and this Schottky diode comprises the Schottky junction barrier metal that is positioned on the Shannon implantation zone, to regulate the leakage current of described Schottky diode; This Shannon is implanted the body regions that is separated that the zone is positioned at adjacent two power transistor cell.
2. semiconductor power devices as claimed in claim 1 is characterized in that: described power transistor cell also comprises:
Some heavy body doped regions, it is arranged in the described body regions that is separated and in abutting connection with the source region, this heavy body doped region forms the junction barrier schottky pocket area around described Schottky diode.
3. semiconductor power devices as claimed in claim 2 is characterized in that:
Each described heavy body doped region is outer also around a light body doped region as the described body regions some that is separated, to improve the puncture of this junction barrier schottky pocket area.
4. semiconductor power devices as claimed in claim 3 is characterized in that:
The described body regions that is separated also comprises a heavy doping body regions, and extend its bottom along this body regions, wears function so that the resistance of passing this semiconductor power devices to be provided, and improves the device steadiness.
5. semiconductor power devices as claimed in claim 1 is characterized in that: each power transistor cell also comprises:
Some heavy body doped regions, it is arranged in the described body regions that is separated and in abutting connection with the source region, this heavy body doped region extends from the source region, and extends to the outer rim of described body regions, with around this Schottky diode and form a junction barrier schottky zone.
6. semiconductor power devices as claimed in claim 1 is characterized in that: each this power transistor cell also comprises:
Some heavy body doped regions, it is arranged in the described body regions that is separated and in abutting connection with the source region, this heavy body doped region extends near described body regions edge and is arranged in the position of this body regions from the source region, with around this Schottky diode and form a junction barrier schottky zone.
7. semiconductor power devices as claimed in claim 1 is characterized in that:
Described Shannon is implanted and is comprised a boron Shannon implantation zone in the zone.
8. semiconductor power devices as claimed in claim 1 is characterized in that:
Also comprise the epitaxial loayer that is covered on the substrate, this epitaxial loayer comprises a part that reduces the epi dopant thing that is positioned at its top, to form Schottky junction barrier.
9. a semiconductor power devices comprises an active cell zone with some power transistor cell, it is characterized in that:
Each power transistor cell comprises a planer schottky diode, and this planer schottky diode comprises a Schottky junction barrier metal, and it covers the zone of breach top, and this breach is separated the body regions of adjacent two power transistor cell;
The body regions that wherein is separated also comprises the some heavy body doped region around this Schottky diode, so that the function of regulating Schottky diode leakage current in each power transistor cell to be provided.
10. semiconductor power devices as claimed in claim 9 is characterized in that:
Each described planer schottky diode also comprises the Shannon implantation zone that is arranged in breach, and this breach is separated the body regions of adjacent two power transistor cell, to regulate the leakage current of this Schottky diode.
11. semiconductor power devices as claimed in claim 9 is characterized in that: each this power transistor cell also comprises:
Some heavy body doped regions, it is arranged in the described body regions that is separated and in abutting connection with the source region, this heavy body doped region is around described Schottky diode, to form the junction barrier schottky pocket area.
12. semiconductor power devices as claimed in claim 11 is characterized in that:
The light body doped region of the outer body regions some that also is separated around a conduct of each described heavy body doped region is to improve the puncture of this junction barrier schottky pocket area.
13. semiconductor power devices as claimed in claim 12 is characterized in that:
The described body regions that is separated also comprises a heavy doping body regions, is positioned at the next door, bottom of this body regions, wears function so that the resistance of passing this semiconductor power devices to be provided, and improves the device steadiness.
14. semiconductor power devices as claimed in claim 9 is characterized in that, each this power transistor cell also comprises:
Some heavy body doped regions, be arranged in the described body regions that is separated and in abutting connection with the source region, this heavy body doped region extends from the source region, and extends to the outer rim of described body regions, to form the junction barrier schottky zone around described Schottky diode.
15. semiconductor power devices as claimed in claim 9 is characterized in that, each this power transistor cell also comprises:
Some heavy body doped regions, be arranged in the described body regions that is separated and in abutting connection with the source region, this heavy body doped region extends from the source region, and extend near described body regions edge and be arranged in the position of this body regions, to form the junction barrier schottky zone around this Schottky diode.
16. semiconductor power devices as claimed in claim 10 is characterized in that:
Described Shannon is implanted the zone and is comprised a boron Shannon implantation zone.
17. semiconductor power devices as claimed in claim 10 is characterized in that:
Also comprise the epitaxial loayer that is covered on the substrate, the vertically lower and smooth variation of doping on the zone in the described epitaxial loayer is to form Schottky junction barrier.
18. semiconductor power devices as claimed in claim 9 is characterized in that:
Described semiconductor power devices comprises a metal oxide field-effect transistor power device.
19. a semiconductor power devices is characterized in that, comprising:
Epitaxial loayer is covered on the substrate, the vertically lower and smooth variation of doping on the zone in this epitaxial loayer; And active cell zone with some power transistor cell, each described power transistor cell has a planer schottky diode, comprise a Schottky junction barrier metal, it covers the zone of breach top, and this breach is separated the body regions of adjacent two power transistor cell;
The described body regions that is separated also provides the function of regulating the leakage current of Schottky diode in each power transistor cell.
20. semiconductor power devices as claimed in claim 19 is characterized in that:
Each described planer schottky diode also comprises the Shannon implantation zone that is arranged in breach, and this breach is separated the body regions of adjacent two power transistor cell, to regulate the leakage current of this Schottky diode.
21. semiconductor power devices as claimed in claim 19 is characterized in that: each described power transistor cell also comprises:
Some heavy body doped regions are arranged in the described body regions that is separated and in abutting connection with the source region, this heavy body doped region is around described Schottky diode, to form the junction barrier schottky pocket area.
22. a semiconductor power devices comprises an active cell zone with some power transistor cell, it is characterized in that:
Each described power transistor cell has a planer schottky diode, and it comprises a Schottky junction barrier metal, its in body regions, cover by heavy body doped region around the zone; A source region, its doping is formed in the body regions, and around described heavy body doped region; A groove is around described source region and body regions.
23. the manufacture method of a semiconductor power devices, the active cell zone so that formation has some power transistor cell is characterized in that:
Form some power transistor cell in described active cell zone, it has some body regions of being separated by breach, and this breach is between two adjacent power transistors; And deposit Schottky junction barrier metal is on the breach between this body regions that is being separated, with in each power transistor cell, form a planer schottky diode, make be arranged in the body regions that is separated and around the leakage current of heavy each power transistor cell Schottky diode of body doped region scalable of Schottky diode.
24. the manufacture method of semiconductor power devices as claimed in claim 23 is characterized in that:
The step of described formation planer schottky diode also comprises a step, it is finished the shallow-layer Shannon and implants, form Shannon with the indentation, there between the body regions that is separated of two adjacent power transistor units and implant the zone, regulate the leakage current of this Schottky diode.
25. semiconductor power devices as claimed in claim 23 is characterized in that:
The step of described formation planer schottky diode also comprises a step, and it is finished counter-doping and implants, and with in the top area of epitaxial loayer, vertically forms the doped region of lower and smooth change, thereby forms Schottky junction barrier.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
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| US12/217,092 US7952139B2 (en) | 2005-02-11 | 2008-06-30 | Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout |
| US12/217,092 | 2008-06-30 |
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| CN201210259939.0A Division CN102751317B (en) | 2008-06-30 | 2009-06-26 | Enhancing schottky breakdown voltage (BV) without affecting an integrated MOSFET-schottky device layout |
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| CN201210259939.0A Active CN102751317B (en) | 2008-06-30 | 2009-06-26 | Enhancing schottky breakdown voltage (BV) without affecting an integrated MOSFET-schottky device layout |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102456622A (en) * | 2010-10-29 | 2012-05-16 | 上海宏力半导体制造有限公司 | Preparation method of trench-type MOS (metal oxide semiconductor) barrier schottky groove |
| CN102683409A (en) * | 2011-03-10 | 2012-09-19 | 凹凸电子（武汉）有限公司 | Methods for fabricating transistors including circular trenches |
| CN102856363A (en) * | 2011-06-29 | 2013-01-02 | 大中集成电路股份有限公司 | Trench junction barrier schottky structure with enhanced contact area integrated with a mosfet |
| CN102945806A (en) * | 2012-09-27 | 2013-02-27 | 上海集成电路研发中心有限公司 | Manufacturing method of MOS (metal oxide semiconductor) device of integrated Schottky diode |
| CN104078517A (en) * | 2014-07-22 | 2014-10-01 | 苏州硅能半导体科技股份有限公司 | Groove type schottky semiconductor device |
| CN104617141A (en) * | 2013-11-04 | 2015-05-13 | 美格纳半导体有限公司 | Semiconductor device and manufacturing method thereof |
| CN115954358A (en) * | 2023-03-14 | 2023-04-11 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105304708B (en) * | 2014-07-31 | 2019-04-26 | 瀚薪科技股份有限公司 | Silicon carbide semiconductor device |
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| US4063964A (en) * | 1976-12-27 | 1977-12-20 | International Business Machines Corporation | Method for forming a self-aligned schottky barrier device guardring |
| GB2151844A (en) * | 1983-12-20 | 1985-07-24 | Philips Electronic Associated | Semiconductor devices |
| TW554528B (en) * | 2002-02-21 | 2003-09-21 | Delta Electronics Inc | Low forward voltage drop Schottky barrier diode and the manufacturing method thereof |
| US6838722B2 (en) * | 2002-03-22 | 2005-01-04 | Siliconix Incorporated | Structures of and methods of fabricating trench-gated MIS devices |
| US7436022B2 (en) * | 2005-02-11 | 2008-10-14 | Alpha & Omega Semiconductors, Ltd. | Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout |
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- 2009-03-17 TW TW098108576A patent/TWI384625B/en active
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102456622A (en) * | 2010-10-29 | 2012-05-16 | 上海宏力半导体制造有限公司 | Preparation method of trench-type MOS (metal oxide semiconductor) barrier schottky groove |
| CN102456622B (en) * | 2010-10-29 | 2013-10-09 | 上海宏力半导体制造有限公司 | Preparation method of trench-type MOS (metal oxide semiconductor) barrier schottky groove |
| CN102683409A (en) * | 2011-03-10 | 2012-09-19 | 凹凸电子（武汉）有限公司 | Methods for fabricating transistors including circular trenches |
| CN102856363A (en) * | 2011-06-29 | 2013-01-02 | 大中集成电路股份有限公司 | Trench junction barrier schottky structure with enhanced contact area integrated with a mosfet |
| CN102945806A (en) * | 2012-09-27 | 2013-02-27 | 上海集成电路研发中心有限公司 | Manufacturing method of MOS (metal oxide semiconductor) device of integrated Schottky diode |
| CN104617141A (en) * | 2013-11-04 | 2015-05-13 | 美格纳半导体有限公司 | Semiconductor device and manufacturing method thereof |
| US10269988B2 (en) | 2013-11-04 | 2019-04-23 | Magnachip Semiconductor, Ltd. | Semiconductor device and manufacturing method thereof |
| CN104617141B (en) * | 2013-11-04 | 2020-11-10 | 美格纳半导体有限公司 | Semiconductor device and method for manufacturing the same |
| US11056595B2 (en) | 2013-11-04 | 2021-07-06 | Magnachip Semiconductor, Ltd. | Semiconductor device and manufacturing method thereof |
| CN104078517A (en) * | 2014-07-22 | 2014-10-01 | 苏州硅能半导体科技股份有限公司 | Groove type schottky semiconductor device |
| CN115954358A (en) * | 2023-03-14 | 2023-04-11 | 合肥晶合集成电路股份有限公司 | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102751317A (en) | 2012-10-24 |
| CN102751317B (en) | 2015-02-11 |
| CN101621062B (en) | 2012-09-19 |
| TWI384625B (en) | 2013-02-01 |
| TW201001705A (en) | 2010-01-01 |
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