CN101615914A - The implementation method of layering minimum and LDPC decoding code check node processing - Google Patents

Abstract

The invention discloses the implementation method that the minimum and LDPC of a kind of layering deciphers code check node processing: a certain check-node, with the Q of all variable node correspondences of being attached thereto _v ^L-1And R _Cv ^L-1Subtract each other respectively, adopt the bubbling method to subtract each other and search absolute value minimum value and time minimum value the result, according to the Q of lookup result to back one check-node from all _v ^lAnd R _Cv ^lUpgrade, till predefined sub-iterations or iteration convergence; During each straton iterative processing, same hardware serial shared processing is adopted in searching of absolute value minimum value and time minimum value; Useful technique effect of the present invention is: reduce the complexity of the decoding iterative processing of LDPC check matrix greatly, reduce the hardware spending of decoding iterative processing greatly.

Description

The implementation method of layering minimum and LDPC decoding code check node processing

Technical field

The present invention relates to a kind of LDPC decoding treatment technology, relate in particular to the implementation method of a kind of layering minimum and LDPC decoding code check node processing.

Background technology

The LDPC sign indicating number has easy realization and the low characteristics of complexity, have high coding gain and characteristic near shannon limit is provided, along with the development LDPC of VLSI technology coding is adopted to business communications system in a large number, its typical case's application mainly contains: satellite DVB-S2, WLAN 802.11n, WiMAX 802.16e, mobile broadband wireless 802.20, IPTV, advanced magnetic media storage, long-distance optical communication, wireless personal local area network (WPAN) 802.12.

LDPC belongs to linear block codes, can describe by containing seldom the sparse check matrix of the nonzero element of number.A certain sparse check matrix H is made up of the capable N row of M, and the number N of row is corresponding through the N bit codewords that obtains after encoding with information bit.Code word is made up of the individual information bit of K=(N-M) and M check bit.

(Tanner figure) can represent the LDPC sign indicating number in the mode of scheming by bipartite graph, as shown in Figure 1.Be called the capable corresponding check bit of variable node or bit node v and check matrix with the code word bits of check matrix column correspondence and be called check-node c, the corresponding bipartite graph with variable node and check-node of each sparse check matrix H is referring to Fig. 2.

Sparse check matrix H shown in Figure 1, the Tanner figure of LDPC sign indicating number correspondence have 6 variable node (v shown in Fig. 1 ₁, v ₂, v ₃, v ₄, v ₅, v ₆) and 3 check-node (c shown in Fig. 1 ₁, c ₂, c ₃), the length N of code word=6, check bit is counted M=3, information bit K=(N-M)=3, code check R=K/N=1/2.Element in the check matrix is h _IjBe to show that i check-node and j variable node were associated at 1 o'clock.The check digit of the M bit in the line number among the sparse check matrix H and the code word is corresponding, in corresponding Tanner figure (Fig. 2), M=N-K check-node c arranged, a bit in the corresponding check equations of check-node, N variable node in each variable node correspondence codeword information.

With the N bit LDPC coding codeword that vectorial X represents, through white Gaussian noise channel Channel Transmission, the codeword vector Y behind the receiving demodulation can be expressed as after the modulation:

Y＝X+N

Wherein N representation vector X is through the white Gaussian noise of Channel Transmission introducing.

After code word Y is received demodulation, at first calculate the log-likelihood ratio (LLR) that receives code word.Log-likelihood ratio is the prior estimate that receives code word bits, and as the soft-decision input of LDPC decoding, the hard decision input helps improving the LDPC decoding performance relatively.

At this sparse check matrix H, the processing mode of prior art makes that the complexity of computing is very high, because the complexity of computing needs a large amount of comparators, and the number of comparators that needs with the variable node number square relation increase progressively, make hardware spending huge.

Summary of the invention

The present invention proposes the implementation method of a kind of layering minimum and LDPC decoding code check node processing, the check matrix of LDPC is divided into multilayer by the check-node number, the decoding iteration of every layer or each check-node is called sub-iteration, and the sub-iteration of whenever finishing once all layers or all check-nodes is then thought and finished the check matrix iteration one time; The output information of last straton iteration is as the input information of back one straton iteration; The output information of a preceding check matrix iteration is as the input information of a back check matrix iteration; Sub-iterations continuous counter between the continuous check matrix iteration; Its innovative point is:

A certain check-node is with the Q of all variable node correspondences of being attached thereto _v ^L-1And R _Cv ^L-1Subtract each other respectively, adopt the bubbling method to subtract each other and search absolute value minimum value and time minimum value the result, according to the Q of lookup result to back one check-node from all _v ^lAnd R _Cv ^lUpgrade, till predefined sub-iterations or iteration convergence;

During each straton iterative processing, same hardware serial shared processing is adopted in searching of absolute value minimum value and time minimum value;

Wherein, subscript l and l-1 represent l and l-1 second son iteration; Q _v ^L-1Represent that each variable node is to the input information of check-node after the iterative processing of l-1 second son; R _Cv ^L-1Represent that check-node is to the input information of each variable node after the iterative processing of l-1 second son; Q _v ^lAnd R _Cv ^lRepresent that the iterative processing of l second son needs updated information, Q _v ^lRepresent that each variable node is to the input information of check-node after the iterative processing of l second son; R _Cv ^lRepresent that check-node is to the input information of each variable node after the iterative processing of l second son;

This method step is:

If a certain check matrix has l check-node, each check-node has d _cIndividual variable node is attached thereto,

1) for the first time during the check matrix iteration, decoder calculates its log-likelihood ratio λ according to the code word Y that receives, with λ with the information Q of each variable node to first check-node _V1 ⁰, Q _V2 ⁰, Q _V3 ⁰... Q _Vdc ⁰Initialization, first check-node is to the information R of each variable node _Cv1 ⁰, R _Cv2 ⁰, R _Cv3 ⁰... R _Cvdc ⁰All be initialized as 0;

With Q _V1 ⁰, Q _V2 ⁰, Q _V3 ⁰... Q _Vdc ⁰And R _Cv1 ⁰, R _Cv2 ⁰, R _Cv3 ⁰... R _Cvdc ⁰Subtract each other respectively, adopt the bubbling method to subtract each other and search absolute value minimum value and time minimum value the result, according to the Q of lookup result to second check-node from all _V1 ¹, Q _V2 ¹, Q _V3 ¹... Q _Vdc ¹And R _Cv1 ¹, R _Cv2 ¹, R _Cv3 ¹... R _Cvdc ¹Upgrade;

2) with Q _V1 ¹, Q _V2 ¹, Q _V3 ¹... Q _Vdc ¹And R _Cv1 ¹, R _Cv2 ¹, R _Cv3 ¹... R _Cvdc ¹Subtract each other respectively, adopt the bubbling method to subtract each other and search absolute value minimum value and time minimum value the result, according to the Q of lookup result to the 3rd check-node from all _V1 ², Q _V2 ², Q _V3 ²... Q _Vdc ²And R _Cv1 ², R _Cv2 ², R _Cv3 ²... R _Cvdc ²Upgrade;

3) repeating step 2), in the sub-iterations of the check matrix iteration first time,, then stop iteration if reach predefined iterations or iteration convergence;

4) if for the first time the check matrix iteration is finished, promptly l check-node all upgrades and finishes, and also do not reach predefined iterations or iteration and do not restrain, then the Q of last second son iteration renewal of check matrix iteration for the first time _V1 ^L-1, Q _V2 ^L-1, Q _V3 ^L-1... Q _Vdc ^L-1And R _Cv1 ^L-1, R _Cv2 ^L-1, R _Cv3 ^L-1... R _Cvdc ^L-1, as the initial value of the first second son iteration of the check matrix iteration second time,

[1] with Q _V1 ^L-1, Q _V2 ^L-1, Q _V3 ^L-1... Q _Vdc ^L-1And R _Cv1 ^L-1, R _Cv2 ^L-1, R _Cv3 ^L-1... R _Cvdc ^L-1Subtract each other respectively, try to achieve d _cThe symbol sign (Δ) of individual Δ value and each Δ,

Wherein, Δ={ Δ ₁, Δ ₂, Δ ₃... Δ _Dc, Δ ₁=Q _V1 ^L-1-R _Cv1 ^L-1..., Δ d _c=Q _Vdc ^L-1-R _Cvdc ^L-1

Sign (Δ)=1 o'clock for negative for just in sign (Δ)=0 o'clock;

[2] adopt the bubbling method, from d _cFind out in the individual Δ | Δ | minimum value min 0 and time minimum value min 1, record min 0 pairing variable node sequence number num (min 0);

Wherein, | Δ | be the set of the absolute value of each Δ value;

[3] establish min 0 pairing num (the min 0)=m that finds in the step [2], and m ∈ [1, d _c], if need the Q of renewal _v ^lAnd R _Cv ^lPairing variable node sequence number is identical with the pairing variable node sequence number of min0, then R _Cvm ^lAbsolute value get min 1, otherwise get min 0; R _Cvm ^lSymbol be: the sign (Δ that removes present node sequence number correspondence _m) product of outer remaining sign (Δ); Q _Vm ^lGet Q _Vm ^l=Δ _m+ R _Cvm ^l

5) repeating step 4), in the sub-iterations of l check-node, if reach predefined iterations or iteration convergence, then stop iteration, otherwise, with the Q that upgrades of last second son iteration of the check matrix iteration second time _V1 ^2l-1, Q _V2 ^2l-1, Q _V3 ^2l-1... Q _Vdc ^2l-1And R _Cv1 ^2l-1, R _Cv2 ^2l-1, R _Cv3 ^2l-1... R _Cvdc ^2l-1,, proceed iterative processing, till reaching predefined iterations or iteration convergence as the initial value of the first second son iteration of check matrix iteration for the third time.

Wherein, variable node represents with the 8bit complement of two's two's complement that to the input information of check-node check-node is represented with the 6bit complement of two's two's complement to the input information of variable node.

In order to guarantee complement of two's two's complement data symmetry, after each Δ calculates, the result of calculation of Δ is all carried out saturation arithmetic.

Useful technique effect of the present invention is: reduce the complexity of the decoding iterative processing of LDPC check matrix greatly, reduce the hardware spending of decoding iterative processing greatly.

Description of drawings

Fig. 1, sparse check matrix;

Fig. 2, the bipartite graph corresponding with Fig. 1;

The input signal process flow block diagram of Fig. 3, employing the inventive method;

The output signal process flow block diagram of Fig. 4, employing the inventive method;

Fig. 5, saturated processing links;

Fig. 6, serial computing link;

Embodiment

At the deficiencies in the prior art of describing in the background technology, the inventor has proposed the implementation method of a kind of layering minimum and LDPC decoding code check node processing through concentrating on studies, the difference of this method and prior art maximum is: the bubbling two-value is searched algorithm introduce in the check matrix decoding iterative processing of LDPC, the complexity that makes the decoding iterative processing is from O (d _c ²) be reduced to O (d _c), and the bubbling two-value is searched algorithm adopt same hardware serial shared processing, reduced hardware spending greatly.

The concrete processing procedure of the inventive method is:

If a certain check matrix has l check-node (for example, c ₁, c ₂..., c _l), each check-node has d _cIndividual variable node is attached thereto,

1) for the first time during the check matrix iteration, decoder calculates its log-likelihood ratio λ according to the code word Y that receives, with λ with the information Q of each variable node to first check-node _V1 ⁰, Q _V2 ⁰, Q _V3 ⁰... Q _Vdc ⁰Initialization, first check-node is to the information R of each variable node _Cv1 ⁰, R _Cv2 ⁰, R _Cv3 ⁰... R _Cvdc ⁰All be initialized as 0;

With Q _V1 ⁰, Q _V2 ⁰, Q _V3 ⁰... Q _Vdc ⁰And R _Cv1 ⁰, R _Cv2 ⁰, R _Cv3 ⁰... R _Cvdc ⁰Subtract each other respectively, adopt the bubbling method to subtract each other and search absolute value minimum value and time minimum value the result, according to the Q of lookup result to second check-node from all _V1 ¹, Q _V2 ¹, Q _V3 ¹... Q _Vdc ¹And R _Cv1 ¹, R _Cv2 ¹, R _Cv3 ¹... R _Cvdc ¹Upgrade;

2) with Q _V1 ¹, Q _V2 ¹, Q _V3 ¹... Q _Vdc ¹And R _Cv1 ¹, R _Cv2 ¹, R _Cv3 ¹... R _Cvdc ¹Subtract each other respectively, adopt the bubbling method to subtract each other and search absolute value minimum value and time minimum value the result, according to the Q of lookup result to the 3rd check-node from all _V1 ², Q _V2 ², Q _V3 ²... Q _Vdc ²And R _Cv1 ², R _Cv2 ², R _Cv3 ²... R _Cvdc ²Upgrade;

3) repeating step 2), in the sub-iterations of the check matrix iteration first time,, then stop iteration if reach predefined iterations or iteration convergence;

4) if for the first time the check matrix iteration is finished, promptly l check-node all upgrades and finishes, and also do not reach predefined iterations or iteration and do not restrain, then the Q of last second son iteration renewal of check matrix iteration for the first time _V1 ^L-1, Q _V2 ^L-1, Q _V3 ^L-1... Q _Vdc ^L-1And R _Cv1 ^L-1, R _Cv2 ^L-1, R _Cv3 ^L-1... R _Cvdc ^L-1, as the initial value of the first second son iteration of the check matrix iteration second time,

[1] with Q _V1 ^L-1, Q _V2 ^L-1, Q _V3 ^L-1... Q _Vdc ^L-1And R _Cv1 ^L-1, R _Cv2 ^L-1, R _Cv3 ^L-1... R _Cvdc ^L-1Subtract each other respectively, try to achieve d _cThe symbol sign (Δ) of individual Δ value and each Δ,

Wherein, Δ={ Δ ₁, Δ ₂, Δ ₃... Δ d _c, Δ ₁=Q _V1 ^L-1-R _Cv1 ^L-1..., Δ d _c=Q _Vdc ^L-1-R _Cvdc ^L-1

Sign (Δ)=1 o'clock for negative for just in sign (Δ)=0 o'clock;

[2] adopt the bubbling method, from d _cFind out in the individual Δ | Δ | minimum value min 0 and time minimum value min 1, record min 0 pairing variable node sequence number num (min 0);

Wherein, | Δ | be the set of the absolute value of each Δ value;

[3] establish min 0 pairing num (the min 0)=m that finds in the step [2], and m ∈ [1, d _c], if need the Q of renewal _v ^lAnd R _Cv ^lPairing variable node sequence number is identical with min 0 pairing variable node sequence number, then R _Cvm ^lAbsolute value get min 1, otherwise get min 0; R _Cvm ^lSymbol be: the sign (Δ that removes present node sequence number correspondence _m) product of outer remaining sign (Δ); Q _Vm ^lGet Q _Vm ^l=Δ _m+ R _Cvm ^l

5) repeating step 4), in the sub-iterations of l check-node, if reach predefined iterations or iteration convergence, then stop iteration, otherwise, with the Q that upgrades of last second son iteration of the check matrix iteration second time _V1 ^2l-1, Q _V2 ^2l-1, Q _V3 ^2l-1... Q _Vdc ^2l-1And R _Cv1 ^2l-1, R _Cv ^2l-1, R _Cv3 ^2l-1... R _Cvdc ^2l-1,, proceed iterative processing, till reaching predefined iterations or iteration convergence as the initial value of the first second son iteration of check matrix iteration for the third time.

Wherein, variable node represents with the 8bit complement of two's two's complement that to the input information of check-node check-node is represented with the 6bit complement of two's two's complement to the input information of variable node.

Set forth the application of the inventive method under two kinds of signal processing situations below respectively.

1, input signal is handled

Input signal is handled and is comprised following link: 1) calculate Δ successively _m=Q _Vm ^L-1R _Cvm ^L-1, (m ∈ [1, d _c]) and carry out saturated processing; 2) with Δ _mWrite RAM; 3) serial computing sign (∏ Δ _m);

4) basis | Δ _m| carry out min 0 and min 1 searches, write down min 0 corresponding sequence number simultaneously; Introduce the processing delay of a clock cycle in the step 1), 2), 3) and 4) parallel processing also introduces the processing delay of a clock cycle, the processing delay of two clock cycle is introduced in the input signal processing altogether.The entire process process as shown in Figure 3.

Degree d with check-node _cIt is corresponding that (" degree " expression has d _cIndividual variable node links to each other with check-node), each link that input signal is handled all needs to carry out d _cInferior.

The position of saturated processing in the step 1) (being saturation arithmetic) link in handling process as shown in Figure 5.Q _Vm ^L-1With 8 bit-binary complement representations, R _Cvm ^L-1With 6 bit-binary complement representations, at first carry out the position expansion, i.e. Q _Vm ^L-1And R _Cvm ^L-1All expanding to 9 bit-binary complement codes subtracts each other then.The reason of carrying out saturated processing is in order to guarantee complement of two's two's complement data symmetry, i.e. the data span of saturated processing is-127 to 127.Q is at first judged in saturated processing _Vm ^L-1-R _Cvm ^L-1Absolute value whether greater than 127, if less than 127 Δs so _m=Q _Vm ^L-1-R _Cvm ^L-1Otherwise according to Q _Vm ^L-1-R _Cvm ^L-1Symbol produce saturated result, if difference is a positive number Δ so _m=127, otherwise Δ _m=-127.

Step 2) in, the Δ that produces successively _mWrite RAM.After finishing, input operation reads Δ from RAM _m, carry out Q _V1 ¹, Q _V2 ¹, Q _V3 ¹... Q _Vdc ¹And R _Cv1 ¹, R _Cv2 ¹, R _Cv3 ¹... R _Cvdc ¹Renewal.

Step 3) serial computing sign (∏ Δ _m), as shown in Figure 6, calculate sign (∏ Δ _m) realize sign (∏ Δ by XOR (mould 2) operation _m) put initial value 0, then to sign (Δ _m) and sign (∏ Δ _m) carry out XOR (mould 2) operation and produce new sign (∏ Δ _m).

Step 4) is carried out the absolute value minimum value by the bubbling algorithm and is searched with time minimum value as shown in Figure 3, and this is the key of the present invention to code check node processing, utilizes the bubbling algorithm can reduce the complexity of hardware greatly, and processing delay also is guaranteed simultaneously.Before the data inputs at first to min 0 and min 1 initialize 127, num (min 0) initialize d _cEvery generation is new | Δ _m| just carry out a bubbling and calculate, the bubbling process is as follows:

If | Δ _m|＜min 0|, | Δ _m| assignment is given min 0, and current min 0 assignment is given min 1, when the node number m of pre-treatment assignment is given num (min 0); If min 0＜| Δ _m|＜min 1, | Δ _m| assignment is given min 1.

2, output signal is handled

Output signal is handled and is comprised following link: 1) upgrade R successively _Cvm ^l, m ∈ [1, dc]; 2) upgrade Q successively _Vm ^l, m ∈ [1, dc].Upgrade Q _Vm ^lNeed utilize R _Cvm ^lLastest imformation, so output signal handle to be introduced the processing delay of a clock cycle.The entire process process as shown in Figure 4.

Degree d with check-node _cCorrespondence, each link that output signal is handled all needs to carry out d _cInferior.

Step 1) is upgraded R as shown in Figure 4 _Cvm ^lComprise that symbol is definite, min 0 and min 1 select saturated processing three parts.

Sign (Δ _m) and sign (∏ Δ _m) carry out XOR (mould 2) and calculate, if XOR (mould 2) result equals 0 R so _Cvm ^lBe positive number, otherwise be negative.If num (min 0)=m, R so _Cvm ^lNumerical value before the saturated processing equals min 1, otherwise R _Cvm ^lNumerical value before the saturated processing equals min 0.Because min 0 and min 1 are 8 bit unsigned numbers, R _Cvm ^lBe 6 bit-binary complement codes, become 8 bit-binary complement code data transaction 6 bit-binary complement codes to export by saturated processing, dateout scope-32～31, the data less than-32 are represented with-32, represent with 31 greater than 31 data.

Step 2) as shown in Figure 4, from RAM reading of data Δ _mAnd the R of same sequence number m _Cvm ^lAddition, the result of addition carries out saturated processing and produces Q _Vm ^lQ _Vm ^lWith 8 bit-binary complement representations, R _Cvm ^lAnd Δ _mCarry out addition with 9 bit-binary complement codes, if data are greater than 127 before the saturated processing, data updated Q _Vm ^lGet 127; If data are less than-128 before the saturated processing, data updated Q _Vm ^lGet-128.

Claims (3)

1, the implementation method of a kind of layering minimum and LDPC decoding code check node processing, the check matrix of LDPC is divided into multilayer by the check-node number, the decoding iteration of every layer or each check-node is called sub-iteration, and the sub-iteration of whenever finishing once all layers or all check-nodes is then thought and finished the check matrix iteration one time; The output information of last straton iteration is as the input information of back one straton iteration; The output information of a preceding check matrix iteration is as the input information of a back check matrix iteration; Sub-iterations continuous counter between the continuous check matrix iteration; It is characterized in that:

A certain check-node is with the Q of all variable node correspondences of being attached thereto _v ^L-1And R _Cv ^L-1Subtract each other respectively, adopt the bubbling method to subtract each other and search absolute value minimum value and time minimum value the result, according to the Q of lookup result to back one check-node from all _v ^lAnd R _Cv ^lUpgrade, till predefined sub-iterations or iteration convergence;

During each straton iterative processing, same hardware serial shared processing is adopted in searching of absolute value minimum value and time minimum value;

Wherein, subscript l and l-1 represent l and l-1 second son iteration; Q _v ^L-1Represent that each variable node is to the input information of check-node after the iterative processing of l-1 second son; R _Cv ^L-1Represent that check-node is to the input information of each variable node after the iterative processing of l-1 second son; Q _v ^lAnd R _Cv ^lRepresent that the iterative processing of l second son needs updated information, Q _v ^lRepresent that each variable node is to the input information of check-node after the iterative processing of l second son; R _Cv ^lRepresent that check-node is to the input information of each variable node after the iterative processing of l second son

2, the implementation method of layering minimum according to claim 1 and LDPC decoding code check node processing, it is characterized in that: this method step is:

If a certain check matrix has l check-node, each check-node has d _cIndividual variable node is attached thereto,

1) for the first time during the check matrix iteration, decoder calculates its log-likelihood ratio λ according to the code word Y that receives, with λ with the information Q of each variable node to first check-node _V1 ⁰, Q _V2 ⁰, Q _V3 ⁰... Q _Vdc ⁰Initialization, first check-node is to the information R of each variable node _Cv1 ⁰, R _Cv2 ⁰, R _Cv3 ⁰... R _Cvdc ⁰All be initialized as 0;

With Q _V1 ⁰, Q _V2 ⁰, Q _V3 ⁰... Q _Vdc ⁰And R _Cv1 ⁰, R _Cv2 ⁰, R _Cv3 ⁰... R _Cvdc ⁰Subtract each other respectively, adopt the bubbling method to subtract each other and search absolute value minimum value and time minimum value the result, according to the Q of lookup result to second check-node from all _V1 ¹, Q _V2 ¹, Q _V3 ¹... Q _Vdc ¹And R _Cv1 ¹, R _Cv2 ¹, R _Cv3 ¹... R _Cvdc ¹Upgrade;

2) with Q _V1 ¹, Q _V2 ¹, Q _V3 ¹... Q _Vdc ¹And R _Cv1 ¹, R _Cv2 ¹, R _Cv3 ¹... R _Cvdc ¹Subtract each other respectively, adopt the bubbling method to subtract each other and search absolute value minimum value and time minimum value the result, according to the Q of lookup result to the 3rd check-node from all _V1 ², Q _V2 ², Q _V3 ²... Q _Vdc ²And R _Cv1 ², R _Cv2 ², R _Cv3 ²... R _Cvdc ²Upgrade;

3) repeating step 2), in the sub-iterations of the check matrix iteration first time,, then stop iteration if reach predefined iterations or iteration convergence;

4) if for the first time the check matrix iteration is finished, promptly l check-node all upgrades and finishes, and also do not reach predefined iterations or iteration and do not restrain, then the Q of last second son iteration renewal of check matrix iteration for the first time _V1 ^L-1, Q _V2 ^L-1, Q _V3 ^L-1... Q _Vdc ^L-1And R _Cv1 ^L-1, R _Cv2 ^L-1, R _Cv3 ^L-1... R _Cvdc ^L-1, as the initial value of the first second son iteration of the check matrix iteration second time,

[1] with Q _V1 ^L-1, Q _V2 ^L-1, Q _V3 ^L-1... Q _Vdc ^L-1And R _Cv1 ^L-1, R _Cv2 ^L-1, R _Cv3 ^L-1... R _Cvdc ^L-1Subtract each other respectively, try to achieve d _cThe symbol sign (Δ) of individual Δ value and each Δ,

Wherein, Δ={ Δ ₁, Δ ₂, Δ ₃... Δ _Dc, Δ ₁=Q _V1 ^L-1-R _Cv1 ^L-1..., Δ _Dc=Q _Vdc ^L-1-R _Cvdc ^L-1

Sign (Δ)=1 o'clock for negative for just in sign (Δ)=0 o'clock;

[2] adopt the bubbling method, from d _cFind out in the individual Δ | Δ | minimum value min0 and time minimum value min1, record min0 pairing variable node sequence number num (min0);

Wherein, | Δ | be the set of the absolute value of each Δ value;

[3] establish the pairing num of min0 (the min0)=m that finds in the step [2], and m ∈ [1, d _c], if need the Q of renewal _v ^lAnd R _Cv ^lPairing variable node sequence number is identical with the pairing variable node sequence number of min0, then R _Cvm ^lAbsolute value get min1, otherwise get min0; R _Cvm ^lSymbol be: the sign (Δ that removes present node sequence number correspondence _m) product of outer remaining sign (Δ); Q _Vm ^lGet Q _Vm ^l=Δ _m+ R _Cvm ^l

5) repeating step 4), in the sub-iterations of l check-node, if reach predefined iterations or iteration convergence, then stop iteration, otherwise, with the Q that upgrades of last second son iteration of the check matrix iteration second time _V1 ^2l-1, Q _V2 ^2l-1, Q _V3 ^2l-1... Q _Vdc ^2l-1And R _Cv1 ^2l-1, R _Cv2 ^2l-1, R _Cv3 ^2l-1... R _Cvdc ^2l-1,, proceed iterative processing, till reaching predefined iterations or iteration convergence as the initial value of the first second son iteration of check matrix iteration for the third time;

Wherein, variable node represents with the 8bit complement of two's two's complement that to the input information of check-node check-node is represented with the 6bit complement of two's two's complement to the input information of variable node.

3, the implementation method of layering minimum according to claim 2 and LDPC decoding code check node processing is characterized in that: after each Δ calculates, the result of calculation of Δ is carried out saturation arithmetic.

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