CN101605118B - HF-VHF communication frame synchronization system and method - Google Patents

HF-VHF communication frame synchronization system and method Download PDF

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CN101605118B
CN101605118B CN2009100232506A CN200910023250A CN101605118B CN 101605118 B CN101605118 B CN 101605118B CN 2009100232506 A CN2009100232506 A CN 2009100232506A CN 200910023250 A CN200910023250 A CN 200910023250A CN 101605118 B CN101605118 B CN 101605118B
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frame synchronization
correlation
sequence
frame
signal
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CN101605118A (en
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司江勃
李赞
权安
郝本建
王利鹏
刘和碧
张文博
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Xidian University
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Xidian University
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Abstract

The invention discloses an HF-VHF communication frame synchronization system and a method, mainly solving the problems of excessive device resource consumption and poor frame synchronization performance of the existing frame synchronization method. The frame synchronization process of the invention is as follows: a PN sequence is repeated for M times at a transmitting terminal to form a frame synchronization sequence; then control information or data is inserted behind the frame synchronization sequence to form a whole data frame to be sent out; a receiving signal and the local PN sequence are performed with correlation operation on a receiving end by a correlator, and a correlation value is written into a storage unit; the storage unit outputs M paths of parallel correlation values to a parallel decision device; if M paths of parallel correlation values all reach a preset threshold, M observation windows whose length is N are opened, the average values of correlation values with same position in the window are calculated, and a frame synchronization timing signal is produced according to maximum value position in N average values; or capture is continued. The invention has the characteristics of small device resource consumption and favourable frame synchronization performance, and can be used in HF-VHF communication to realize frame synchronization.

Description

A kind of HF-VHF communication frame synchronization system and method
Technical field
The invention belongs to communication technical field, relate to wireless communication technology, be specifically related to frame synchornization method, it is synchronous to be used in the HF-VHF communication achieve frame.
Background technology
HF-VHF communication mainly utilizes ionosphere, channels such as discrete E layer, meteoric trail and atmospheric duct that the reflection and the scattering process of HF-VHF signal are communicated, and is the important means of ground, aviation and marine communication.
Signal through the transmission of HF-VHF wireless channel usually receives influences such as ionospheric disturbance, multipath effect and frequency shift (FS); And be accompanied by the continuous quickening of urbanization process and developing rapidly of radio communication; Make HF-VHF communication face many new problems: at first, the crowded day by day of wireless signal significantly improves wireless background noise; Secondly, man-made noise progressively occupies the HF-VHF frequency range with disturbing; Once more, the noise that produces of the vehicles such as automobile strengthens day by day.This has higher reliability with regard to the method for synchronous that requires HF-VHF communication.
Be meant that synchronously the sending and receiving both sides act in agreement in time, so be also referred to as regularly.In digital communication system, be divided into according to synchronous effect: carrier synchronization, symbol synchronization, frame synchronization and net are synchronous.In wireless communication systems such as CDMA, adopt the PN sequence as frame synchronization sequence usually, the PN sequence can be resisted narrow-band noise and interference effectively, is a kind of well behaved synchronizing sequence.At present, the catching method of PN sequence has two kinds: a kind of is to utilize auxiliary channel to catch; Another kind is to catch through synchronizing sequence.Because the auxiliary channel method needs extra channel, obviously is not suitable for the HF-VHF communication system, so the method that in HF-VHF communication, adopts synchronizing sequence to catch usually.Usually use a PN sequence in this method as frame synchronization sequence; In the wireless communications environment that goes from bad to worse at present; Though the length through increasing the PN sequence can obtain frame synchronization performance preferably; But, be unfavorable for the realization of communication system because the increase of correlation computations length causes the increase of communication system to the device resource demand.
Summary of the invention
The objective of the invention is to overcome the deficiency of above-mentioned prior art; A kind of HF-VHF communication frame synchronization system and method are proposed; Under the situation that obtains identical frame synchronization performance; The short PN sequence of utilizing proposed by the invention repeats repeatedly as frame synchronization sequence and parallel detection, than adopting a long PN sequence obviously to reduce as the required device resource of the method for frame synchronization sequence.
For realizing above-mentioned purpose, the HF-VHF communication frame synchronization system that the present invention proposes comprises:
Framer is used to produce frame synchronization sequence, and itself and control information or data are formed complete Frame sends;
Local PN sequencer is used to produce local PN sequence, outputs to correlator;
Correlator is used for carrying out related operation with local PN sequence to received signal, correlation is quantized, and output to memory cell;
Memory cell be used to store the correlation after the quantification, and the parallel correlation of output is given the parallel judgment device;
The parallel judgment device; Be used for the correlation and the predefined threshold value of input are compared; And the signal of exporting the unlatching of indication watch window if the correlation of input all is greater than or equal to predefined threshold value, then indicates the signal of watch window unlatching effective to watch window; Otherwise this index signal is invalid;
Watch window is used under the effective situation of signal that the indication watch window is opened, storing N correlation continuously, gives the average processing unit;
The average processing unit is used for the identical correlation in observation window position is got average, and this N average is given select big map unit;
Select big map unit, be used for finding out the maximum of N average, give the frame synchronization timing generator peaked position;
The frame synchronization timing generator is used for specifying the moment to produce a pulse signal as the frame synchronization timing signal according to the peaked position of N average;
Delay unit was used for N sampling clock cycle of reception signal lag, and last code element of the frame synchronization sequence of time delayed signal is alignd with the frame synchronization timing signal.
HF-VHF communication frame method for synchronous for realizing that above-mentioned purpose the present invention proposes comprises the steps:
(1) the PN sequence that is L with a length of transmitting terminal repeats M configuration frame synchronizing sequence, with its start-up portion as each Frame, and inserts control information in its back or the complete Frame of data composition sends;
(2) receiving terminal utilizes a correlator to carry out related operation with local PN sequence to received signal, and the correlation y (n) that calculates is represented with r bit quantization;
(3) the correlation y (n) after will quantizing writes a memory cell with an input port and M output port, and gives the parallel judgment device through the parallel correlation in this memory cell output M road;
(4) parallel judgment device correlation and the predefined threshold value that the M road is parallel compares; If these correlations all are greater than or equal to predefined threshold value, execution in step (5) then, otherwise; Think not receive Frame, will continue execution in step (4);
(5) an opening M length is the watch window of N, and the correlation that position in the window is identical is got average, thereby obtains N mean value, produces frame synchronization timing signal, wherein 1≤P≤N according to the peaked position P in this N mean value again;
(6) will receive signal lag N sampling clock cycle, last code element of the frame synchronization sequence of time delayed signal is alignd with the frame synchronization timing signal.
The present invention has the following advantages:
1, under the situation that obtains identical frame synchronization performance, the short PN sequence of utilizing proposed by the invention repeats repeatedly as frame synchronization sequence and parallel detection, than adopting a long PN sequence obviously to reduce as the required device resource of the method for frame synchronization sequence;
2, correlator of employing and a memory cell proposed by the invention produce the parallel correlation in M road, compare with the method that adopts M correlator parallel computation, have reduced producing the parallel required device resource of correlation in M road effectively;
3, parallel detection proposed by the invention because that judgement requires is strict more, thereby has reduced the false synchronous probability of communication system.
Description of drawings
Fig. 1 is a system architecture diagram of the present invention;
Fig. 2 is the structured flowchart of correlator used in the present invention;
Fig. 3 is a frame synchronization flow chart of the present invention;
Fig. 4 is the sketch map of the frame structure that adopts of the present invention;
Fig. 5 is the present invention and single PN sequence method accurate synchronization probabilistic simulation comparison diagram;
Fig. 6 is the present invention and single PN sequence method missed synchronization probabilistic simulation comparison diagram;
Fig. 7 is the present invention and the false synchronous probability emulation of single PN sequence method comparison diagram.
Embodiment
With reference to figure 1; HF-VHF communication frame synchronization system of the present invention; Mainly by framer, correlator, local PN sequencer, memory cell, parallel judgment device, watch window, average processing unit, select big map unit, frame synchronization timing generator and delay unit and form, wherein:
The PN sequence that framer is L with a length repeats M configuration frame synchronizing sequence, and as the start-up portion of each Frame, the back of this frame synchronization sequence is inserted with control information or data, sends to form complete Frame;
Correlator links to each other with local PN sequencer, and the local PN sequence that local PN sequencer produces is as the input of correlator, and correlator carries out related operation with local PN sequence to received signal, and correlated results is quantized.The structure of this correlator is as shown in Figure 2; It comprises multiplier, integrator, squarer and adder; Multiplier will receive I in the signal, Q two paths of signals respectively with corresponding the multiplying each other of local PN sequence, give integrator with I, Q two-way multiplied result and carry out the integration that length is L respectively, squarer carries out a square processing respectively to I, Q two-way integral result; Give adder with I, Q two-way square value, the output of adder is exactly correlation;
Memory cell links to each other with correlator, and the output of correlator is as the input of memory cell, and memory cell is exported the parallel correlation in M road;
The parallel judgment device links to each other with memory cell; The output of memory cell is as the input of parallel judgment device, and parallel judgment device correlation and the predefined threshold value that the M road is parallel compares, and produces the signal that the indication watch window is opened; If these correlations all are greater than or equal to predefined threshold value; The signal of then indicating watch window to open is effective, otherwise this index signal is invalid;
Watch window links to each other with the parallel judgment device, and the output of parallel judgment device is as the input of watch window, if the signal that the indication watch window is opened is effective, then an opening M length is the watch window of N, and each window is stored N correlation continuously;
The average processing unit links to each other with watch window, and the output of watch window is as the input of average processing unit, and the average processing unit is got average to the identical correlation in position in the watch window, exports N average;
Select big map unit and link to each other with the average processing unit, the output of average processing unit is selected big map unit and from N average, is found out maximum as selecting the input of big map unit, and with the output of peaked position;
The frame synchronization timing generator with select big map unit and link to each other; Select the input of the output of big map unit as the frame synchronization timing generator, the frame synchronization timing generator is specifying the moment to produce a pulse signal as the frame synchronization timing signal based on the peaked position in N the average;
Delay unit will receive signal lag N sampling clock cycle, and last code element of the frame synchronization sequence of time delayed signal is alignd with the frame synchronization timing signal.
With reference to figure 3, frame synchornization method of the present invention comprises the steps:
Step 1; The PN sequence that is L with a length repeats M configuration frame synchronizing sequence; With its start-up portion, and insert control information in its back or data are formed complete Frame, the frame structure of the Frame of formation as each Frame; As shown in Figure 4, this Frame is sent by transmitting terminal.
Step 2, receiving terminal utilize a correlator to carry out related operation with local PN sequence to received signal, and the correlation y (n) that calculates is expressed as with r bit quantization: y ( n ) = ( Σ i = 1 L C ( i ) Q ( n - L + i ) ) 2 + ( Σ i = 1 L C ( i ) I ( n - L + i ) ) 2 , Q in the formula (n) expression receives the Q road signal in the signal, and I (n) expression receives the I road signal in the signal, and C (n) representes local PN sequence, and L representes the length of PN sequence.
Step 3; Correlation y (n) after quantizing is write a memory cell with an input port and M output port in order; This memory cell comprises L * M * R continuous address, and size is L * M * R * r bit, and wherein R representes the multiple of receiving terminal over-sampling.
Step 4 is read correlation in the address of the M from memory cell and is given the parallel judgment device, and the expression formula of this M address is: rd_add j=wr_add+j * L * R, 0≤j≤M-1 wherein, wr_add representes the address that writes of correlation y (n).
Step 5, parallel judgment device correlation and the predefined threshold value that the M road is parallel compares, if these correlations all are greater than or equal to predefined threshold value, then execution in step 6; Otherwise, think not receive Frame, will continue execution in step 5.
Step 6, an opening M length is the watch window of N, the correlation in w watch window is expressed as { y W, 1, y W, 2..., y W, N, wherein 1≤w≤M gets average to the identical correlation in position in M the watch window, and the N that an obtains mean value is expressed as { y 1, y 2..., y N, the expression formula of n mean value is: y n ‾ = 1 N Σ w = 1 N y w , n , 1≤n≤N wherein.
Step 7 is found out maximum y in the N that in step 6, the obtains mean value P, P is exactly the peaked position in the mean value, and wherein 1≤P≤N if this peaked position is P, then closes P the sampling clock in back at watch window and produces a pulse signal in the cycle as the frame synchronization timing signal.
Step 8 will receive signal lag N sampling clock cycle, and last code element of the frame synchronization sequence of time delayed signal is alignd with the frame synchronization timing signal, and the time delayed signal of frame synchronization timing signal back is exactly control information or the data in the Frame.
Effect of the present invention can further prove through following simulation example:
One, simulated conditions
The multiple R of receiving terminal over-sampling is set to 8; The length N of watch window is set to 16; Under the noiseless condition, 0.4 times of correlation peak as decision threshold; Adopt additive white gaussian noise channels, the excursion of signal to noise ratio snr is :-20dB～0dB, carry out frame synchronization 10000 times under each signal to noise ratio snr.
Two, emulation content
Emulation 1: be an instance of the present invention, the length of PN sequence is 64, and number of repetition is 2.
Emulation 2: be to adopt the instance of a PN sequence as the frame synchronization sequence method, the length of PN sequence is 128.
Emulation 3: be to adopt the instance of a PN sequence as the frame synchronization sequence method, the length of PN sequence is 64.
Three, simulation result
Fig. 5 has contrasted the accurate synchronization probability P D of said 3 emulation, and Fig. 6 has contrasted the missed synchronization probability P L of said 3 emulation, and Fig. 7 has contrasted the false synchronous probability PF of said 3 emulation.
Visible by Fig. 5, signal to noise ratio snr >=-during 10dB, the accurate synchronization probability P D of 3 emulation is basic identical; Reduction along with signal to noise ratio snr; The accurate synchronization probability of 3 emulation all begins to reduce, and the performance of the accurate synchronization of emulation 1 and emulation 2 is basic identical, and than emulation 3 high 2～3dB.
Visible by Fig. 6, signal to noise ratio snr >=-during 8dB, the missed synchronization probability P L of 3 emulation is basic identical; Reduction along with signal to noise ratio snr; The missed synchronization probability P L of 3 emulation begins to increase, because the judgment condition of emulation 1 is strict more, its missed synchronization probability P L is higher than emulation 2 and emulation 3.
Visible by Fig. 7, signal to noise ratio snr >=-during 10dB, the false synchronous probability PF of 3 emulation is basic identical; Reduction along with signal to noise ratio snr; The false synchronous probability PF of 3 emulation obviously increases, and the false net synchronization capability of emulation 2 is superior to emulation 3 about 3dB, and the false net synchronization capability of emulation 1 is superior to emulation 2 about 1dB.
Emulation 1 is 64 with the PN sequence length that emulation 3 is adopted, and the length of correlation computations is the half the of emulation 2, and required device resource approximately is the half the of emulation 2, but the frame synchronization performance of emulation 1 and emulation 2 is basic identical.
Comprehensive above-mentioned simulation result and analysis; Under the situation that obtains identical frame synchronization performance; The short PN sequence of utilizing proposed by the invention repeats repeatedly as frame synchronization sequence and parallel detection, than adopting a long PN sequence obviously to reduce as the required device resource of the method for frame synchronization sequence.And under above-mentioned simulated conditions, when signal to noise ratio snr >=-during 14dB, method accurate synchronization probability proposed by the invention can reach more than 90%, has good frame synchronization performance.
Concrete realization of the present invention FPGA capable of using or DSP or special chip and other programmable logic devices are accomplished.Said instance is a kind of implementation of the present invention in practical application, but implementation is not limited thereto, and can require according to the performance index of real system to adjust accordingly.

Claims (10)

1. HF-VHF communication frame synchronization system comprises:
Framer is used to produce frame synchronization sequence, and itself and control information or data are formed complete Frame sends;
Local PN sequencer is used to produce local PN sequence, outputs to correlator;
Correlator is used for carrying out related operation with local PN sequence to received signal, correlation is quantized, and output to memory cell;
Memory cell be used to store the correlation after the quantification, and the parallel correlation of output is given the parallel judgment device;
The parallel judgment device; Be used for the correlation and the predefined threshold value of input are compared; And the signal of exporting the unlatching of indication watch window if the correlation of input all is greater than or equal to predefined threshold value, then indicates the signal of watch window unlatching effective to watch window; Otherwise this index signal is invalid;
M watch window is used under the effective situation of signal that the indication watch window is opened, and an opening M length is the watch window of N, and each window is stored N correlation continuously, gives the average processing unit;
The average processing unit is used for the identical correlation in observation window position is got average, and the N that an obtains average is given select big map unit;
Select big map unit, be used for finding out the maximum of N average, give the frame synchronization timing generator peaked position;
The frame synchronization timing generator is used for specifying the moment to produce a pulse signal as the frame synchronization timing signal according to the peaked position of N average;
Delay unit was used for N sampling clock cycle of reception signal lag, and last code element of the frame synchronization sequence of time delayed signal is alignd with the frame synchronization timing signal.
2. frame synchronization system according to claim 1 is characterized in that frame synchronization sequence is to obtain through a PN sequence is repeated M time.
3. frame synchronization system according to claim 1 is characterized in that the correlation that memory cell writes stores in order, whenever writes a correlation, exports M correlation simultaneously.
4. frame synchronization system according to claim 1 is characterized in that comprising in the parallel judgment device M independently decision device, and wherein each decision device receives one road correlation.
5. frame synchronization system according to claim 1 is characterized in that frame synchronization timing generator P sampling clock after watch window is closed produces the frame synchronization timing signal in the cycle, and wherein P is the peaked position in N the mean value.
6. a HF-VHF communication frame method for synchronous comprises the steps:
(1) the PN sequence that is L with a length of transmitting terminal repeats M configuration frame synchronizing sequence, with its start-up portion as each Frame, and inserts control information in its back or the complete Frame of data composition sends;
(2) receiving terminal utilizes a correlator to carry out related operation with local PN sequence to received signal, and the correlation y (n) that calculates is represented with r bit quantization;
(3) the correlation y (n) after will quantizing writes a memory cell with an input port and M output port, and gives the parallel judgment device through the parallel correlation in this memory cell output M road;
(4) parallel judgment device correlation and the predefined threshold value that the M road is parallel compares; If these correlations all are greater than or equal to predefined threshold value, execution in step (5) then, otherwise; Think not receive Frame, will continue execution in step (4);
(5) an opening M length is the watch window of N, and the correlation that position in the window is identical is got average, thereby obtains N mean value, produces frame synchronization timing signal, wherein 1≤P≤N according to the peaked position P in this N mean value again;
(6) will receive signal lag N sampling clock cycle, last code element of the frame synchronization sequence of time delayed signal is alignd with the frame synchronization timing signal.
7. frame synchornization method according to claim 6; The size that it is characterized in that the described memory cell of step (3) is L * M * R * r bit; And comprise L * M * R continuous address, through reading, writing address control, make the parallel correlation in memory cell output M road; Wherein R representes the multiple of receiving terminal over-sampling, and r is the quantizing bit number of each correlation y (n).
8. frame synchornization method according to claim 6; Correlation y (n) after it is characterized in that step (3) is described and will quantizing writes a memory cell with an input port and M output port; Be that each correlation y (n) that correlator calculates is stored in the memory cell in order, each correlation y (n) address in memory cell has nothing in common with each other.
9. frame synchornization method according to claim 7 is characterized in that the described reading, writing address control of passing through, and makes the parallel correlation in memory cell output M road, is undertaken by following process:
9a) in said memory cells, correlation is write an address, this address is designated as wr_add;
9b) from M address of memory cell, read correlation simultaneously, the expression formula of this M address is: rd_add j=wr_add+j * L * R, wherein 0≤j≤M-1.
10. frame synchornization method according to claim 6; It is characterized in that step (5) is described according to the peaked position P generation frame synchronization timing signal in N the mean value, is to close P the sampling clock in back at watch window to produce a pulse signal in the cycle as the frame synchronization timing signal.
CN2009100232506A 2009-07-08 2009-07-08 HF-VHF communication frame synchronization system and method Expired - Fee Related CN101605118B (en)

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CN102801441B (en) * 2012-07-27 2014-08-27 北京邮电大学 Synchronous clock extraction method for receiving end in fully digital spread spectrum communication system
CN103023529B (en) * 2012-12-05 2014-08-20 天津光电通信技术有限公司 Field programmable gate array (FPGA) based method for achieving synchronous detection of oversampling Golay sequence
CN107872286B (en) * 2017-12-31 2023-08-25 南京火零信息科技有限公司 Frame synchronization device using double PN codes

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CN1466292A (en) * 2002-06-07 2004-01-07 ���ǵ�����ʽ���� OFDM transmitter and method for inserting pilot frequency into OFDM signal
CN1980205A (en) * 2005-11-29 2007-06-13 华为技术有限公司 Series generating system and method, transmitting and synchronizing method and power regulating system

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Publication number Priority date Publication date Assignee Title
CN1466292A (en) * 2002-06-07 2004-01-07 ���ǵ�����ʽ���� OFDM transmitter and method for inserting pilot frequency into OFDM signal
CN1980205A (en) * 2005-11-29 2007-06-13 华为技术有限公司 Series generating system and method, transmitting and synchronizing method and power regulating system

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