CN101604922B - Parallel current sharing method for converters with weighted average of per-unit values of output current - Google Patents

Abstract

The invention belongs to the technical field of parallel control of inverters, and relates to a parallel current sharing method for converters with the weighted average of per-unit values of output current. The widths of pulse signals of various inverter modules are used to represent per-unit values of output current, namely the percentage that the output current of a module accounts for the rated current thereof, the average value of the per-unit values of the output current of various modules is obtained through a mode of performing weighted voting on various pulse width signals, and the modules are converted into current values according to the average value to adjust respective output current to finally achieve that the per-unit values of the output current of the modules are equal within the allowed error range and realize the current sharing control of parallel inverters. The method is applicable to the parallel current sharing control of a plurality of inverter modules, particularly to the parallel current sharing control of a plurality of inverter modules with partially equal power. The current sharing control method can remarkably improve current sharing control accuracy,and ensure that the inverter modules bear corresponding output current according to the rated values thereof at the same time.

Description

A kind of average weighted inverter parallel current equalizing method of output current perunit value

Technical field

The present invention is a kind of average weighted inverter parallel current equalizing method of output current perunit value, belongs to Control Technique for Inverters in Parallel Operation field.

Background technology

The fast development of modern science and technology promotes deepening continuously and extensively for Power Electronic Technique research to the capacity of electric power system, the requirement more and more higher of Performance And Reliability.The parallel connection of modular power can increase power system capacity, while multiple inverter module parallel operations can improve flexibility and the redundancy of system.The key for realizing multiple inverter module parallel operations is to ensure the output current same frequency of each inverter, same-phase in parallel system, while the equal each module output current of rated power is consistent, that is, is realized " flowing ".

Inverter parallel scheme, which is divided into, two kinds of interconnection line and no control interconnection.No control interconnection scheme is difficult to extensive industrialization at present；It is the method compared using electric current to have one of current equalizing method of interconnection line shunt chopper.Each inverter is compared respective output current with stream bus signals, draws offset current, and control signal is adjusted accordingly and realizes sharing control, but the control accuracy of system is not high.It is necessary to existing current equalizing method is improved.

The content of the invention

The present invention is a kind of average weighted inverter parallel current equalizing method of output current perunit value.This method is applied to multiple inverter parallel sharing controls, the not all equal module inverter current sharing control of multiple power that are particularly suitable for use in.The present invention realizes inverter parallel sharing control with a kind of mode of pulse width weighted voting, the control method can effectively improve the inaccurate problem of analog signal, current sharing control accuracy is improved, while can ensure that each inverter module undertakes corresponding output current according to the rated value of itself.

Inverter parallel system by the first module, the second module, the 3rd module ..., the n-th wired in parallel constitutes, each inverter module of the present invention sends pulse signal to interconnection line simultaneously in given time, its pulsewidth represents that the perunit value of output current, the i.e. module output current account for the percentage of its rated current.Specific method for expressing is as shown in Figure 1, the cycle time of sine wave on the basis of T, define factor sigma (0 ＜ σ ＜ 1), α (0 ＜ α≤σ), β (σ ＜ β ＜ 1), each module starts to send high level pulse signal at the α T moment, (β-α) T time width is taken to come representation module output current accounts for its rated current 100%, if the percentage that certain module output current accounts for its rated current is γ %, the width for the pulse signal that the module is sent is (β-α) T γ %.The pulse width signal of each module is weighted using power as weights benchmark to obtain public pulse width signal, public pulse width signal is transferred to each module by system by interconnection line, and each module receives after public pulse width signal and to carry out output current regulation into respective output current value according to its pulse width conversion.The circuit reference of weighted voting《A kind of inverter parallel Phase synchronization control method of power weightings》(number of patent application：200910033279.2), the pulse signal of all modules of given time reaches after rising edge to be high level, its pulsewidth represents the perunit value of each module output current respectively, therefore all pulse signals each can reach trailing edge after the corresponding time and be changed into low level, the trailing edge moment can represent the perunit value of module output current, and the weighted voting of pulse width signal can essentially be replaced with to the trailing edge weighted voting.When the weights sum (hereinafter referred to as weights and) of all pulse width signals is uneven number, public pulse width signal is obtained when the weights in low level pulse width signal and the half more than the weights sum of all pulse width signals for low level, when all pulse width signals weights and be even number and when the power sum of some modules occur just be the half of general power, the false module circuit that false module signal weights are 1 is added in hardware flow equalizing circuit, it is always low level to make this false module signal, public pulse width signal is obtained for low level when being in low level signal weights in the signal including false module signal and Ge Lu pulse width signals simultaneously and more than all signal weights and half, public pulse width signal is obtained when being in the weights of low level pulse width signal and the half more than or equal to the weights sum of all pulse width signals for low level.

The width of a cycle public pulse signal as obtained by weighted voting may not be precisely the percentage of total rated current shared by total current, but the pulsewidth can represent the percentage of total rated current shared by total current.It is exactly the percentage of total rated current shared by total current just and the pulsewidth restrains after some cycles：Assuming that the width of each module pulse signal of initial time is not completely equivalent (if pulsewidth is essentially equal, system has reached stable state), respectively W₁₀、W₂₀、W₃₀、......、W_n0(W₁₀≤W₂₀≤W₃₀≤......≤W_n0), then now the maximum pulse width difference of all signals is Δ W₀=W_n0-W₁₀；The width that the public pulse signal of average gained is weighted in period 1 is W_o1, then must have W_o1＞ W₁₀Or W_o1＜ W_n0, each module is according to W_o1It is converted into respective output current value and carries out output current regulation so that the width of itself pulse signal is close to W_o1, the width that the period 1 terminates rear each module pulse signal is changed into W₁₁、W₂₁、W₃₁、......、W_n1(W₁₁≤W₂₁≤W₃₁≤......≤W_n1), then there must be W₁₁＞ W₁₀Or W_n1＜ W_n0, now the maximum pulse width difference of all signals is Δ W₁=W_n1-W₁₁, Δ W can be obtained according to conclusions₁＜ Δs W₀；Proving by the same methods, the width that second round terminates rear each module pulse signal is changed into W₁₂、W₂₂、W₃₂、......、W_n2(W₁₂≤W₂₂≤W₃₂≤......≤W_n2), then there must be W₁₂＞ W₁₁Or W_n2＜ W_n1, now the maximum pulse width difference of all signals is Δ W₂=W_n2-W₁₂＜ Δs W₁＜ Δs W₀；The maximum pulse width difference that all module pulse signals after each end cycle can be obtained by that analogy is poor less than the maximum pulse width of all module pulse signals of previous cycle, i.e. Δ W_x＜ Δs W_x-1, the maximum pulse width difference of all module pulse signals will be less and less, is finally reached Δ W_x=0, i.e., the width of all module pulse signals is equal after x cycle, and the percentage that each module output current accounts for its rated current is identical, i.e., perunit value is identical, and the output current of each module reaches stationary value, and parallel system, which is completed, flows process.

In the case where meeting above-mentioned condition, the utilization of the control method can obtain good stream effect, improve the reasonability of parallel system load distribution and substantially increase control accuracy.

Brief description of the drawings

Fig. 1 represents that module output current accounts for the specific method of its rated current percentage with pulsewidth for the present invention

Fig. 2 is the hardware flow equalizing circuit figure of the parallelly connected reverse converter system of the present invention

Fig. 3 is the stream schematic diagram of one of specific embodiment

Fig. 4 is the flow equalizing circuit figure of one of specific embodiment

Fig. 5 is two stream schematic diagram of specific embodiment

Fig. 6 is two flow equalizing circuit figure of specific embodiment

Fig. 7 is three stream schematic diagram of specific embodiment

Fig. 8 is three flow equalizing circuit figure of specific embodiment

Fig. 9 flows schematic diagram for the single-chip microcomputer of the present invention

Specific embodiment

Fig. 2 show the hardware flow equalizing circuit figure of the parallelly connected reverse converter system of the present invention, inverter parallel system by the first module, the second module, the 3rd module ..., the n-th wired in parallel constitutes, public pulse width signal PULSE is transferred to each module by system by interconnection line BUS, and each module is adjusted accordingly after receiving public pulse width signal.Hardware flow equalizing circuit is the signal deteching circuit n of the first signal deteching circuit 1 to the n-th, false module circuit A, power supply V by n signal deteching circuit_cc, comparator composition, wherein the first signal deteching circuit 1 is by the first optocoupler, the first pull-up resistor R₁₁, the first pull down resistor R₁₂Composition, secondary signal detects circuit 2 by the second optocoupler, the second pull-up resistor R₂₁, the second pull down resistor R₂₂Composition, the 3rd signal deteching circuit 3 is by the 3rd optocoupler, the 3rd pull-up resistor R₃₁, the 3rd pull down resistor R₃₂Composition, until the n-th signal deteching circuit n is by the n-th optocoupler, the n-th pull-up resistor R_n1, the n-th pull down resistor R_n2Composition, false module circuit A is by the first triode Q₁, the second triode Q₂, the first false module resistance R_o1, the second false module resistance R_o2, phase inverter G composition；Power supply V_ccPhotodiode P poles and phototriode C poles, the photodiode P poles of the second optocoupler and phototriode C poles, the photodiode P poles of the 3rd optocoupler and phototriode C poles respectively with the first optocoupler is until photodiode P poles and phototriode C poles, the first triode Q of the n-th optocoupler₁E levels connection, the first pull-up resistor R₁₁Upper end is connected with the phototriode E poles of the first optocoupler, the first pull down resistor R₁₂Lower end is connected to ground, the second pull-up resistor R₂₁Upper end is connected with the phototriode E poles of the second optocoupler, the second pull down resistor R₂₂Lower end is connected to ground, the 3rd pull-up resistor R₃₁Upper end is connected with the phototriode E poles of the 3rd optocoupler, the 3rd pull down resistor R₃₂Lower end is connected to ground, until the n-th pull-up resistor R_n1Upper end is connected with the phototriode E poles of the n-th optocoupler, the n-th pull down resistor R_n2Lower end is connected to ground, the first false module resistance R_o1Upper end and the first triode Q₁C levels connection, the second false module resistance R_o2Lower end and the second triode Q₂C levels connection, the first pull-up resistor R₁₁Lower end and the first pull down resistor R₁₂Upper end junction constitutes the intermediate ends of the first signal deteching circuit 1, the second pull-up resistor R₂₁Lower end and the second pull down resistor R₂₂Upper end junction constitutes the intermediate ends that secondary signal detects circuit 2, the 3rd pull-up resistor R₃₁Lower end and the 3rd pull down resistor R₃₂Upper end junction constitutes the intermediate ends of the 3rd signal deteching circuit 3, until the n-th pull-up resistor R_n1Lower end and the n-th pull down resistor R_n2Upper end junction constitutes the n-th signal deteching circuit n intermediate ends, the first false module resistance R_o1Lower end and the second false module resistance R_o2Upper end junction constitutes false module circuit A intermediate ends, intermediate ends, the secondary signal of first signal deteching circuit 1 detect that the intermediate ends of circuit 2, the intermediate ends of the 3rd signal deteching circuit 3 are connected up to the inverting input of the n-th signal deteching circuit n intermediate ends, false module circuit A intermediate ends and comparator, the first triode Q₁B levels be connected with phase inverter G output ends, the second triode Q₂B levels be connected with phase inverter G inputs, the second triode Q₂E levels be connected to ground；The pulse width signal PULSE1 of first module is received by the photodiode N poles of the first optocoupler, the pulse width signal PULSE2 of second module is received by the photodiode N poles of the second optocoupler, the pulse width signal PULSE3 of 3rd module is received by the photodiode N poles of the 3rd optocoupler, until the pulse width signal PULSEn of the n-th module is received by the photodiode N poles of the n-th optocoupler, false module signal AUX is by phase inverter G inputs and the second triode Q₂B poles receive, middle terminal voltage V_ by comparator inverting input receive, comparison voltage V_refReceived by the in-phase input end of comparator, public pulse width signal PULSE is exported by comparator.

First modular power is P₁, pulse width signal weights are Q₁, the second modular power is P₂, pulse width signal weights are Q₂, the 3rd modular power is P₃, pulse width signal weights are Q₃, until the n-th modular power is P_n, pulse width signal weights are Q_n, false module signal AUX weights are 1, and the weights for defining all other module are all higher than or equal to 1, are made $\frac{P_1}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}=\frac{P_2}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}=\frac{P_3}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}=\&CenterDot;\&CenterDot;\&CenterDot;=\frac{P_n}{Q_n},$ Q₁R₁₁=Q₂R₂₁=Q₃R₃₁=...=Q_nR_n1=R_o1, $\frac{R_{11}}{R_{12}}=\frac{R_{21}}{R_{22}}=\frac{R_{31}}{R_{32}}=\&CenterDot;\&CenterDot;\&CenterDot;=\frac{R_{n1}}{{\mathrm{<figure-callout\; id="2"\; label="R\; n"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">R</figure-callout>}}_n}=\frac{R_{o1}}{{\mathrm{<figure-callout\; id="2"\; label="R\; o"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">R</figure-callout>}}_o}=\frac{1}{2};$ When the weights sum of all pulse width signals is uneven number, false module signal AUX is set to high level, false module circuit A is added without in flow equalizing circuit, each module of given time sends pulse width signal simultaneously, now all signals are that high level turns off the optocoupler of the first signal deteching circuit to the n-th signal deteching circuit, comparator anti-phase input terminal voltage is V_=0, and homophase input terminal voltage is $V_{\mathrm{ref}}=\frac{1}{2}{V}_{\mathrm{cc}},$ The public pulse width signal PULSE of comparator output terminal is high level；When the first module pulse width signal PULSE1 is low level, the first optocoupler is turned on, and disregards optocoupler conduction voltage drop, comparator anti-phase input terminal voltage is $V\_=\frac{R_{12}//R_{22}//\&CenterDot;\&CenterDot;\&CenterDot;//R_{n2}}{R_{12}//R_{22}//\&CenterDot;\&CenterDot;\&CenterDot;//{\mathrm{<figure-callout\; id="2"\; label="R\; n"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">R</figure-callout>}}_n+R_{11}}{V}_{\mathrm{cc}},$ Homophase input terminal voltage is $V_{\mathrm{ref}}=\frac{1}{2}{V}_{\mathrm{cc}},$ Work as R₁₂//R₂₂//…//R_n2＞ R₁₁When comparator output terminal public pulse width signal PULSE be low level, work as R₁₂//R₂₂//…//R_n2＜ R₁₁When comparator output terminal public pulse width signal PULSE be high level；When the first module pulse width signal PULSE1 is low level, and the second module pulse width signal PULSE2 is low level, the first optocoupler and the second optocoupler are turned on, and comparator anti-phase input terminal voltage is $V\_=\frac{R_{12}//R_{22}//\&CenterDot;\&CenterDot;\&CenterDot;//R_{n2}}{R_{12}//R_{22}//\&CenterDot;\&CenterDot;\&CenterDot;//{\mathrm{<figure-callout\; id="2"\; label="R\; n"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">R</figure-callout>}}_n+R_{11}//R_{21}}{V}_{\mathrm{cc}},$ Work as R₁₂//R₂₂//…//R_n2＞ R₁₁//R₂₁When comparator output terminal public pulse width signal PULSE be low level, work as R₁₂//R₂₂//…//R_n2＜ R₁₁//R₂₁When comparator output terminal public pulse width signal PULSE be high level, when being less than all pull down resistor parallel values in the corresponding pull-up resistor parallel value of low level pulse width signal, the public pulse width signal PULSE of comparator output terminal is low level；The weights sum of all pulse width signals is even number and the power sum of some modules occurs when being just the half of general power, false module signal AUX is set to low level, false module circuit A is added in flow equalizing circuit, each module of given time sends pulse width signal simultaneously, now all pulse width signals are that high level turns off the optocoupler of the first signal deteching circuit to the n-th signal deteching circuit, and comparator anti-phase input terminal voltage is $V\_=\frac{R_{12}//R_{22}//\&CenterDot;\&CenterDot;\&CenterDot;//{\mathrm{<figure-callout\; id="2"\; label="R\; n"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">R</figure-callout>}}_n//R_{o2}}{R_{12}//R_{22}//\&CenterDot;\&CenterDot;\&CenterDot;//{\mathrm{<figure-callout\; id="2"\; label="R\; n"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">R</figure-callout>}}_n//R_{o2}+R_{o1}}{V}_{\mathrm{cc}},$ Homophase input terminal voltage is $V_{\mathrm{ref}}=\frac{1}{2}{V}_{\mathrm{cc}},$ Make R₁₂//R₂₂//…//R_n2//R_o2＜ R_o1, the public pulse width signal PULSE of comparator output terminal is high level；When the first module pulse width signal PULSE1 is low level, comparator anti-phase input terminal voltage is $V\_=\frac{R_{12}//R_{22}//\&CenterDot;\&CenterDot;\&CenterDot;//{\mathrm{<figure-callout\; id="2"\; label="R\; n"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">R</figure-callout>}}_n//R_{o2}}{R_{12}//R_{22}//\&CenterDot;\&CenterDot;\&CenterDot;//{\mathrm{<figure-callout\; id="2"\; label="R\; n"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">R</figure-callout>}}_n//R_{o2}+R_{11}//R_{o1}}{V}_{\mathrm{cc}},$ Homophase input terminal voltage is $V_{\mathrm{ref}}=\frac{1}{2}{V}_{\mathrm{cc}},$ Work as R₁₂//R₂₂//…//R_n2//R_o2＞ R₁₁//R_o1When comparator output terminal public pulse width signal PULSE be low level, work as R₁₂//R₂₂//…//R_n2//R_o2＜ R₁₁//R_o1When comparator output terminal public pulse width signal PULSE be high level, when being less than all pull down resistors and false module second resistance parallel value in the corresponding pull-up resistor of low level pulse width signal and false module first resistor parallel value, the public pulse width signal PULSE of comparator output terminal is low level.

One of specific embodiment：The inverter module parallel connection of one 10kW inverter module and three 5kW

The embodiment has 4 shunt chopper modules, assuming that the percentage that each module output current of initial time accounts for its rated value is respectively 20%, 40%, 50%, 60%, factor alpha=0.2, β=0.8 are taken, then the width of four module pulse width signals is respectively $\frac{(0.8-0.2)20}{100}T=0.12T,$ $\frac{(0.8-0.2)40}{100}T=0.24T,$ $\frac{(0.8-0.2)50}{100}T=0.3T,$ $\frac{(0.8-0.2)60}{100}T=0.36T.$ Limit evidence $\frac{P_1}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}=\frac{P_2}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}=\frac{P_3}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}=\&CenterDot;\&CenterDot;\&CenterDot;=\frac{P_n}{Q_n},$ The weights that each 5kW modules might as well be defined are 1, then the weights of 10kW modules are 2, weights of all module pulse width signals and for 5, are uneven number, then false module signal AUX, which is set in high level, flow equalizing circuit, is added without false module circuit.Fig. 3 show the stream schematic diagram of one of specific embodiment.The pulse width signal PULSE1 of 10kW inverter module output in figure, weights are 2, and the pulse width signal of three 5kW inverter module output is respectively PULSE2, PULSE3, PULSE4, and weights are 1, Ts is the cycle time of public pulse width signal, Ts=T.Public pulse width signal PULSE is obtained when the weights in low level pulse width signal and the weights more than all pulse width signals and 5 half for low level, as long as weights herein in low level pulse width signal and thinking the weights and 5 half more than all pulse width signals more than or equal to 3.

Fig. 4 show the flow equalizing circuit figure of one of specific embodiment.First modular power is 10kW, and pulse width signal PULSE1 weights are 2, and the second modular power is 5kW, pulse width signal PULSE2 weights are 1, and the 3rd modular power is 5kW, and pulse width signal PULSE3 weights are 1,4th modular power is 5kW, and pulse width signal PULSE4 weights are 1, V_ccFor power supply voltage, V_ is comparator anti-phase input terminal voltage, $V_{\mathrm{ref}}=\frac{1}{2}{V}_{\mathrm{cc}}.$ According to $\frac{P_1}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}=\frac{P_2}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}=\frac{P_3}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}=\&CenterDot;\&CenterDot;\&CenterDot;=\frac{P_n}{Q_n},$ Q₁R₁₁=Q₂R₂₁=Q₃R₃₁=...=Q_nR_n1, $\frac{R_{11}}{R_{12}}=\frac{R_{21}}{R_{22}}=\frac{R_{31}}{R_{32}}=\&CenterDot;\&CenterDot;\&CenterDot;=\frac{R_{n1}}{{\mathrm{<figure-callout\; id="2"\; label="R\; n"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">R</figure-callout>}}_n}=\frac{1}{2},$ Have $\frac{P_1}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}=\frac{10\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">k</figure-callout>}}{2}=\frac{P_2}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}=\frac{5\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">k</figure-callout>}}{1}=\frac{P_3}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}=\frac{5\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">k</figure-callout>}}{1}=\frac{P_4}{Q_4}=\frac{5\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">k</figure-callout>}}{1},$ There is 2R in correspondence flow equalizing circuit₁₁=R₂₁=R₃₁=R₄₁, $\frac{R_{11}}{R_{12}}=\frac{R_{21}}{R_{22}}=\frac{R_{31}}{R_{32}}=\frac{R_{41}}{R_{42}}=\frac{1}{2}.$ Given time four road pulse width signal PULSE1, PULSE2, PULSE3, PULSE4 turns off the optocoupler of the first signal deteching circuit to the 4th signal deteching circuit for high level simultaneously, and comparator anti-phase input terminal voltage is：V_=0, homophase input terminal voltage is： $V_{\mathrm{ref}}=\frac{1}{2}{V}_{\mathrm{cc}},$ Now comparator is output as high level, i.e., public pulse width signal PULSE is high level；When the first module pulse width signal PULSE1 is low level, the first optocoupler is turned on, and is now in the weights of low level pulse width signal and for 2, is according to comparator anti-phase input terminal voltage is calculated： $V\_=\frac{\frac{2}{5}{R}_{21}}{\frac{2}{5}{R}_{21}+R_{21}}{V}_{\mathrm{cc}}=\frac{2}{7}{V}_{\mathrm{cc}},$ Homophase input terminal voltage is： $V_{\mathrm{ref}}=\frac{1}{2}{V}_{\mathrm{cc}},$ $\frac{2}{7}{V}_{\mathrm{cc}}<\frac{1}{2}{V}_{\mathrm{cc}},$ Now comparator is output as high level, i.e., public pulse width signal PULSE is high level；When the first module pulse width signal PULSE1 is low level, first optocoupler and the conducting of the second optocoupler when second module pulse width signal PULSE2 is low level, it is now in the weights of low level pulse width signal and for 3, is according to comparator anti-phase input terminal voltage is calculated： $V\_=\frac{\frac{2}{5}{R}_{21}}{\frac{2}{5}{R}_{21}+\frac{1}{3}{R}_{21}}{V}_{\mathrm{cc}}=\frac{6}{11}{V}_{\mathrm{cc}},$ Homophase input terminal voltage is： $V_{\mathrm{ref}}=\frac{1}{2}{V}_{\mathrm{cc}},$ $\frac{6}{11}{V}_{\mathrm{cc}}>\frac{1}{2}{V}_{\mathrm{cc}},$ Now comparator is output as low level, i.e., public pulse width signal PULSE is low level.Weights then in low level pulse width signal and public pulse width signal PULSE is obtained during more than or equal to 3 for low level, percentage 40% represented by public pulse width signal is the desired value that all inverter module output currents account for its rated current percentage, i.e., the expectation perunit value of each module output current is 0.4.Public pulse width signal PULSE is transferred to each module by system by interconnection line BUS, and each module, which is received, is converted into respective output current value progress output current regulation after public pulse width signal.

The two of specific embodiment：The inverter module parallel connection of one 10kW inverter module and four 5kW

The embodiment has 5 shunt chopper modules, assuming that the percentage that each module output current of initial time accounts for its rated value is respectively 20%, 30%, 40%, 50%, 60%, factor alpha=0.2, β=0.8 are taken, then the width of five module pulse width signals is respectively $\frac{(0.8-0.2)20}{100}T=0.12T,$ $\frac{(0.8-0.2)30}{100}T=0.18T,$ $\frac{(0.8-0.2)40}{100}T=0.24T,$ $\frac{(0.8-0.2)50}{100}T=0.3T,$ $\frac{(0.8-0.2)60}{100}T=0.36T.$ According to $\frac{P_1}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}=\frac{P_2}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}=\frac{P_3}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}=\&CenterDot;\&CenterDot;\&CenterDot;=\frac{P_n}{Q_n},$ The weights that each 5kW modules might as well be defined are 1, then the weights of 10kW modules are 2, weights of all module pulse width signals and for 6, for even number, and there is the half that the power sum of some modules is just general power, such as 10kW module is 15kW plus 5kW modular power, is just general power 30kW half.Then false module signal AUX is set to low level, and false module circuit is added in flow equalizing circuit.Fig. 5 show the stream schematic diagram of the two of specific embodiment.The pulse width signal PULSE1 of 10kW inverter module output in figure, weights are 2, the pulse width signal of four 5kW inverter module output is respectively PULSE2, PULSE3, PULSE4, PULSE5, weights are 1, AUX is false module signal, weights are the cycle time that 1, Ts is public pulse width signal, Ts=T.Public pulse width signal PULSE is obtained for low level when being in low level signal weights in the signal including false module signal AUX and Ge Lu pulse width signal simultaneously and more than all signal weights and 7 half, i.e., public pulse width signal PULSE is obtained when the weights in low level pulse width signal and the weights more than or equal to all pulse width signals and 6 half for low level.

Fig. 6 show the flow equalizing circuit figure of the two of specific embodiment.First modular power is 10kW, pulse width signal PULSE1 weights are 2, and the second modular power is 5kW, and pulse width signal PULSE2 weights are 1,3rd modular power is 5kW, pulse width signal PULSE3 weights are 1, and the 4th modular power is 5kW, and pulse width signal PULSE4 weights are 1,5th modular power is 5kW, pulse width signal PULSE5 weights are 1, and false module signal AUX weights are 1, V_ccFor power supply voltage, V_ is comparator anti-phase input terminal voltage, $V_{\mathrm{ref}}=\frac{1}{2}{V}_{\mathrm{cc}}.$ According to $\frac{P_1}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}=\frac{P_2}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}=\frac{P_3}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}=\&CenterDot;\&CenterDot;\&CenterDot;=\frac{P_n}{Q_n},$ Q₁R₁₁=Q₂R₂₁=Q₃R₃₁=...=Q_nR_n1=R_o1, $\frac{R_{11}}{R_{12}}=\frac{R_{21}}{R_{22}}=\frac{R_{31}}{R_{32}}=\&CenterDot;\&CenterDot;\&CenterDot;=\frac{R_{n1}}{{\mathrm{<figure-callout\; id="2"\; label="R\; n"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">R</figure-callout>}}_n}=\frac{R_{o1}}{R_{o2}}=\frac{1}{2},$ Have $\frac{P_1}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}=\frac{10\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">k</figure-callout>}}{2}=\frac{P_2}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}=\frac{5\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">k</figure-callout>}}{1}=\frac{P_3}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}=\frac{5\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">k</figure-callout>}}{1}=\frac{P_4}{Q_4}=\frac{5\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">k</figure-callout>}}{1}=\frac{P_5}{Q_5}=\frac{5\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">k</figure-callout>}}{1},$ 2R in correspondence flow equalizing circuit₁₁=R₂₁=R₃₁=R₄₁=R₅₁=R_o1, $\frac{R_{11}}{R_{12}}=\frac{R_{21}}{R_{22}}=\frac{R_{31}}{R_{32}}=\frac{R_{41}}{R_{42}}=\frac{R_{51}}{R_{52}}=\frac{R_{o1}}{R_{o2}}=\frac{1}{2}.$ False module signal AUX is set to low level, and false module circuit adds flow equalizing circuit.The road pulse width signal of given time five turns off the optocoupler of the first signal deteching circuit to the 5th signal deteching circuit for high level simultaneously, and comparator anti-phase input terminal voltage is： $V\_=\frac{\frac{2}{7}{R}_{21}}{\frac{2}{7}{R}_{21}+R_{21}}{V}_{\mathrm{cc}}=\frac{2}{9}{V}_{\mathrm{cc}},$ Homophase input terminal voltage is： $V_{\mathrm{ref}}=\frac{1}{2}{V}_{\mathrm{cc}},$ $\frac{2}{9}{V}_{\mathrm{cc}}<\frac{1}{2}{V}_{\mathrm{cc}},$ Now comparator is output as high level, i.e., public pulse width signal PULSE is high level；When the first module pulse width signal is low level, the first optocoupler is turned on, and is now in the weights of low level pulse width signal and for 2, is according to comparator anti-phase input terminal voltage is calculated： $V\_=\frac{\frac{2}{7}{R}_{21}}{\frac{2}{7}{R}_{21}+\frac{1}{3}{R}_{21}}{V}_{\mathrm{cc}}=\frac{6}{13}{V}_{\mathrm{cc}},$ Homophase input terminal voltage is： $V_{\mathrm{ref}}=\frac{1}{2}{V}_{\mathrm{cc}},$ $\frac{6}{13}{V}_{\mathrm{cc}}<\frac{1}{2}{V}_{\mathrm{cc}},$ Now comparator is output as high level, i.e., public pulse width signal PULSE is high level；When the first module pulse width signal PULSE1 is low level, first optocoupler and the conducting of the second optocoupler when second module pulse width signal PULSE2 is low level, it is now in the weights of low level pulse width signal and for 3, is according to comparator anti-phase input terminal voltage is calculated： $V\_=\frac{\frac{2}{7}{R}_{21}}{\frac{2}{7}{R}_{21}+\frac{1}{4}{R}_{21}}{V}_{\mathrm{cc}}=\frac{8}{15}{V}_{\mathrm{cc}},$ Homophase input terminal voltage is： $V_{\mathrm{ref}}=\frac{1}{2}{V}_{\mathrm{cc}},\frac{8}{15}{V}_{\mathrm{cc}}>\frac{1}{2}{V}_{\mathrm{cc}},$ Now comparator is output as low level, i.e., public pulse width signal PULSE is low level.Then public pulse width signal PULSE is obtained for low level when being in low level signal weights in the signal including false module signal AUX and Ge Lu pulse width signal simultaneously and more than all signal weights and 7 half, public pulse width signal PULSE is obtained when the weights i.e. in low level pulse width signal and the weights more than or equal to all pulse width signals and 6 half for low level, percentage 30% represented by public pulse width signal is the desired value that all inverter module output currents account for its rated current percentage, the expectation perunit value of i.e. each module output current is 0.3.Public pulse width signal PULSE is transferred to each module by system by interconnection line BUS, and each module receives after public pulse width signal and to carry out output current regulation into respective output current value according to its pulse width conversion.

The three of specific embodiment：The inverter module of one 10kW inverter module, 5kW inverter module and a 3kW is in parallel

The embodiment has 3 shunt chopper modules, it is assumed that the percentage that each module output current of initial time accounts for its rated value is respectively 30%, 40%, 50%, takes factor alpha=0.2, β=0.8, then the width of three module pulse width signals is respectively $\frac{(0.8-0.2)30}{100}T=0.18T,$ $\frac{(0.8-0.2)40}{100}T=0.24T,$ $\frac{(0.8-0.2)50}{100}T=0.3T.$ According to $\frac{P_1}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}=\frac{P_2}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}=\frac{P_3}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}=\&CenterDot;\&CenterDot;\&CenterDot;=\frac{P_n}{Q_n},$ The weights that 3kW modules might as well be defined are 3, then the weights of 5kW modules are 5, the weights of 10kW modules are 10, weights of all module pulse width signals and for 18,18 be even number herein, but not there are pulse width signal weights and equal to total weight value and the situation of half, false module signal AUX, which is set in high level, flow equalizing circuit, is added without false module circuit.Fig. 7 show the stream schematic diagram of the three of specific embodiment.The pulse width signal PULSE1 of 10kW inverter module output in figure, weights are 10, the pulse width signal PULSE2 of 5kW inverter module output, weights are 5, the pulse width signal PULSE3 of 3kW inverter module output, weights are the cycle time that 3, Ts is public pulse width signal, Ts=T.Public pulse width signal PULSE is obtained when the weights in low level pulse width signal and the weights more than all pulse width signals and 18 half for low level, as long as PULSE1 is in low level herein, weights in low level pulse width signal and it is greater than or equal to 10, i.e. weights and 18 half more than all pulse width signals.

Fig. 8 show the flow equalizing circuit figure of the three of specific embodiment.First modular power is 10kW, and pulse width signal PULSE1 weights are 10, and the second modular power is 5kW, and pulse width signal PULSE2 weights are 5, and the 3rd modular power is 3kW, and pulse width signal PULSE3 weights are 3, V_ccFor power supply voltage, V_ is comparator anti-phase input terminal voltage, $V_{\mathrm{ref}}=\frac{1}{2}{V}_{\mathrm{cc}}.$ According to $\frac{P_1}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}=\frac{P_2}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}=\frac{P_3}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}=\&CenterDot;\&CenterDot;\&CenterDot;=\frac{P_n}{Q_n},$ Q₁R₁₁=Q₂R₂₁=Q₃R₃₁=...=Q_nR_n1, $\frac{R_{11}}{R_{12}}=\frac{R_{21}}{R_{22}}=\frac{R_{31}}{R_{32}}=\&CenterDot;\&CenterDot;\&CenterDot;=\frac{R_{n1}}{{\mathrm{<figure-callout\; id="2"\; label="R\; n"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">R</figure-callout>}}_n}=\frac{1}{2},$ Have $\frac{P_1}{{\mathrm{<figure-callout\; id="1"\; label="Q"\; filenames="H2009101812994E00021.png,H2009101812994E00062.png"\; state="\{\{state\}\}">Q</figure-callout>}}_1}=\frac{10k}{10}=\frac{P_2}{{\mathrm{<figure-callout\; id="2"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}=\frac{5k}{5}=\frac{P_3}{{\mathrm{<figure-callout\; id="3"\; label="Q"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">Q</figure-callout>}}_3}=\frac{3\mathrm{<figure-callout\; id="3"\; label="k"\; filenames="H2009101812994E00021.png"\; state="\{\{state\}\}">k</figure-callout>}}{3},$ There is 10R in corresponding circuits₁₁=5R₂₁=3R₃₁, $\frac{R_{11}}{R_{12}}=\frac{R_{21}}{R_{22}}=\frac{R_{31}}{R_{32}}=\frac{1}{2}.$ The road pulse width signal of given time three turns off the optocoupler of the first signal deteching circuit to the 3rd signal deteching circuit for high level simultaneously, and comparator anti-phase input terminal voltage is：V_=0, homophase input terminal voltage is： $V_{\mathrm{ref}}=\frac{1}{2}{V}_{\mathrm{cc}},$ Now comparator is output as high level, i.e., public pulse width signal PULSE is high level；When the first module pulse width signal PULSE1 is low level, the first optocoupler is turned on, and is now in the weights of low level pulse width signal and for 10, is according to comparator anti-phase input terminal voltage is calculated： $V\_=\frac{\frac{5}{9}{R}_{21}}{\frac{5}{9}{R}_{21}+\frac{1}{2}{R}_{21}}{V}_{\mathrm{cc}}=\frac{10}{19}{V}_{\mathrm{cc}},$ Homophase input terminal voltage is： $V_{\mathrm{ref}}=\frac{1}{2}{V}_{\mathrm{cc}},$ $\frac{10}{19}{V}_{\mathrm{cc}}>\frac{1}{2}{V}_{\mathrm{cc}},$ Now comparator is output as low level, i.e., public pulse width signal PULSE is low level.When the first module pulse width signal PULSE1 is in high level, no matter whether PULSE2, PULSE3 are low level, and the output of comparator is high level；As long as PULSE1 is in low level, the anti-phase input terminal voltage of comparator is greater than comparator homophase input terminal voltage, and comparator is output as low level, i.e., public pulse width signal PULSE is low level.Public pulse width signal PULSE is obtained when weights then in low level pulse width signal and the weights more than all pulse width signals and 18 half for low level, as long as PULSE1 is in low level herein, weights in low level pulse width signal and it is greater than or equal to 10, i.e. more than the weights and 18 half of all pulse width signals, percentage 30% represented by public pulse width signal is the desired value that all inverter module output currents account for its rated current percentage, i.e., the expectation perunit value of each module output current is 0.3.Public pulse width signal PULSE is transferred to each module by system by interconnection line BUS, and each module receives after public pulse width signal and to carry out output current regulation into respective output current value according to its pulse width conversion.

The four of specific embodiment：Voting is weighted using CPU

The single-chip microcomputer that Fig. 9 show the present invention flows schematic diagram.Inverter parallel system is by the first module, second module, 3rd module, ..., n-th wired in parallel is constituted, each inverter module of given time sends pulse signal by interconnection line BUS to single-chip microcomputer simultaneously, its pulsewidth represents the perunit value of the module output current, the pulse width signal received is weighted single-chip microcomputer using power as weights benchmark, and carry out the judgement of majority, it is low level to obtain public pulse width signal when judging the weights in low level pulse width signal and the half more than or equal to the weights sum of all pulse width signals, and public pulse width signal is transferred to by each module by interconnection line BUS, each module receive after public pulse width signal according to its pulse width conversion into respective output current value carry out output current regulation.

Claims (1)

1. a kind of average weighted inverter parallel current equalizing method of output current perunit value, it is characterized in that each module of inverter parallel represents the perunit value of the module output current with pulse width signal (output current accounts for the percentage of its rated current), the average value of each module perunit value is obtained by weighted average circuit, the weights (the hereinafter also referred to weights of pulse width signal) of each module are determined by modular power, each module is converted into respective output current value according to the average value and carries out output current regulation, finally realize that the output current perunit value of each module is equal in the error range of permission；

Specific method is：The cycle time of sine wave on the basis of T, define factor sigma (0 ＜ σ ＜ 1), α (0 ＜ α≤σ), β (σ ＜ β ＜ 1), each module starts to send pulse signal at the α T moment, (β-α) T time width is taken to come representation module output current accounts for its rated current 100%, if the percentage that certain module output current accounts for its rated current is γ %, then the width for the pulse signal that the module is sent is (β-α) T γ %, shunt chopper sharing control is realized by way of to each module pulse width signal weighted voting, so as to improve current sharing control accuracy, ensure that each inverter module output current perunit value is equal in the error range of permission；

The implementation method of each module pulse width signal weighted voting is as follows：Inverter parallel system by the first module, the second module, the 3rd module ..., the n-th wired in parallel constitutes, public pulse width signal PULSE is transferred to each module by system by interconnection line BUS, and each module is adjusted accordingly after receiving public pulse width signal；Hardware flow equalizing circuit is the signal deteching circuit n of the first signal deteching circuit 1 to the n-th, false module circuit A, power supply V by n signal deteching circuit_cc, comparator composition, wherein the first signal deteching circuit 1 is by the first optocoupler, the first pull-up resistor R₁₁, the first pull down resistor R₁₂Composition, secondary signal detects circuit 2 by the second optocoupler, the second pull-up resistor R₂₁, the second pull down resistor R₂₂Composition, the 3rd signal deteching circuit 3 is by the 3rd optocoupler, the 3rd pull-up resistor R₃₁, the 3rd pull down resistor R₃₂Composition, until the n-th signal deteching circuit n is by the n-th optocoupler, the n-th pull-up resistor R_n1, the n-th pull down resistor R_n2Composition, false module circuit A is by the first triode Q₁, the second triode Q₂, the first false module resistance R_o1, the second false module resistance R_o2, phase inverter G composition, power supply V_ccPhotodiode P poles and phototriode C poles, the photodiode P poles of the second optocoupler and phototriode C poles, the photodiode P poles of the 3rd optocoupler and phototriode C poles respectively with the first optocoupler is until photodiode P poles and phototriode C poles, the first triode Q of the n-th optocoupler₁E levels connection, the first pull-up resistor R₁₁Upper end is connected with the phototriode E poles of the first optocoupler, the first pull down resistor R₁₂Lower end is connected to ground, the second pull-up resistor R₂₁Upper end is connected with the phototriode E poles of the second optocoupler, the second pull down resistor R₂₂Lower end is connected to ground, the 3rd pull-up resistor R₃₁Upper end is connected with the phototriode E poles of the 3rd optocoupler, the 3rd pull down resistor R₃₂Lower end is connected to ground, until the n-th pull-up resistor R_n1Upper end is connected with the phototriode E poles of the n-th optocoupler, the n-th pull down resistor R_n2Lower end is connected to ground, the first false module resistance R_o1Upper end and the first triode Q₁C levels connection, the second false module resistance R_o2Lower end and the second triode Q₂C levels connection, the first pull-up resistor R₁₁Lower end and the first pull down resistor R₁₂Upper end junction constitutes the intermediate ends of the first signal deteching circuit 1, the second pull-up resistor R₂₁Lower end and the second pull down resistor R₂₂Upper end junction constitutes the intermediate ends that secondary signal detects circuit 2, the 3rd pull-up resistor R₃₁Lower end and the 3rd pull down resistor R₃₂Upper end junction constitutes the intermediate ends of the 3rd signal deteching circuit 3, until the n-th pull-up resistor R_n1Lower end and the n-th pull down resistor R_n2Upper end junction constitutes the n-th signal deteching circuit n intermediate ends, the first false module resistance R_o1Lower end and the second false module resistance R_o2Upper end junction constitutes false module circuit A intermediate ends, intermediate ends, the secondary signal of first signal deteching circuit 1 detect that the intermediate ends of circuit 2, the intermediate ends of the 3rd signal deteching circuit 3 are connected up to the inverting input of the n-th signal deteching circuit n intermediate ends, false module circuit A intermediate ends and comparator, the first triode Q₁B levels be connected with phase inverter G output ends, the second triode Q₂B levels be connected with phase inverter G inputs, the second triode Q₂E levels be connected to ground；The pulse width signal PULSE1 of first module is received by the photodiode N poles of the first optocoupler, the pulse width signal PULSE2 of second module is received by the photodiode N poles of the second optocoupler, the pulse width signal PULSE3 of 3rd module is received by the photodiode N poles of the 3rd optocoupler, until the pulse width signal PULSEn of the n-th module is received by the photodiode N poles of the n-th optocoupler, false module signal AUX is by phase inverter G inputs and the second triode Q₂B poles receive, middle terminal voltage V_ by comparator inverting input receive, comparison voltage V_refReceived by the in-phase input end of comparator, public pulse width signal PULSE is exported by comparator；First modular power is P₁, pulse width signal weights are Q₁, the second modular power is P₂, pulse width signal weights are Q₂, the 3rd modular power is P₃, pulse width signal weights are Q₃, until the n-th modular power is P_n, pulse width signal weights are Q_n, false module signal AUX weights are 1, and the weights for defining all other module are all higher than or equal to 1, are made

Q₁R₁₁=Q₂R₂₁=Q₃R₃₁=...=Q_nR_n1=R_o1,

Each module is in given time (α T) while starting to send high level pulse signal to interconnection line, each module sends different pulse widths according to respective output current perunit value, signal is changed into low level after end, the trailing edge moment of the pulse signal can just represent the width of the pulse signal, also the output current perunit value of each module can just be represented, the weighted voting of pulse-width signal is actually that the trailing edge of pulse signals is weighted voting：When the weights sum of all pulse width signals is uneven number, false module signal (AUX) is set to high level, false module circuit (A) is added without in flow equalizing circuit, now when all signals are that high level turns off the optocoupler of the first signal deteching circuit to the n-th signal deteching circuit, comparator anti-phase input terminal voltage is V_=0, and homophase input terminal voltage is

The public pulse width signal of comparator output terminal (PULSE) is high level；When the first module pulse width signal (PULSE1) is low level, the first optocoupler is turned on, and disregards optocoupler conduction voltage drop, comparator anti-phase input terminal voltage is

Homophase input terminal voltage is

Work as R₁₂//R₂₂//…//R_n2＞ R₁₁When the public pulse width signal of comparator output terminal (PULSE) be low level, work as R₁₂//R₂₂//…//R_n2＜ R₁₁When the public pulse width signal of comparator output terminal (PULSE) be high level；When the first module pulse width signal (PULSE1) is low level, and the second module pulse width signal (PULSE2) is low level, the first optocoupler and the second optocoupler are turned on, and comparator anti-phase input terminal voltage is

Work as R₁₂//R₂₂//…//R_n2＞ R₁₁//R₂₁When the public pulse width signal of comparator output terminal (PULSE) be low level, work as R₁₂//R₂₂//…//R_n2＜ R₁₁//R₂₁When the public pulse width signal of comparator output terminal (PULSE) be high level, when being less than all pull down resistor parallel values in the corresponding pull-up resistor parallel value of low level pulse width signal, the public pulse width signal of comparator output terminal (PULSE) is low level；The weights sum of all pulse width signals is even number and the power sum of some modules occurs when being just the half of general power, false module signal (AUX) is set to low level, false module circuit (A) is added in flow equalizing circuit, now when all pulse width signals are that high level turns off the optocoupler of the first signal deteching circuit to the n-th signal deteching circuit, comparator anti-phase input terminal voltage is

Homophase input terminal voltage is

Make R₁₂//R₂₂//…//R_n2//R_o2＜ R_o1, the public pulse width signal of comparator output terminal (PULSE) is high level；When the first module pulse width signal (PULSE1) is low level, comparator anti-phase input terminal voltage is

Homophase input terminal voltage is

Work as R₁₂//R₂₂//…//R_n2//R_o2＞ R₁₁//R_o1When the public pulse width signal of comparator output terminal (PULSE) be low level, work as R₁₂//R₂₂//…//R_n2//R_o2＜ R₁₁//R_o1When the public pulse width signal of comparator output terminal (PULSE) be high level, when being less than all pull down resistors and false module second resistance parallel value in the corresponding pull-up resistor of low level pulse width signal and false module first resistor parallel value, the public pulse width signal of comparator output terminal (PULSE) is low level；The time that public pulse width signal (PULSE) is continuously high level represents the average value of each module output current perunit value, and each module carries out output current regulation according to the average value, you can realize the sharing control of each module.

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