CN101601009B - 处理器及在其中执行指令的方法 - Google Patents

处理器及在其中执行指令的方法 Download PDF

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Publication number
CN101601009B
CN101601009B CN200880002977.XA CN200880002977A CN101601009B CN 101601009 B CN101601009 B CN 101601009B CN 200880002977 A CN200880002977 A CN 200880002977A CN 101601009 B CN101601009 B CN 101601009B
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CN
China
Prior art keywords
instruction
instructions
pipeline
flushing
processor
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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CN200880002977.XA
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English (en)
Chinese (zh)
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CN101601009A (zh
Inventor
迈克尔·斯科特·麦克勒瓦伊内
詹姆斯·诺里斯·迪芬德尔费尔
托马斯·安德鲁·萨托里乌斯
罗德尼·韦恩·史密斯
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Qualcomm Inc
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Qualcomm Inc
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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
CN200880002977.XA 2007-01-24 2008-01-24 处理器及在其中执行指令的方法 Expired - Fee Related CN101601009B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/626,443 US7624254B2 (en) 2007-01-24 2007-01-24 Segmented pipeline flushing for mispredicted branches
US11/626,443 2007-01-24
PCT/US2008/051966 WO2008092045A1 (en) 2007-01-24 2008-01-24 Segmented pipeline flushing for mispredicted branches

Publications (2)

Publication Number Publication Date
CN101601009A CN101601009A (zh) 2009-12-09
CN101601009B true CN101601009B (zh) 2015-09-16

Family

ID=39327442

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200880002977.XA Expired - Fee Related CN101601009B (zh) 2007-01-24 2008-01-24 处理器及在其中执行指令的方法

Country Status (10)

Country Link
US (1) US7624254B2 (https=)
EP (1) EP2115572B1 (https=)
JP (4) JP2010517183A (https=)
KR (1) KR101107812B1 (https=)
CN (1) CN101601009B (https=)
BR (1) BRPI0807405A2 (https=)
CA (1) CA2674720C (https=)
MX (1) MX2009007949A (https=)
RU (1) RU2427889C2 (https=)
WO (1) WO2008092045A1 (https=)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7624254B2 (en) * 2007-01-24 2009-11-24 Qualcomm Incorporated Segmented pipeline flushing for mispredicted branches
US9384003B2 (en) * 2007-10-23 2016-07-05 Texas Instruments Incorporated Determining whether a branch instruction is predicted based on a capture range of a second instruction
US7877586B2 (en) * 2008-02-01 2011-01-25 International Business Machines Corporation Branch target address cache selectively applying a delayed hit
US8099586B2 (en) * 2008-12-30 2012-01-17 Oracle America, Inc. Branch misprediction recovery mechanism for microprocessors
US20110320787A1 (en) * 2010-06-28 2011-12-29 Qualcomm Incorporated Indirect Branch Hint
CA2801382C (en) 2010-06-29 2018-12-18 Exxonmobil Upstream Research Company Method and system for parallel simulation models
US8862861B2 (en) 2011-05-13 2014-10-14 Oracle International Corporation Suppressing branch prediction information update by branch instructions in incorrect speculative execution path
US8886920B2 (en) 2011-05-13 2014-11-11 Oracle International Corporation Associating tag to branch instruction to access array storing predicted target addresses for page crossing targets for comparison with resolved address at execution stage
CN102360282A (zh) * 2011-09-26 2012-02-22 杭州中天微系统有限公司 快速处置分支指令预测错误的流水线处理器装置
EP2786905B1 (en) 2011-11-29 2018-10-31 TS Tech Co., Ltd. Mounting member, and airbag module-equipped seat
US9268569B2 (en) * 2012-02-24 2016-02-23 Apple Inc. Branch misprediction behavior suppression on zero predicate branch mispredict
CN105164637B (zh) * 2013-05-30 2017-12-19 英特尔公司 用于执行循环的方法、系统、装置和处理器以及机器可读介质
US9792252B2 (en) 2013-05-31 2017-10-17 Microsoft Technology Licensing, Llc Incorporating a spatial array into one or more programmable processor cores
US10409606B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Verifying branch targets
US10191747B2 (en) 2015-06-26 2019-01-29 Microsoft Technology Licensing, Llc Locking operand values for groups of instructions executed atomically
US9946548B2 (en) 2015-06-26 2018-04-17 Microsoft Technology Licensing, Llc Age-based management of instruction blocks in a processor instruction window
US10409599B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Decoding information about a group of instructions including a size of the group of instructions
US10175988B2 (en) 2015-06-26 2019-01-08 Microsoft Technology Licensing, Llc Explicit instruction scheduler state information for a processor
US9952867B2 (en) 2015-06-26 2018-04-24 Microsoft Technology Licensing, Llc Mapping instruction blocks based on block size
US9720693B2 (en) 2015-06-26 2017-08-01 Microsoft Technology Licensing, Llc Bulk allocation of instruction blocks to a processor instruction window
US10169044B2 (en) 2015-06-26 2019-01-01 Microsoft Technology Licensing, Llc Processing an encoding format field to interpret header information regarding a group of instructions
US10346168B2 (en) 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
US10255074B2 (en) 2015-09-11 2019-04-09 Qualcomm Incorporated Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved target address, in response to a precise interrupt
CN121300858A (zh) * 2025-09-02 2026-01-09 北京微核芯科技有限公司 分支指令预测方法、装置和设备

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5586278A (en) * 1994-03-01 1996-12-17 Intel Corporation Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor
US5627985A (en) * 1994-01-04 1997-05-06 Intel Corporation Speculative and committed resource files in an out-of-order processor

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1300471A1 (ru) * 1985-11-01 1987-03-30 Предприятие П/Я Г-4677 Устройство дл выполнени условных переходов в конвейерном процессоре
US5694564A (en) * 1993-01-04 1997-12-02 Motorola, Inc. Data processing system a method for performing register renaming having back-up capability
EP0649086B1 (en) 1993-10-18 2000-07-19 National Semiconductor Corporation Microprocessor with speculative execution
ES2138051T3 (es) * 1994-01-03 2000-01-01 Intel Corp Metodo y aparato para la realizacion de un sistema de resolucion de bifurcaciones en cuatro etapas en un procesador informatico.
US7496734B1 (en) * 2000-04-28 2009-02-24 Stmicroelectronics, Inc. System and method for handling register dependency in a stack-based pipelined processor
JP3667703B2 (ja) * 2002-03-18 2005-07-06 エヌイーシーコンピュータテクノ株式会社 エラー訂正制御回路
US7152155B2 (en) * 2005-02-18 2006-12-19 Qualcomm Incorporated System and method of correcting a branch misprediction
US7624254B2 (en) * 2007-01-24 2009-11-24 Qualcomm Incorporated Segmented pipeline flushing for mispredicted branches

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5627985A (en) * 1994-01-04 1997-05-06 Intel Corporation Speculative and committed resource files in an out-of-order processor
US5586278A (en) * 1994-03-01 1996-12-17 Intel Corporation Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor

Also Published As

Publication number Publication date
US20080177992A1 (en) 2008-07-24
JP6370829B2 (ja) 2018-08-08
WO2008092045A1 (en) 2008-07-31
JP6208084B2 (ja) 2017-10-04
CA2674720A1 (en) 2008-07-31
CN101601009A (zh) 2009-12-09
JP2016167284A (ja) 2016-09-15
CA2674720C (en) 2015-02-03
KR101107812B1 (ko) 2012-01-25
MX2009007949A (es) 2009-08-07
JP2014211881A (ja) 2014-11-13
US7624254B2 (en) 2009-11-24
JP2012230687A (ja) 2012-11-22
RU2427889C2 (ru) 2011-08-27
EP2115572B1 (en) 2015-03-11
RU2009131712A (ru) 2011-02-27
JP5866259B2 (ja) 2016-02-17
BRPI0807405A2 (pt) 2014-07-08
KR20090102871A (ko) 2009-09-30
EP2115572A1 (en) 2009-11-11
JP2010517183A (ja) 2010-05-20

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Granted publication date: 20150916

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