CN101593503A - The testing circuit of display power supply management - Google Patents
The testing circuit of display power supply management Download PDFInfo
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- CN101593503A CN101593503A CNA2008101084719A CN200810108471A CN101593503A CN 101593503 A CN101593503 A CN 101593503A CN A2008101084719 A CNA2008101084719 A CN A2008101084719A CN 200810108471 A CN200810108471 A CN 200810108471A CN 101593503 A CN101593503 A CN 101593503A
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Abstract
A kind of testing circuit that is used for the display power supply management comprises row, field sync signal, row, a clamping circuit, integral filter circuit, ON-OFF control circuit, detection signal.This testing circuit is by detecting row, field synchronization input signal, and it can not use under display monitor a period of time cycle situation, automatically notifies display monitor that electric source modes is switched to the power-off energy saver mode, thus minimizing power dissipation; And will use display monitor the time, can automatically notify to allow display monitor be in normal full speed operation pattern.Circuit design of the present invention all adopts resolution element, relies on the special semiconductor IC integrated circuit to compare with adopting, and this circuit design is simple and reliable, and is portable high, highly versatile, and also cost is low.
Description
Technical field
The invention belongs to the display monitor technical field, matrix ground is said, relate to a kind of signal deteching circuit that is used for display monitor, it can not use under display monitor a period of time cycle situation, automatically notify display monitor that electric source modes is switched to the power-off energy saver mode, thus minimizing power dissipation; And will use display monitor the time, can automatically notify to allow display monitor be in normal full speed operation pattern.
Background technology
Usually, in a period of time, there is not signal to be input to display monitor, the electric source modes of the power circuit display monitor in the display monitor automatically switches to the power supply save mode, up to signal input is normally arranged, thereby just saved unnecessary power consumption, reduce its power consumption, to reach the purpose of energy savings.Has this function mostly at currently marketed display monitor.
EPA has issued " Energy Star " sign television technologies standard (ENERGY
ProgramRequirements for Televisions Eligibility Criteria).When multi-functional, hd-tv program is provided for consumers in general, the purpose that save the energy to reach, reduces greenhouse gas emission.The holding state (Standby Mode) of display monitor product and the energy consumption limit value of hanging up under (suspend) are less than 1W.VESA (Video ElectronicsStandard Association, VESA) formulated a special energy conservation criteria-DPMS (Display Power Management Signaling, display power management sig-maling) at display monitor.DPMS has defined standby (standby) and has hung up (suspend) two kinds of power save modes, this just requires when not having signal to be input to display monitor, and the signal deteching circuit in the display monitor wants fast, accurately to notify central processing unit to start the power supply save mode.Traditional way is to adopt the integrated signal deteching circuit function of special semiconductor IC, and finishes input.Limit the dirigibility that semiconducter IC is selected for use so greatly, and increased cost.
Purpose of the present invention just is to overcome above-mentioned shortcoming and defect, and a kind of simple in structure concentrating is provided, and adopts resolution element to finish the design proposal of display power supply supervisory signal testing circuit.
Summary of the invention
In order to overcome in the prior art, the display power supply supervisory signal testing circuit in the display monitor adopts the integrated signal deteching circuit of dedicated semiconductor, and signal deteching circuit is portable poor, limitation such as versatility difference.
In order to solve the problems of the technologies described above, the present invention is achieved by the following technical programs:
A kind of testing circuit of display power supply management is the capable synchronous input signal at display monitor, and the field synchronization input signal carries out testing circuit.DPMS has clearly stipulated four kinds of duties of display monitor: start (on) state, standby (standby), hang-up (suspend) and shutdown (off) state.Under normal boot-strap (on) state, video card is exported row, field scan signal simultaneously, and display monitor is capable, the equal operate as normal of field-scanning circuit, and display monitor is operated in full-speed state; Under standby (standby) state, video card stops to export line synchronizing signal, and field sync signal continues output simultaneously, line-scan circuit quits work in the display, but field sync signal works on, and is in the blank screen state though display monitor enters energy saver mode, can be waken up by moment; Under (suspend) state of hang-up, video card continues the output line synchronizing signal, stops the output of field scan signal simultaneously, line-scan circuit works in the display, but field sync signal quits work, and is in the blank screen state though display monitor enters energy saver mode, can be waken up by moment; Under shutdown (off) state, video card stops row, field scan signal output simultaneously, and display monitor is capable, field-scanning circuit all quits work, and this rises under the state has only power supply to keep work, power consumption seldom, but wakeup time is also longer.The testing circuit of display power supply of the present invention management at above four kinds of duties can be fast, accurately detect, when being in power save mode, this testing circuit feeds back to the central processing unit of display monitor fast, makes display monitor enter energy saver mode; When normal signal was imported, this testing circuit fed back to the central processing unit of display monitor fast, wakes up to normal mode of operation by energy saver mode, makes the display monitor full speed operation.
The testing circuit of above-mentioned display power supply management, respectively to row synchronously and the pulse signal of the square wave of field sync signal carry out the signal clamper and be converted to dc level signal, again dc level signal is carried out integral filtering, this dc level signal can be controlled ON-OFF control circuit at last, through the level state of ON-OFF control circuit output, the present duty of central processing unit of notice display monitor.If the level of ON-OFF control circuit output is a high level state, the expression signal of input at present is in the normal boot-strap state, and central processing unit starts the full speed operation circuit, allows display monitor be in normal full speed operation pattern; If the level of ON-OFF control circuit output is a low level state, the expression signal of input at present is in power save mode, and central processing unit starts energy-saving control circuit, allows display monitor work be in energy saver mode.
Compared with prior art, advantage of the present invention and good effect are: this circuit design is simple and reliable, and is portable high, highly versatile, and cost is low.Remedied traditional DMPS testing circuit and can only rely on the special semiconductor IC integrated circuit, the line design very flexible has bigger limitation.
Description of drawings
Fig. 1 is the matrix calcspar of the testing circuit of display power supply management of the present invention.
Fig. 2 is the circuit diagram of an embodiment of the testing circuit of display power supply of the present invention management.
The matrix embodiment
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Fig. 1 is the matrix calcspar of the testing circuit of display power supply management of the present invention.The line synchronizing signal input is converted to dc level signal through space clamping circuit 130,140 pairs of dc level signals of integral filter circuit carry out integral filtering, this dc level signal can advance control to ON-OFF control circuit 150 at last, and the level of exporting through ON-OFF control circuit 150 is a detection signal; Field sync signal input simultaneously is converted to dc level signal through interlude clamping circuit 100,110 pairs of dc level signals of integral filter circuit carry out integral filtering, this dc level signal can be controlled ON-OFF control circuit 120 at last, is to link together through the detection signal of ON-OFF control circuit 120 outputs and the detection signal of ON-OFF control circuit 150 outputs.If the level of detection signal is a high level state, the expression signal of input at present is in the normal boot-strap state, and central processing unit starts the full speed operation circuit, allows display monitor be in normal full speed operation pattern; If the level of detection signal is a low level state, the expression signal of input at present is in power save mode, and central processing unit starts energy-saving control circuit, allows display monitor work be in energy saver mode.
Fig. 2 is the circuit diagram of an embodiment of the testing circuit of display power supply of the present invention management.Four kinds of duties at display monitor DPMS: start (on) state, standby (standby), hang-up (suspend) and shutdown (off) state.Below at these four kinds of duties, the testing circuit of display power supply of the present invention management is elaborated.
Display monitor is under normal boot-strap (on) state, video card is exported row, field scan square-wave signal simultaneously, the field synchronization square-wave signal, C101 through interlude clamping circuit 200 discharges and recharges, and by after the unidirectional conducting of D101, carry out filtering by integral filter circuit 210 R101 and C103 again, produce the base stage that stable direct current high level removes gauge tap control circuit 220 PNP pipe Q101, because the base stage of PNP Q101 is a high voltage, Q101 ends, and makes that the detection pin SYNC_DETECT of central processing unit is a high level; The row synchronous square-wave signal, C102 through space clamping circuit 230 discharges and recharges, after D102 signal clamper, carry out filtering by integral filter circuit 240 R102 and C104 again, produce stable direct current high level and go gauge tap control circuit 250PNP pipe Q102 base stage, because the base stage of PNP Q102 is a high voltage, Q102 ends, and makes that the detection pin SYNC_DETECT of central processing unit is a high level; So under normal boot-strap (on) state, SYNC_DETECT keeps high level.
Display monitor is under standby (standby) state, and video card stops to export line synchronizing signal, and field sync signal continues output simultaneously.The field synchronization square-wave signal, C101 through interlude clamping circuit 200 discharges and recharges, and by after the unidirectional conducting of D101, carry out filtering by integral filter circuit 210 again, produce the base stage that stable direct current high level removes gauge tap control circuit 220 PNP pipe Q101, because the base stage of PNP Q101 is a high voltage, Q101 ends, and makes that the detection pin SYNC_DETECT of central processing unit is a high level; But, because the row synchronous square-wave signal stops output, C102 and D102 through space clamping circuit 230 keep low level, keep low level output through integral filter circuit 240 backs, because the PNP Q102 base stage of ON-OFF control circuit 250 is a low level, the Q102 conducting makes SYNC_DETECT conducting over the ground.So under the standby (standby), SYNCDETECT keeps low level.
Display monitor is under (suspend) state of hang-up, video card continues the output line synchronizing signal, stop the output of field scan signal simultaneously, the row synchronous square-wave signal, C102 through space clamping circuit 230 discharges and recharges, after D102 signal clamper, carry out filtering by integral filter circuit 240 R102 and C104 again, produce stable direct current high level and go gauge tap control circuit 250PNP pipe Q102 base stage, because the base stage of PNP Q102 is a high voltage, Q102 ends, and makes that the detection pin SYNC_DETECT of central processing unit is a high level; But the field synchronization square-wave signal stops output, keeps low level through interlude clamping circuit 200 C101 and D101, keep low level through integral filter circuit 210, because the base stage of ON-OFF control circuit 220 PNP Q101 is a low level, the Q101 conducting makes SYNC_DETECT conducting over the ground.So under the standby (standby), SYNC_DETECT keeps low level.
Display monitor is under shutdown (off) state, video card stops row, the output of field scan signal simultaneously, because the row synchronous square-wave signal stops output, keep low level through space clamping circuit 230 C102 and D102, and by behind integral filter circuit 240 R102 and the C104, keep low level, because the base stage of PNP Q102 is a low level, the Q102 conducting makes SYNC_DETECT conducting over the ground.The field synchronization square-wave signal stops output, and clamping circuit 200 C101 and D101 keep low level through interlude, keeps low levels through integral filter circuit 210, because the base stage of PNP Q101 is a low level, the Q101 conducting makes SYNCDETECT conducting over the ground.So under the shutdown (off), SYNC_DETECT keeps low level.
In sum, this display power supply management testing circuit is at the start (on) of DPMS, standby (standby), hang-up (suspend) and shutdown (off) four kinds of state-detection situations are: when display monitor is in normal boot-strap (on) state, OK, the field scan signal is normally imported, through this display power supply management testing circuit, obtain SYNC_DETECT and keep high level, SYNC_DETECT links to each other with the detection pin of central processor CPU, it is high level that central processor CPU detects SYNC_DETECT, start display monitor and be operated in the full speed operation pattern, satisfy the requirement that the user uses.When display monitor is in standby (standby) state, hang-up (suspend) state or shutdown (off) state respectively, row, field scan signal are through this display power supply management testing circuit, obtain SYNC_DETECT and keep low level, because SYNC_DETECT links to each other with the detection pin of central processor CPU, it is low level that central processor CPU detects SYNC_DETECT, start display monitor and be operated in the energy conservation pattern, thus minimizing power dissipation.
Claims (4)
1. the testing circuit of display power supply management, comprise line of input, field sync signal, row, a clamping circuit, integral filter circuit, ON-OFF control circuit, detection signal is characterized in that: the input termination line synchronizing signal of described capable clamping circuit, and the output terminal of row clamping circuit connects integral filter circuit; The input termination field sync signal of field clamping circuit, the output terminal of a clamping circuit connects integral filter circuit; The input end of described ON-OFF control circuit is to connect the integral filter circuit signal, and output terminal is a detection signal.
2. according to the testing circuit of claims 1 described display power supply management, it is characterized in that: described capable clamping circuit, a clamping circuit constitute realization by capacitor and the series connection of Schottky duodiode respectively.
3. according to the testing circuit of claims 1 described display power supply management, it is characterized in that: described ON-OFF control circuit can adopt the PNP transistor, NPN transistor, and field effect transistor, integrated circuit is realized.
4. according to the testing circuit of claims 1 described display power supply management, it is characterized in that: described detection signal is low-voltage high level and zero level two states.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101084719A CN101593503A (en) | 2008-05-31 | 2008-05-31 | The testing circuit of display power supply management |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101084719A CN101593503A (en) | 2008-05-31 | 2008-05-31 | The testing circuit of display power supply management |
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| CN101593503A true CN101593503A (en) | 2009-12-02 |
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| CNA2008101084719A Pending CN101593503A (en) | 2008-05-31 | 2008-05-31 | The testing circuit of display power supply management |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108831407A (en) * | 2018-06-26 | 2018-11-16 | 苏州佳世达电通有限公司 | Display controller and its power-economizing method and display device |
| CN112087583A (en) * | 2020-09-16 | 2020-12-15 | 深圳Tcl新技术有限公司 | Display method, display device, multimedia equipment and storage medium |
-
2008
- 2008-05-31 CN CNA2008101084719A patent/CN101593503A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108831407A (en) * | 2018-06-26 | 2018-11-16 | 苏州佳世达电通有限公司 | Display controller and its power-economizing method and display device |
| CN112087583A (en) * | 2020-09-16 | 2020-12-15 | 深圳Tcl新技术有限公司 | Display method, display device, multimedia equipment and storage medium |
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Open date: 20091202 |