CN101588192B - Method and device for confirming coarse synchronizing of downlink pilot - Google Patents

Method and device for confirming coarse synchronizing of downlink pilot Download PDF

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CN101588192B
CN101588192B CN2009100781842A CN200910078184A CN101588192B CN 101588192 B CN101588192 B CN 101588192B CN 2009100781842 A CN2009100781842 A CN 2009100781842A CN 200910078184 A CN200910078184 A CN 200910078184A CN 101588192 B CN101588192 B CN 101588192B
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window
length
power ratio
chips
performance number
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CN101588192A (en
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许百成
刘俊英
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Beijing T3G Technology Co Ltd
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Beijing T3G Technology Co Ltd
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Abstract

The present invention provides a method and a device for confirming the coarse synchronizing of the downlink pilot and belongs to the field of wireless communication technology. The method of the invention comprises the following steps: firstly after adding the power value of a first guard interval with the power value of a second guard interval, dividing the obtained value with the power value ofthe SYNC-DL for obtaining a first power ratio; determining whether the first power ratio is less than a first preset threshold value, if it is, confirming the received data window as the characterist ic window; then obtaining the SNYC-DL with the length of 64 codes in the characteristic window, searching out the maximum energy window and the minimum energy window which have the length of W-shift codes; dividing the maximum energy window with the minimum energy window for obtaining a second power ratio; and determining whether the second power ratio is larger than a second preset threshold value, and if it is, the position of SNYC-DL can be confirmed to the position of the coarse synchronizing of the downlink pilot. The accuracy of the coarse synchronizing can be effectively increased.

Description

Be used for determining method and the device of coarse synchronizing of downlink pilot
Technical field
The invention belongs to wireless communication technology field, relate in particular to a kind of method and device for determining coarse synchronizing of downlink pilot.
Background technology
TD-SCDMA (Time Division-Synchronous Code Division Multiple Access, the CDMA (Code Division Multiple Access) that time-division is synchronous) one of system core technology is exactly synchronization CDMA (Code DivisionMultiple Access, code division multiple access), refer to that namely each terminal signaling of up link is at the base-station demodulator Complete Synchronization.For realizing synchronization CDMA, synchronously detection has just become wherein one of key technology.Synchronously detection is divided into thick synchronous and smart synchronous, synchronous the catching of thick synchronously finger, i.e. and the search of settling signal place frequency range and definite DwPTS (descending pilot frequency time slot) are synchronously thick; Smart synchronous tracking, the i.e. definite system-frame sync bit of referring to synchronously.On the spectrum allocation may of ITU (International Telecommunications Union), the TD-SCDMA system assignment 1880MHz-1920MHz and two wavelength coverages of 2010MHz-2025MHz.
How can catch fast and effectively the useful signal frequency range and determine that DwPTS slightly is that the TD-SCDMA phylogenetic relationship is to the key component of communication speed and quality synchronously.Generally, fairly simple and generally acknowledged definite coarse synchronization method is the position of determining signal frequency range and DwPTS according to the DwPTS special construction.Referring to Fig. 1, be the frame structure of TD-SCDMA system, wherein the DwPTS structure is that the protection interval (GP) of 32chips (chip) adds that length is that the synchronous code of 64chips consists of by length; The protection interval of then between DwPTS and UpPTS (uplink pilot time slot), having inserted 96chips.Because the power of the GP that receives is very little, and SYNC (synchronously) code segment data is with full power transmissions, so from the time analysis that distributes, the power of SYNC is compared with both sides GP, the SYNC section is " peak " value.When with the power of both sides 64 chips and (each 32 chip of every limit) divided by SYNC section power and the time, the value that obtains can be very little.With the slide Window of this length of variable step size, the position that the Window of ratio minimum is corresponding is the thick sync bit of DwPTS to receiver in receiving data stream.
But in practical communication system, because causing, a variety of causes such as leakage of terminal radio frequency device energy do not having this Window can to occur on the frequency of signal yet, if use traditional Window algorithm can cause slightly being synchronized on the frequency range that does not have signal, make synchronous search time long even can't resident frequency to signal is arranged.
Summary of the invention
In order to address the above problem, the purpose of this invention is to provide a kind of method and device for determining coarse synchronizing of downlink pilot, can the thick synchronous accuracy of Effective Raise.
In order to achieve the above object, the invention provides a kind of method for determining coarse synchronizing of downlink pilot, described method comprises:
In length was the receive data window of 128 chips, performance number, the length of obtaining respectively length and be the first protection interval of 32 chips was the performance number at the second protection interval of 32 chips and the performance number of the descending synchronous code sequence SYNC-DL that length is 64 chips;
With described first the protection interval performance number and described second the protection interval the performance number addition after, again divided by the performance number of described SYNC-DL, obtain the first power ratio;
Whether judge described the first power ratio less than the first predetermined threshold, if determine that described receive data window is Window;
Obtain that length is the SNYC-DL of 64 chips in the described Window, searching out length in described SNYC-DL is the ceiling capacity window of W-shift chip and the least energy window that length is the W-shift chip, and wherein W-shift is variable energy window length;
Described least energy window divided by described ceiling capacity window, is obtained the second power ratio;
Whether judge described the second power ratio greater than the second predetermined threshold, if determine that described length is that the position of the SNYC-DL of 48 chips is the position of coarse synchronizing of downlink pilot.
Preferably, described method also comprises:
Obtain a plurality of the first power ratio, wherein the number of the first power ratio calculates by formula M=(N-W)/S+1, and M is the number of the first power ratio, and N is for receiving the length of signal, and W is characteristic length, and S is moving step length.
Preferably, whether described the first power ratio is specially less than the step of the first predetermined threshold:
In M the first power ratio, filter out the first minimum power ratio;
The first power ratio and first predetermined threshold of described minimum are compared.
Preferably, if described the first power ratio more than or equal to described the first predetermined threshold, described method also comprises:
Skip the back validation checking, directly report synchronization failure.
The present invention also provides a kind of device for determining coarse synchronizing of downlink pilot, and described device comprises characteristic window detector and Window the validity judge device, wherein
Described Window detector, be used in length is the receive data window of 128 chip, performance number and the length that calculates length and be the first protection protection interval of 32 chips be 32 chips the second protection interval performance number with, obtain the 3rd performance number, be the performance number of the descending synchronous code sequence SYNC-DL of 64 chips divided by length with described the 3rd performance number, obtain the first power ratio, if described the first power ratio during less than the first predetermined threshold, determines that described receive data window is Window;
Described Window the validity judge device, the SNYC-DL that the described Window intercepted length that is used for determining at described Window detector is 64 chips, in described SNYC-DL, search out long for the ceiling capacity window of W-shift chip and length be the least energy window of W-shift chip, and with described least energy window divided by the ceiling capacity window, obtain the second power ratio, if described the second power ratio is during greater than the second predetermined threshold, determine that described length is that the position of the SNYC-DL of 64 chips is the position of coarse synchronizing of downlink pilot, wherein W-shift is variable energy window length.
Preferably, described characteristic window detector comprises:
The first acquisition module, be used in length is the receive data window of 128 chips, performance number, the length of obtaining respectively length and be the first protection interval of 32 chips is the performance number at the second protection interval of 32 chips and the performance number of the descending synchronous code sequence SYNC-DL that length is 64 chips;
The first computing module after the performance number and described second at described the first protection interval is protected the performance number addition at interval, again divided by the performance number of described SYNC-DL, obtains the first power ratio;
The first processing module is used for whether judging described the first power ratio less than the first predetermined threshold, if determine that described receive data window is Window.
Preferably, described Window the validity judge device comprises:
The second acquisition module is used for obtaining described Window length the SNYC-DL that is 64 chips, and searching out length in described SNYC-DL is the ceiling capacity window of W-shift chip and the least energy window that length is the W-shift chip;
The second computing module is used for described least energy window obtaining the second power ratio divided by described ceiling capacity window;
The second processing module is used for whether judging described the second power ratio greater than the second predetermined threshold, if described length is that the position of the SNYC-DL of 64 chips is the position of coarse synchronizing of downlink pilot.
Preferably, described the first computing module is used for obtaining a plurality of the first power ratio, and wherein the number of the first power ratio calculates by formula M=(N-W)/S+1, M is the number of the first power ratio, N is for receiving the length of signal, and W is characteristic length, and S is moving step length.
Preferably, described the first processing module is used for filtering out the first minimum power ratio M the first power ratio, if the first power ratio of described minimum during less than the first predetermined threshold, determines that described receive data window is Window; If the first power ratio of described minimum during more than or equal to the first predetermined threshold, directly reports synchronization failure.
At least one technical scheme has following beneficial effect in the technique scheme: by at first detecting the DwPTS Window according to traditional characteristic window method, then whether the envelope of detected characteristics window satisfies condition, thereby can avoid causing in the problem that does not have also can occur on the frequency of signal Window because of a variety of causes such as leakage of terminal radio frequency device energy, and can save the time of synchronous search, thereby but the thick synchronous performance of Effective Raise.
Description of drawings
Fig. 1 is the frame structure schematic diagram of TD-SCDMA system;
Fig. 2 is the structural representation of DwPTS;
Fig. 3 is the method flow diagram that is used for determining coarse synchronizing of downlink pilot in the embodiments of the invention;
Fig. 4 is the device block diagram that is used for determining coarse synchronizing of downlink pilot in the embodiments of the invention.
Embodiment
Present embodiment is only with the example that is applied as in the terminal use (UE) of TD SDMA (TD-SCDMA) system.Although present embodiment also can be used in other field of wireless communications systems only take the TD-SCDMA system as example.In the TD-SCDMA system, in UE when start, only have frame structure information not reach frame synchronization with signal, and receiver must keep with the frame structure of data flow just communicating synchronously, so must set up first the down-going synchronous with the residential quarter.
For can be clearer the process of data input and data output in the explanation TD-SCDMA system, now the frame structure of TD-SCDMA is done and is described.As shown in Figure 2, TD-SCDMA is the chronomere take 10ms (millisecond) as a frame.TD-SCDMA is owing to use intelligent antenna technology, need the at any time position of (for example every 5ms) grasp user terminal, therefore TD-SCDMA further can be divided into each frame the subframe of two 5ms, thereby can shorten the time in each time up-downgoing cycle, make it possible within the as far as possible short time, finish the location to the user.The subframe of each 5ms is divided into 7 common time slots, and (TS0～TS6) and 3 special time slots, wherein 3 special time slots are respectively: descending pilot frequency time slot (DwPTS), uplink pilot time slot (UpPTS) and protection period (GP).The subframe of each 5ms is comprised of 6400 chips (chips) altogether.In TD-SCDMA, the DwPTS in each subframe is descending pilot frequency and designing synchronously.
As shown in Figure 2; structure chart for DwPTS; by among the figure as can be known; DwPTS is that the descending synchronous code (SYNC) of 64 chips (chip) and the protection period (GP) of 32 chips (chip) form by length; wherein SYCN is one group of pseudo noise code (PN); can distribute to different residential quarters, be used for the residential quarter search and descending synchronously.
When UE starts shooting, at first to determine the subdistrict position at the place of UE, then the data of reception reach the sync bit of chip level synchronously at first by the approximate location of thick synchronously search DwPTS according to essence.Only pay close attention in the present embodiment synchronously thick, the approximate location of utilizing the power " Window " of the DwPTS of down link to search for SYNC by terminal.As shown in Figure 1, in the frame structure of TD-CDMA, SYNC-DL code section is 64 chips, and there is the GP of 32 chips on the left side, and there is the GP of 96 chips on the right.
For the purpose, technical scheme and the advantage that make the embodiment of the invention is clearer, below in conjunction with embodiment and accompanying drawing, the embodiment of the invention is done in further detail explanation.At this, illustrative examples of the present invention and explanation are used for explanation the present invention, but not as a limitation of the invention.
As shown in Figure 3, for being used for determining the method flow diagram of coarse synchronizing of downlink pilot in the embodiments of the invention, concrete steps are as follows:
Step 301, to obtain length in the receive data window respectively be that performance number, the length at the first protection interval of 32 chips is the performance number at the second protection interval of 32 chips and the performance number of the descending synchronous code sequence SYNC-DL that length is 64 chips;
Namely, it is that the signal of N (unit is chip) obtains the input signal power value by power calculation (for example square adding the method for signal imaginary part square by the signal real part) that terminal at first will receive length, then resulting signal power value is carried out Window and detects.Suppose that Window length is W (unit is chip), the Window of this length can move in the scope of whole related power value, and mobile step-length is variable (for example can choose according to operand and system requirements).
If take Window length as W=128, moving step length S is that 2 chips are example, by M the Window that formula M=(N-W)/S+1 can calculate.Suppose (1≤i≤M), calculate at first respectively the protection interval power of the 32chips on the SYNC-DL left side in i Window P left _ i = Σ j = 0 31 P left _ i , j (i.e. the performance number at the first protection interval), wherein i represents i Window, j represents j chip in i the Window; Calculate the 32chips protection interval power on SYNC-DL the right P right _ i = Σ j = 0 31 P right _ i , j (i.e. the performance number at the second protection interval), wherein i represents i Window, j represents j chip in i the Window; Calculating length is the SYNC-DL performance number of 64chips P sync _ i = Σ j = 0 63 P sync _ i , j , Wherein i represents i Window, and j represents j chip in i the Window;
Step 302, with first the protection interval performance number and second the protection interval the performance number addition after, again divided by the performance number of SYNC-DL, obtain the first power ratio;
In this step, can be according to formula λ i=(P Left_i+ P Right_i)/P Sync_iCalculate the first power ratio, and according to M the Window that obtains in the step 301, can obtain M first power ratio λ by step 302 this moment i
Step 303, whether judge the first power ratio less than the first predetermined threshold, if, execution in step 304; Otherwise, execution in step 309;
In M the first power ratio, filter out the first minimum power ratio λ Min(λ Min=Min (λ 1..., λ M)), the first power ratio λ that then should minimum MinWith the first predetermined threshold value λ TCompare, if the first power ratio λ MinLess than the first predetermined threshold λ T, then this receive data window is Window, otherwise expression can't be found sync bit, skips the back validation checking, directly reports synchronization failure.Choosing of above-mentioned the first predetermined threshold can have relation with Signal-to-Noise.For example can by a large amount of emulation, then scan this first predetermined threshold according to the system signal noise ratio demand.
Step 304, determine that this receive data window is Window;
In the present embodiment, the protection interval of two 32chips among Fig. 2 and the synchronous code of 64chips can be defined as Window, this moment, window length was 128chips.And above-mentioned steps 301～304 can realize by the Window detector.
Step 305, obtain that length is the SNYC-DL of 48 chips in the Window, and in length is the SNYC-DL of 64 chips, search out ceiling capacity window that length is W-shift (take W_shift=32 as example) chip and length and be the least energy window of W_shift (take W_shift=32 as example) chip;
Terminal is input to definite result of step 304 in the Window the validity judge device, this Window the validity judge device is in Window, power according to SYNC-DL is judged validity, in the present embodiment decision rule can be set to: the power of 64chips in the middle of the intercepting SYNC-DL, the window that with length is W_shift=32 slides take 1chip as unit, obtain successively 33 groups of performance numbers ( W 0 = Σ j = 0 32 P sync _ i , j , W k=W K-1+ P Sync_i, k+32-P Sync_i, k-1, k=1 ..., 32), from 33 groups of performance numbers, search out ceiling capacity window MaxW=max (W 0..., W 32) and least energy window MinW=min (W 0..., W 32);
Step 306, with this least energy window divided by the ceiling capacity window, obtain the second power ratio;
Namely utilize formula Ratio=MinW/MaxW to calculate the second power ratio;
Step 307, whether judge the second power ratio greater than the second predetermined threshold, if execution in step 308, otherwise execution in step 309;
The the second power ratio Ratio that namely calculates and the second predetermined threshold Ratio TCompare, if the second power ratio Ratio is greater than the second predetermined threshold Ratio TThe time, i.e. Ratio＞Ratio T, then this Window is effective, and the position of this SYNC-DL is the thick sync bit of detection, otherwise invalid, reports synchronization failure.In the present embodiment, this second threshold value choose relevant with the flatness of the envelope of sync.By emulation and testing setup threshold value.
Step 308, determine that length is that the position of the SNYC-DL of 64 chips is the position of coarse synchronizing of downlink pilot;
If when step 309 the second power ratio is equal to or less than the second predetermined threshold, can report synchronization failure.
As shown from the above technical solution, by at first detecting the DwPTS Window according to traditional characteristic window method, then whether the envelope of detected characteristics window satisfies condition, thus but the thick synchronous performance of Effective Raise.
In order to realize above-mentioned embodiment of the method, other embodiment of the present invention also provide a kind of device for determining coarse synchronizing of downlink pilot.What need in addition at first explanation is; because following embodiment is for realizing aforesaid embodiment of the method; so this device all is to establish for each step that realizes preceding method; but the present invention is not limited to following embodiment, and any device of said method of realizing all should be contained in protection scope of the present invention.And in the following description, the content identical with preceding method omitted at this, to save length.
As shown in Figure 4, for being used for determining the device of coarse synchronizing of downlink pilot in the embodiments of the invention, this device comprises: characteristic window detector 41 and Window the validity judge device 42, wherein
Window detector 41, be used in length is the receive data window of 128 chip, performance number and the length that calculates length and be the first protection protection interval of 32 chips be 32 chips the second protection interval performance number with, obtain the 3rd performance number, be the performance number of the descending synchronous code sequence SYNC-DL of 64 chips divided by length with the 3rd performance number, described the first power ratio obtains the first power ratio, if during less than the first predetermined threshold, can determine that described receive data window is Window;
Window the validity judge device 42, the SNYC-DL that the described Window intercepted length that is used for determining at described Window detector is 64 chips, in described SNYC-DL, search out the long ceiling capacity window of W_shift (take 32 as example) chip and the length least energy window as W_shift (take 32 as example) chip that is, and with described least energy window divided by the ceiling capacity window, obtain the second power ratio, if it is that the position of the SNYC-DL of 64 chips is the position of coarse synchronizing of downlink pilot that described the second power ratio during greater than the second predetermined threshold, is determined described length.
In another embodiment of the present invention, above-mentioned characteristic window detector 41 comprises:
The first acquisition module, be used in length is the receive data window of 128 chips, performance number, the length of obtaining respectively length and be the first protection interval of 32 chips is the performance number at the second protection interval of 32 chips and the performance number of the descending synchronous code sequence SYNC-DL that length is 64 chips;
The first computing module after the performance number and described second at described the first protection interval is protected the performance number addition at interval, again divided by the performance number of described SYNC-DL, obtains the first power ratio;
The first processing module is used for whether judging described the first power ratio less than the first predetermined threshold, if determine that described receive data window is Window.
In another embodiment of the present invention, above-mentioned Window the validity judge device 42 comprises:
The second acquisition module, be used for obtaining described Window length the SNYC-DL that is 64 chips, in described SNYC-DL, search out length and be the ceiling capacity window of W_shift (take 32 as example) chip and length and be the least energy window of W_shift (take 32 as example) chip;
The second computing module is used for described least energy window obtaining the second power ratio divided by described ceiling capacity window;
The second processing module is used for whether judging described the second power ratio greater than the second predetermined threshold, if described length is that the position of the SNYC-DL of 64 chips is the position of coarse synchronizing of downlink pilot.
As shown from the above technical solution, by at first detecting the DwPTS Window according to traditional characteristic window method, then whether the envelope of detected characteristics window satisfies condition, thereby can avoid causing in the problem that does not have also can occur on the frequency of signal Window because of a variety of causes such as leakage of terminal radio frequency device energy, and can save the time of synchronous search, thereby but the thick synchronous performance of Effective Raise.
The above only is preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (9)

1. method of be used for determining coarse synchronizing of downlink pilot is characterized in that described method comprises:
In length was the receive data window of 128 chips, performance number, the length of obtaining respectively length and be the first protection interval of 32 chips was the performance number at the second protection interval of 32 chips and the performance number of the descending synchronous code sequence SYNC-DL that length is 64 chips;
With described first the protection interval performance number and described second the protection interval the performance number addition after, again divided by the performance number of described SYNC-DL, obtain the first power ratio;
Whether judge described the first power ratio less than the first predetermined threshold, if determine that described receive data window is Window;
Obtain that length is the SNYC-DL of 64 chips in the described Window, searching out length in described SNYC-DL is the ceiling capacity window of W-shift chip and the least energy window that length is the W-shift chip, and wherein W-shift is variable energy window length;
Described least energy window divided by described ceiling capacity window, is obtained the second power ratio;
Whether judge described the second power ratio greater than the second predetermined threshold, if determine that described length is that the position of the SNYC-DL of 48 chips is the position of coarse synchronizing of downlink pilot.
2. method according to claim 1 is characterized in that, described method also comprises:
Obtain a plurality of the first power ratio, wherein the number of the first power ratio calculates by formula M=(N-W)/S+1, and M is the number of the first power ratio, and N is for receiving the length of signal, and W is characteristic length, and S is moving step length.
3. method according to claim 2 is characterized in that, describedly judges that whether described the first power ratio is specially less than the step of the first predetermined threshold:
In M the first power ratio, filter out the first minimum power ratio;
The first power ratio and first predetermined threshold of described minimum are compared.
4. method according to claim 3 is characterized in that, if described the first power ratio more than or equal to described the first predetermined threshold, described method also comprises:
Skip the back validation checking, directly report synchronization failure.
5. a device that is used for determining coarse synchronizing of downlink pilot is characterized in that described device comprises characteristic window detector and Window the validity judge device, wherein
Described characteristic window detector, be used in length is the receive data window of 128 chip, performance number and the length that calculates length and be the first protection interval of 32 chips be 32 chips the second protection interval performance number with, obtain the 3rd performance number, be the performance number of the descending synchronous code sequence SYNC-DL of 64 chips divided by length with described the 3rd performance number, obtain the first power ratio, if described the first power ratio during less than the first predetermined threshold, determines that described receive data window is Window;
Described Window the validity judge device, the SNYC-DL that the described Window intercepted length that is used for determining at described characteristic window detector is 64 chips, in described SNYC-DL, search out long for the ceiling capacity window of W-shift chip and length be the least energy window of W-shift chip, and with described least energy window divided by the ceiling capacity window, obtain the second power ratio, if described the second power ratio is during greater than the second predetermined threshold, determine that described length is that the position of the SNYC-DL of 64 chips is the position of coarse synchronizing of downlink pilot, wherein W-shift is variable energy window length.
6. device according to claim 5 is characterized in that, described characteristic window detector comprises:
The first acquisition module, be used in length is the receive data window of 128 chips, performance number, the length of obtaining respectively length and be the first protection interval of 32 chips is the performance number at the second protection interval of 32 chips and the performance number of the descending synchronous code sequence SYNC-DL that length is 64 chips;
The first computing module after the performance number and described second at described the first protection interval is protected the performance number addition at interval, again divided by the performance number of described SYNC-DL, obtains the first power ratio;
The first processing module is used for whether judging described the first power ratio less than the first predetermined threshold, if determine that described receive data window is Window.
7. device according to claim 5 is characterized in that, described Window the validity judge device comprises:
The second acquisition module is used for obtaining described Window length the SNYC-DL that is 64 chips, and searching out length in described SNYC-DL is the ceiling capacity window of W-shift chip and the least energy window that length is the W-shift chip;
The second computing module is used for described least energy window obtaining the second power ratio divided by described ceiling capacity window;
The second processing module is used for whether judging described the second power ratio greater than the second predetermined threshold, if described length is that the position of the SNYC-DL of 64 chips is the position of coarse synchronizing of downlink pilot.
8. device according to claim 6, it is characterized in that, described the first computing module is used for obtaining a plurality of the first power ratio, wherein the number of the first power ratio calculates by formula M=(N-W)/S+1, M is the number of the first power ratio, N is for receiving the length of signal, and W is characteristic length, and S is moving step length.
9. device according to claim 8, it is characterized in that described the first processing module is used for filtering out the first minimum power ratio M the first power ratio, if the first power ratio of described minimum during less than the first predetermined threshold, determines that described receive data window is Window; If the first power ratio of described minimum during more than or equal to the first predetermined threshold, directly reports synchronization failure.
CN2009100781842A 2009-02-26 2009-02-26 Method and device for confirming coarse synchronizing of downlink pilot Expired - Fee Related CN101588192B (en)

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CN102457325B (en) * 2010-10-19 2014-11-05 中兴通讯股份有限公司 Method and device for rough synchronization of cell search

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