CN101587837A - Forming method of groove - Google Patents
Forming method of groove Download PDFInfo
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- CN101587837A CN101587837A CNA2008101125047A CN200810112504A CN101587837A CN 101587837 A CN101587837 A CN 101587837A CN A2008101125047 A CNA2008101125047 A CN A2008101125047A CN 200810112504 A CN200810112504 A CN 200810112504A CN 101587837 A CN101587837 A CN 101587837A
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Abstract
The invention relates to a forming method for a groove, which comprises the following steps: forming a medium layer on a semiconductor substrate; forming a sacrificial layer and a photoresist layer on the medium layer; patterning the photoresist layer; defining the shape of the groove to be formed; sequentially etching the sacrificial layer and the medium layer by taking the photoresist layer as a mask; forming the groove in the medium layer; and removing the photoresist layer and the sacrificial layer. The forming method improves the strip shape phenomenon on the top of the groove in the process of the groove etching, better controls the depth of the needed groove and improves the etching precision.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, specifically, relate to a kind of formation method of groove.
Background technology
In semiconductor fabrication process, in order on Semiconductor substrate, to form needed through hole or groove, be used for application such as backend interconnect technology Damascus technics, need to adopt lithographic method on Semiconductor substrate, to carve the groove of desired depth.But because the difficulty of technology controlling and process, the groove that etching is come out has some defectives mostly, differs to meet requirement in advance surely fully.
Prior art discloses the method that forms groove in a kind of dielectric layer on Semiconductor substrate, described method comprises: be coated with anti-reflection coating (Anti Reflect Coating on dielectric layer, ARC), on described ARC, form the photoresist mask, etching ARC and dielectric layer successively, and in dielectric layer, etching the groove of desired depth, the etching selection ratio of described dielectric layer and photoresist layer is between 1: 1 and 2: 1.
At application number is in the Chinese patent application of CN200480040167.5, can also find more information relevant with technique scheme.
In the process of existing etching groove; because it is too thin to be used to define the photoresist layer of patterning of groove shape; to such an extent as to can not protect the dielectric layer below the photoresist layer during as etch mask well, make the whole groove top generation striated phenomenon (Striation Issue) that etching is come out.As shown in Figure 1, in the process for the formation groove that exists in the prior art, the vertical view of the test result of groove top generation striated phenomenon.11 places can see by mark among the figure, and the top that the groove of striated phenomenon takes place the very out-of-flatness that becomes may influence the required precision in the semiconductor fabrication process.
For the striated phenomenon that takes place in the process that solves above-mentioned etching groove, available technology adopting multiple improvement way, a kind of formation method of groove wherein, as shown in Figure 2.Etch on the dielectric layer 102 on Semiconductor substrate 100 in the process of groove 104,106 and 108, on the basis of original employed dry etching gas, change the flow of gas, perhaps add new polymer gas, as CHF
3And prolongation etch period, the etching groove result who obtains like this can suppress the striated phenomenon of groove top preferably, but this method can not be controlled the groove 104,106 and 108 that is etched well and reach required depth bounds, the concrete numerical value change fluctuation ratio of gash depth is bigger, the precision control ratio is difficulty, influences the uniformity that deposit enters the resistance value of the metal interconnecting wires in the groove then.
The formation method of another kind of groove, as shown in Figure 3.On Semiconductor substrate 110, form dielectric layer 112, the thicker photoresist layer 114 of coating one deck on dielectric layer 112, the patterning photoresist layer 114 then, define the position that will form groove.But the etching groove result who obtains so equally can be not desirable, because the top can take place in blocked up photoresist layer 114 after graphical, the figure that causes photoresist layer 114 to define is out compared with the figure on the mask some shape skews can be taken place, and just can't obtain desirable groove shape in the position of original required formation groove like this in ensuing dry etching process.
As mentioned above, though given technical scheme can solve the striated phenomenon of groove top in the groove forming process to a certain extent in the prior art, but also can bring other serious defectives, therefore these all can not be necessary to find out a kind of better method from other angles as the appropriate method that solves the striated phenomenon.
Summary of the invention
The problem that the present invention solves provides a kind of formation method of groove, has improved the fringe phenomena in the etching groove process.
For addressing the above problem, the invention provides a kind of formation method of groove, comprising: on Semiconductor substrate, form dielectric layer; On dielectric layer, form sacrifice layer and photoresist layer; The patterning photoresist layer defines the shape that will form groove; With the photoresist layer is mask, and etching sacrificial layer and dielectric layer form groove in dielectric layer successively; Remove photoresist layer and sacrifice layer.
Optionally, described sacrifice layer is simple layer or composite bed.
Optionally, the described dielectric layer combination in any that is silicon dioxide, silicon nitride, silicon oxynitride, non-impurity-doped silicate glass, boron phosphorus silicate glass or tetraethoxysilane or above-mentioned material.
Optionally, the described sacrifice layer combination in any that is silicon dioxide, silicon nitride, silicon oxynitride, non-impurity-doped silicate glass, boron phosphorus silicate glass or tetraethoxysilane or above-mentioned material.
Optionally, described dielectric layer has different etching selection ratio with sacrifice layer.
Optionally, the thickness of described sacrifice layer is 500 dusts～1500 dusts.
Optionally, the formation method of described sacrifice layer is CVD (Chemical Vapor Deposition) method or plasma enhanced CVD method.
Optionally, the method for described etching sacrificial layer and dielectric layer is dry etching method or wet etching method.
Compared with prior art, the present invention has the following advantages: form sacrifice layer on the dielectric layer on the Semiconductor substrate, on sacrifice layer, form photoresist layer and patterning then, like this at etching sacrificial layer and dielectric layer successively when in dielectric layer, forming the groove of desired depth, because the existence of sacrifice layer is arranged on dielectric layer, make in the process of etching groove, can avoid since etching gas to the selection of dielectric layer and photoresist layer than not high enough, to such an extent as in etching groove, also etch away some photoresist layers, and then be etched directly into the place that should not be etched on the dielectric layer.In the process of etching groove, even if the striated phenomenon has appearred in sacrifice layer, also can after removing photoresist layer, be removed, on dielectric layer, just stay all smooth smooth groove of top and sidewall like this, and can control the degree of depth of required groove preferably.
Description of drawings
Fig. 1 is the vertical view of the test result of groove top generation striated phenomenon in the process of the formation groove that exists in the prior art;
Fig. 2 to Fig. 3 is the cross-sectional view that prior art forms groove;
Fig. 4 is the method flow schematic diagram of the formation groove of a specific embodiment of the present invention;
Fig. 5 to Fig. 9 is the cross-sectional view of the formation groove of the first embodiment of the present invention;
Figure 10 to Figure 14 is the cross-sectional view of the formation groove of the second embodiment of the present invention;
Figure 15 is the vertical view of test result of groove of the formation of a specific embodiment of the present invention.
Embodiment
The present invention forms sacrifice layer on the dielectric layer on the Semiconductor substrate, on sacrifice layer, form photoresist layer and patterning then, like this at etching sacrificial layer and dielectric layer successively when in dielectric layer, forming the groove of desired depth, because the existence of sacrifice layer is arranged on dielectric layer, make in the process of etching groove, can avoid since etching gas to the selection of dielectric layer and photoresist layer than not high enough, to such an extent as in etching groove, also etch away some photoresist layers, and then be etched directly into the place that should not be etched on the dielectric layer.In the process of etching groove, even if the striated phenomenon has appearred in sacrifice layer, also can after removing photoresist layer, be removed, on dielectric layer, just stay all smooth smooth groove of top and sidewall like this, and can control the degree of depth of required groove preferably.
The invention will be further described below in conjunction with specific embodiments and the drawings, but should this restriction protection scope of the present invention.
Be the formation method flow schematic diagram of the groove of a specific embodiment of the present invention as shown in Figure 4.As shown in Figure 4, comprising: execution in step S201 forms dielectric layer on Semiconductor substrate; Execution in step S202 forms sacrifice layer and photoresist layer on dielectric layer; Execution in step S203, the patterning photoresist layer defines the shape that will form groove; Execution in step S204 is a mask with the photoresist layer, and etching sacrificial layer and dielectric layer form groove in dielectric layer successively; Execution in step S205 removes photoresist layer and sacrifice layer.
Fig. 5 to Fig. 9 is the cross-sectional view of the formation groove of the first embodiment of the present invention, below in conjunction with accompanying drawing, describes its forming process in detail.As shown in Figure 5, on Semiconductor substrate 200, form dielectric layer 202.
The material of described formation dielectric layer 202 can be the combination in any of silicon dioxide, silicon nitride, silicon oxynitride, non-impurity-doped silicate glass (USG), boron phosphorus silicate glass (BPSG) or tetraethoxysilane (TEOS) or above-mentioned material; The method of described formation dielectric layer 202 can be CVD (Chemical Vapor Deposition) method or plasma enhanced CVD method; The thickness of described dielectric layer 202 can be 9000 dusts～15000 dusts; Be used as inter-level dielectric (ILD) or inter-metal medium (IMD) in the backend process interconnection structure.
As shown in Figure 6, form sacrifice layer 204 on dielectric layer 202, described dielectric layer 202 has different etching selection ratio with sacrifice layer 204.
The material of described formation sacrifice layer 204 can be the combination in any of silicon dioxide, silicon nitride, silicon oxynitride, non-impurity-doped silicate glass (USG), boron phosphorus silicate glass (BPSG) or tetraethoxysilane (TEOS) or above-mentioned material, preferred silicon dioxide; The method of described formation sacrifice layer 204 can be CVD (Chemical Vapor Deposition) method or plasma enhanced CVD method; The thickness of described sacrifice layer 204 can be 500 dusts～1500 dusts; Be used as the sacrifice layer that suppresses trenched side-wall striated phenomenon in the subsequent etching process.
In the present embodiment, the thickness concrete example of described sacrifice layer 204 is as 500 dusts, 600 dusts, 700 dusts, 800 dusts, 900 dusts, 1000 dusts, 1100 dusts, 1200 dusts, 1300 dusts, 1400 dusts or 1500 dusts etc., preferred 1000 dusts.
As shown in Figure 7, on sacrifice layer 204, form photoresist layer 206, the groove shape on the mask is transferred on the photoresist layer 206, after developing, on Semiconductor substrate, define groove shape; With photoresist layer 206 is mask, and etching sacrificial layer 204 forms groove 207 to dielectric layer 202.
In the present embodiment, described lithographic method can be dry etching method or wet etching method.
As shown in Figure 8, be mask with photoresist layer 206, etching dielectric layer 202 desired depth to the dielectric layer 202 forms groove 208.
In the present embodiment, described lithographic method can be dry etching method or wet etching method.
As shown in Figure 9, obtain groove 208 behind removal photoresist layer 206 and the sacrifice layer 204.
In the present embodiment, described removal photoresist layer 206 can adopt ashing method and wet etching method, and described removal sacrifice layer 204 can adopt dry etching method or wet etching method.
Figure 10 to Figure 14 is the cross-sectional view of the formation groove of the second embodiment of the present invention, below in conjunction with accompanying drawing, describes its forming process in detail.As shown in figure 10, on Semiconductor substrate 300, form dielectric layer 302.
The material of described formation dielectric layer 302 can be the combination in any of silicon dioxide, silicon nitride, silicon oxynitride, non-impurity-doped silicate glass (USG), boron phosphorus silicate glass (BPSG) or tetraethoxysilane (TEOS) or above-mentioned material; The method of described formation dielectric layer 302 can be CVD (Chemical Vapor Deposition) method or plasma enhanced CVD method; The thickness of described dielectric layer 302 can be 9000 dusts～15000 dusts; Be used as inter-level dielectric (ILD) or inter-metal medium (IMD) in the backend process interconnection structure.
As shown in figure 11, form sacrifice layer 307 on dielectric layer 302, described sacrifice layer 307 comprises first sacrifice layer 304 and second sacrifice layer 306 successively, and described dielectric layer 302 has different etching selection ratio with sacrifice layer 307.
The material of described formation first sacrifice layer 304 can be the combination in any of silicon dioxide, silicon nitride, silicon oxynitride, non-impurity-doped silicate glass (USG), boron phosphorus silicate glass (BPSG) or tetraethoxysilane (TEOS) or above-mentioned material, preferred nitrogen silica; The method of described formation first sacrifice layer 304 can be CVD (Chemical Vapor Deposition) method or plasma enhanced CVD method; The thickness of described first sacrifice layer 304 can be 500 dusts～1500 dusts; Be used as the sacrifice layer that suppresses trenched side-wall striated phenomenon in the subsequent etching process.
In the present embodiment, the thickness concrete example of described first sacrifice layer 304 is as 500 dusts, 600 dusts, 700 dusts, 800 dusts, 900 dusts, 1000 dusts, 1100 dusts, 1200 dusts, 1300 dusts, 1400 dusts or 1500 dusts etc., preferred 1000 dusts.
The material of described formation second sacrifice layer 306 can be the combination in any of silicon dioxide, silicon nitride, silicon oxynitride, non-impurity-doped silicate glass (USG), boron phosphorus silicate glass (BPSG) or tetraethoxysilane (TEOS) or above-mentioned material, preferred silicon dioxide; The method of described formation second sacrifice layer 306 can be CVD (Chemical Vapor Deposition) method or plasma enhanced CVD method; The thickness of described second sacrifice layer 306 can be 500 dusts～1500 dusts; Be used as the sacrifice layer that suppresses trenched side-wall striated phenomenon in the subsequent etching process.
In the present embodiment, the thickness concrete example of described second sacrifice layer 306 is as 500 dusts, 600 dusts, 700 dusts, 800 dusts, 900 dusts, 1000 dusts, 1100 dusts, 1200 dusts, 1300 dusts, 1400 dusts or 1500 dusts etc., preferred 1000 dusts.
In the present embodiment, form two-layer sacrifice layer reason can directly to contact adhesiveness not enough for second sacrifice layer 306 and dielectric layer 302, in order to strengthen the adhesiveness between second sacrifice layer 306 and the dielectric layer 302, so before forming second sacrifice layer 306 on the dielectric layer 302, can form one deck first sacrifice layer 304 earlier.
As shown in figure 12, on second sacrifice layer 306, form photoresist layer 308, the groove shape on the mask is transferred on the photoresist layer 308, after developing, on Semiconductor substrate, define groove shape; With photoresist layer 308 is mask, and second sacrifice layer 306 in the etching sacrificial layer 307 and first sacrifice layer 304 form groove 309 to dielectric layer 302 successively.
In the present embodiment, described lithographic method can be dry etching method or wet etching method.
As shown in figure 13, be mask with photoresist layer 308, etching dielectric layer 302 desired depth to the dielectric layer 302 forms groove 310.
In the present embodiment, described lithographic method can be dry etching method or wet etching method.
As shown in figure 14, obtain groove 310 behind removal photoresist layer 308 and the sacrifice layer 307.
In the present embodiment, described removal photoresist layer 308 can adopt ashing method and wet etching method, and described removal sacrifice layer 307 can adopt dry etching method or wet etching method.
Be the vertical view of test result of groove of the formation of a specific embodiment of the present invention as shown in figure 15.Compare with the result who obtains after as shown in Figure 1 the use prior art, 21 places can see by mark among the figure, utilize method of the present invention can suppress in the semiconductor fabrication process striated phenomenon of the groove top that produced in the general etching groove process preferably, resulting groove top and sidewall lines are smooth smooth, satisfy the subsequent technique needs.
In above-mentioned embodiment of the present invention, the number of plies of each dielectric layer on the described Semiconductor substrate and material are not well-determined, may have the part dielectric layer in the technical process of reality reduces or increases, two-layer such as on Semiconductor substrate, forming, three layers, four layers even more multi-layered dielectric layer, as long as after etching obtains the groove of desired depth on the dielectric layer of required formation groove, to be arranged in all the other dielectric layers on the dielectric layer of required reservation as the sacrifice layer of etching groove process, finish groove later on its removal in etching, the groove top of being made up of all the other each dielectric layers just can keep smoothness preferably, can suppress the groove top marginal band shape phenomenon that produces in the etching groove process effectively.Described each dielectric layer all is an employed rete in the particular semiconductor manufacturing process; its concrete purposes depends on concrete device architecture; should only not be confined to embodiment disclosed in this invention; but, then all fall within the rights protection scope of the presently claimed invention as long as it is identical with above-mentioned embodiment to form the core methed of groove.
In above-mentioned embodiment of the present invention, the photoresist layer that defines the groove position of patterning also can be got rid of earlier after intact one deck of etching or multilayer sacrifice layer, be hard mask with one deck or multilayer sacrifice layer then, sacrifice layer or dielectric layer below the current sacrifice layer of continuation etching, desired depth to the dielectric layer forms groove.
The invention has the advantages that, on the dielectric layer on the Semiconductor substrate, form sacrifice layer, on sacrifice layer, form photoresist layer and patterning then, like this at etching sacrificial layer and dielectric layer successively when in dielectric layer, forming the groove of desired depth, because the existence of sacrifice layer is arranged on dielectric layer, make in the process of etching groove, can avoid since etching gas to the selection of dielectric layer and photoresist layer than not high enough, to such an extent as in etching groove, also etch away some photoresist layers, and then be etched directly into the place that should not be etched on the dielectric layer.In the process of etching groove, even if the striated phenomenon has appearred in sacrifice layer, also can after removing photoresist layer, be removed, on dielectric layer, just stay all smooth smooth groove of top and sidewall like this, and can control the degree of depth of required groove preferably.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (8)
1. the formation method of a groove is characterized in that, comprising:
On Semiconductor substrate, form dielectric layer;
On dielectric layer, form sacrifice layer and photoresist layer;
The patterning photoresist layer defines the shape that will form groove;
With the photoresist layer is mask, and etching sacrificial layer and dielectric layer form groove in dielectric layer successively;
Remove photoresist layer and sacrifice layer.
2. the formation method of groove according to claim 1 is characterized in that, described sacrifice layer is simple layer or composite bed.
3. the formation method of groove according to claim 1 is characterized in that, described dielectric layer has different etching selection ratio with sacrifice layer.
4. the formation method of groove according to claim 3 is characterized in that, described dielectric layer is the combination in any of silicon dioxide, silicon nitride, silicon oxynitride, non-impurity-doped silicate glass, boron phosphorus silicate glass or tetraethoxysilane or above-mentioned material.
5. the formation method of groove according to claim 3 is characterized in that, described sacrifice layer is the combination in any of silicon dioxide, silicon nitride, silicon oxynitride, non-impurity-doped silicate glass, boron phosphorus silicate glass or tetraethoxysilane or above-mentioned material.
6. the formation method of groove according to claim 1 is characterized in that, the thickness of described sacrifice layer is 500 dusts～1500 dusts.
7. the formation method of groove according to claim 1 is characterized in that, the formation method of described sacrifice layer is CVD (Chemical Vapor Deposition) method or plasma enhanced CVD method.
8. the formation method of groove according to claim 1 is characterized in that, the method for described etching sacrificial layer and dielectric layer is dry etching method or wet etching method.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101125047A CN101587837A (en) | 2008-05-23 | 2008-05-23 | Forming method of groove |
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| CNA2008101125047A CN101587837A (en) | 2008-05-23 | 2008-05-23 | Forming method of groove |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101913550A (en) * | 2010-08-11 | 2010-12-15 | 上海集成电路研发中心有限公司 | Microbridge structure of micro-electromechanical system and manufacture method thereof |
| CN103632953A (en) * | 2012-08-20 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | A manufacturing method for a V-type groove structure based on a silicon oxide substrate |
| CN117877973A (en) * | 2024-03-08 | 2024-04-12 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure |
| CN117877973B (en) * | 2024-03-08 | 2024-06-04 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure |
-
2008
- 2008-05-23 CN CNA2008101125047A patent/CN101587837A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101913550A (en) * | 2010-08-11 | 2010-12-15 | 上海集成电路研发中心有限公司 | Microbridge structure of micro-electromechanical system and manufacture method thereof |
| CN101913550B (en) * | 2010-08-11 | 2015-12-02 | 上海集成电路研发中心有限公司 | The manufacture method of microbridge structure of micro-electromechanical system |
| CN103632953A (en) * | 2012-08-20 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | A manufacturing method for a V-type groove structure based on a silicon oxide substrate |
| CN103632953B (en) * | 2012-08-20 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | A kind of manufacture method of the V-type groove structure based on silicon oxide substrate |
| CN117877973A (en) * | 2024-03-08 | 2024-04-12 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure |
| CN117877973B (en) * | 2024-03-08 | 2024-06-04 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor structure |
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