CN101582293B - Memory element and method for controlling word line signal in power supply starting up/cutting off program - Google Patents
Memory element and method for controlling word line signal in power supply starting up/cutting off program Download PDFInfo
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- CN101582293B CN101582293B CN2009101410407A CN200910141040A CN101582293B CN 101582293 B CN101582293 B CN 101582293B CN 2009101410407 A CN2009101410407 A CN 2009101410407A CN 200910141040 A CN200910141040 A CN 200910141040A CN 101582293 B CN101582293 B CN 101582293B
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Abstract
The present invention relates to a power supply starting up/cutting off sequence mechanism for a memory element, and concretely provides a method of controlling word wire signals of a memory element in a power supply cutting-off program. The method comprises steps of pulling down word wire signals to a low logic state; cutting off the current path between an external power supplier and an internal power supplier, after the word wire signals are pulled down to the low logic state; and cutting off the current path between an external ground voltage to an internal ground voltage, after the current path between the external power supplier and the internal power supplier is cut off completely.
Description
Technical field
Relate generally to integrated circuit of the present invention (IC) designs, and relates more particularly to the method for its word-line signal of control in memory element and dump or the start-up routine.
Background technology
In order to reduce under the electrical source consumption pattern, for example sleep pattern or standby mode use dump mechanism to cut off the power supply supply of some circuit module to memory element usually at some.General dump mechanism utilization internal electric source control circuit, power supply unit switch (VDD switch), ground voltage switch (VSS switch).Fig. 1 shows required internal electric source control circuit 100, VSS switch 130 and the VDD switch 160 of general dump mechanism.Internal electric source control circuit 100 is made up of reverser (inverter) 102, and the output terminal of reverser 102 is coupled to the input end of reverser 104 and the input end of reverser 106.Reverser 102 is linked to external power source supply VDD, externally voltage VSS and voltage VSSI internally.Reverser 104 is linked to external power source supply VDD, internal electric source supply VDDI and voltage VSS externally.Reverser 106 also is linked to external power source supply VDD, internal electric source supply VDDI and voltage VSS externally.Reverser 104 and 106 output terminal are coupled respectively to word line WLR and WL.The source electrode of PMOS transistor 108 is connected to external power source supply VDD and node 110, and the drain electrode of PMOS transistor 108 is connected to the output terminal of reverser 102 and the input end of reverser 104 and 106.The grid of PMOS transistor 108 is then controlled by dump signal (PD).
VDD switch 160 is made up of the PMOS transistor 162 and 164 that is connected between external power source supply VDD and the internal electric source supply VDDI.The grid of PMOS transistor 162 is controlled by the first power supply unit switch controlling signal PDL, and the grid of PMOS transistor 164 is controlled by second source supply switch controlling signal PDR.VSS switch 130 comprises and is coupling in externally voltage VSS and the nmos pass transistor between the voltage VSSI 132 internally.The grid of nmos pass transistor 132 is controlled by dump signal PD.
When a dump program start, dump signal PD pulled down to low level opening PMOS transistor 108, and external power source supply vdd voltage is passed to the input end of reverser 104 and 106.Therefore, the voltage on word line WL and the WLR remains on low level, therefore the data that are stored in memory array (not being shown among the figure) is kept, and can not change because of the power supply of peripheral circuit and disperse.Low power supply is cut electric signal PD and is closed nmos pass transistor 132, so isolating exterior ground voltage VSS and voltage VSSI internally.In the dump program; The first power supply unit control signal PDL and second source supply control signal PDR by on move high levels to; To close PMOS transistor 162 and 164, make external power source supply VDD and internal electric source supply VDDI be isolated from each other.
A shortcoming of known dump mechanism is data surging (glitch), and it is caused by the unsuitable sequential of control PMOS transistor 108, VDD switch 160 and VSS switch 130.In the dump program process, dump signal PD pulled down to low level, and power supply unit control signal PDL and PDR simultaneously by on move high levels to.Current path between external power source supply VDD and internal electric source supply VDDI possibly just be cut off before PMOS transistor 108 is opened fully fully.Cause the VDDI circuit that is connected to reverser 104 and 106 to become floating.This possibly cause that the signal on word line WL and the WLR produces surging, therefore disturbs the data that are stored in memory array.
Therefore those skilled in the art need a kind of power initiation/cut-out mechanism of peripheral circuit, and it can not disturb the data that are stored in memory array.
Summary of the invention
The present invention relates to a kind ofly in a dump program, control the method for a word-line signal of a memory element.In one embodiment of this invention, this method comprises: word-line signal is pulled down to a low logic state; After word-line signal is pulled down to low logic state, cut off a current path from external power source supply to an internal electric source supply; And after the current path that cuts off external power source supply to internal electric source supply fully, cut off from voltage to one current path of voltage internally externally.
In another embodiment of the present invention, this method comprises: connect from voltage to one current path of voltage internally externally; After the current path that connects voltage externally to voltage internally, connect a current path from external power source supply to an internal electric source supply; And after the current path that connects external power source supply to internal electric source supply, a word line is maintained a normal manipulation mode.
In an embodiment more of the present invention, this method is embodied as a memory element, and it comprises: a dump control module supplies response one dump signal and produces one and draw signal on initial; One dump is selected module, with the coupling of dump control module, supplies to produce on one and draws signal, produces a word-line signal that is positioned at a low logic state so that draw signal in the power control response; One first delay chain; Select the module coupling with dump control module and dump; Draw signal and produce one first inhibit signal on the response of first delay chain is initial, and first inhibit signal is sent to dump selection module, dump is selected module responds first inhibit signal and is produced an internal electric source supply switch controlling signal; Wherein, the sequential of internal electric source supply switch controlling signal lags behind the sequential of drawing signal; One second delay chain; Select the module coupling with dump; Supply power source-responsive to cut off and select the M signal that module produced and produce one second inhibit signal, second inhibit signal feeds back to dump and selects module, to produce a voltage switch control signal internally; Wherein, internally the sequential of voltage switch control signal lags behind the sequential of internal electric source supply switch controlling signal; An and code translator; Select the module coupling with dump; Supply to draw signal in the response and with word-line signal be pulled down to a low logic state, after word-line signal is pulled down to low logic state; Response internal electric source supply switch controlling signal and cutting off from a current path of external power source supply to an internal electric source supply; And after externally the current path of power supply unit to internal electric source supply has been completely severed, responds internally the voltage switch control signal and cut off from voltage to one current path of voltage internally externally.
Yet operating structure of the present invention and method and its additional objects and advantage will be from below in conjunction with more fully being understood the description of accompanying drawing to specific embodiment.
Description of drawings
Fig. 1 shows various circuit modules, and it supports the dump mechanism of the peripheral circuit of a known memory element.
Fig. 2 is according to one embodiment of the invention, shows the startup/shutoff sequence mechanism of the peripheral circuit of a memory element.
Fig. 3 is according to one embodiment of the invention, and legend shows a memory element of implementing to have startup/shutoff sequence mechanism.
Fig. 4 is according to one embodiment of the invention, and legend shows the dump control module of startup of the present invention/shutoff sequence mechanism.
Fig. 5 is according to one embodiment of the invention, and legend shows the dump of startup of the present invention/shutoff sequence mechanism and selects module.
Fig. 6 is according to one embodiment of the invention, and legend shows a delay chain of startup of the present invention/shutoff sequence mechanism.
Fig. 7 is according to one embodiment of the invention, and legend shows an x code translator of startup of the present invention/shutoff sequence mechanism.
Embodiment
The present invention relates to the startup/shutoff sequence mechanism of memory element.Various embodiment of the present invention below only is described, to explain its principle.Though not it will be understood by a person skilled in the art that clearly to be described in wherein, yet the present invention also can be applicable in the various equivalence variations that make the concrete realization of principle of the present invention.
Fig. 2 is according to one embodiment of the invention, shows the startup/shutoff sequence mechanism of the peripheral circuit of a memory element.For this embodiment; Memory element; For example static random access memory (SRAM), DRAM (DRAM), flash memory, magnetic-resistance random access internal memory (MRAM) and phase transition internal memory comprise: a VDD switch, a VSS switch, an internal electric source control circuit.The VDD switch opens and close external power source supply VDD and internal electric source supply VDDI between current path; VSS switch opens and close externally voltage VSS and the internally current path between the voltage VSSI; And draw on one in the internal electric source control circuit control memory element/voltage on the pull-down node, with the voltage on the control word line.This memory element comprises a circuit design, in order to the sequence of operation of control VDD switch, VSS switch and internal electric source control circuit, makes them can not operated simultaneously.
With reference to Fig. 1 and Fig. 2, when the dump program start, at first open the PMOS transistor 108 of internal electric source control circuit 100, simultaneously to provide vdd voltage to node 110.As a result, reverser 104 and output signal each self-sustaining low logic state on word line WLR and WL of 106.After PMOS transistor 108 is opened fully, close VDD switch 160, to cut off the current path between external power source supply VDD and the internal electric source supply VDDI.Then, close VSS switch 130, to cut off externally voltage VSS and the internally current path between the voltage VSSI.
After PMOS transistor 108 is opened fully, when the PMOS transistor (not being shown among the figure) in reverser 104 and 106 on word line WLR and WL during output LOW voltage, the PMOS transistor remains on closed condition.To cause internal electric source supply line VDDI suspension joint though close VDD switch 160 subsequently, this can not influence the signal on word line WLR and the WL, closes because in reverser 104 and 106, be coupled to the PMOS transistor of internal electric source supply line VDDI.Therefore, in the dump program, can keep the data integrity of memory element.
In the power initiation program, open VSS switch 130, with conducting externally voltage VSS and the current path between the voltage VSSI internally.Then, open VDD switch 130, with the current path between conducting external power source supply VDD and the internal electric source supply VDDI.Afterwards, close PMOS transistor 108, make word line WLR and WL can pass through reverser 102,104 and 106 accesses under normal operation.
Fig. 3 is according to one embodiment of the invention, and legend shows the layout of a memory element 300 of the unlatching of embodiment of the present invention/cut-out mechanism.Memory element 300 comprises an x code translator 302, dump is selected module 304, dump control module 306 and delay chain 308 and 310.X code translator 302 has input end, and these input ends are coupled to external power source supply VDD, externally voltage VSS, code translator input signal A and B, enable signal EN and dump are selected the various input signals that module 304 is received.X code translator 302 has output terminal, and these output terminals are coupled to a word line WL, and it also is connected to memory cell array (not being shown among this figure).X code translator 302 is coupled to dump through load 312b and 312c and selects module 304, and is coupled to delay chain 308 and 310 through load 312d, 316b and 320b.X code translator 302 also is coupled to nmos pass transistor 314, and it receives internally that voltage switch control signal PD_VSSI_L controls.
Dump is selected module 304 to be connected to external power source supply VDD and is reached voltage VSS externally.Dump selects module 304 to be coupled to delay chain 308 through load 320a, 320b, 320c and 320d, and is coupled to delay chain 310 through load 316a, 316b, 316c and 316d.Dump selects module 304 also to be coupled to dump control module 306 and dump signal PD.
The circuit of embodiment of the present invention dump sequence mechanism is arranged on x code translator 302, dump is selected module 304, dump control module 306, and in delay chain 308 and 310.The structure of this circuit and operation will combine accompanying drawing to be described in detail in down.
Fig. 4 is according to one embodiment of the invention, and legend shows the dump control module 306 of startup of the present invention/cut-out mechanism.A string reverser 402,404,406 and 408 is coupling in external power source supply VDD and externally between the voltage VSS.Reverser 402 has an input end, is coupled to dump signal PD and diode 410.Reverser 406 output one initial pulldown signal PD_L_int, it is reversed, and device 408 is reverse to become one to draw signal PD_H_int on initially.
Fig. 5 is according to one embodiment of the invention, and legend shows the dump of startup of the present invention/cut-out mechanism and selects module 304.Reverser 502 has an input end, is coupled to dump signal PD and reverser 504,506,508 and 510.Reverser 504 has an input end, is coupled to an input end that draws signal PD_H_int and reverser 510 on initial.Reverser 506 has an input end, is coupled to an input end of reverser 508 and an output terminal of reverser 512.One reverser 514 is coupling between the input end and the second inhibit signal PD_LNG of reverser 512.Reverser 504 and 506 output terminal are coupled to an input end of reverser 516, and reverser 516 also is connected to reverser 518.Reverser 508 and 510 output terminal are coupled to an input end of reverser 520, and reverser 520 also is connected to reverser 522.Reverser 518 outputs one drop-down signal PD_L, it is reversed on the device 524 reverse one-tenth one and draws signal PD_H.Reverser 522 outputs one are voltage switch control signal PD_VSSI_L internally.
With reference to Fig. 3 and Fig. 5, dump selects module 304 to comprise a circuit 526, receives one first inhibit signal PD_MD from delay chain 310 to load 316d, and exports an internal electric source supply switch controlling signal PD_VDDI_H simultaneously.Circuit 526 comprises phase inverter 530 and 532, in series is coupling between the first inhibit signal PD_MD and the power supply unit control signal PD_VDDI_H.Dump selects module 304 also to comprise a circuit 528, receives the first inhibit signal PD_MD, and exports a M signal PD_INT.Circuit 528 comprises the reverser 534 and 536 that in series is coupling between the first inhibit signal PD_MD and the M signal PD_INT.
Fig. 6 is according to one embodiment of the invention, and legend shows the delay chain 308 of startup of the present invention/cut-out mechanism.With reference to Fig. 3 and Fig. 6, delay chain 308 selects module 304 to receive M signal PD_INT from dump, and exports the second inhibit signal PD_LNG simultaneously.Delay chain 308 comprises a plurality of reversers 602,604,606,608,610,612,614 and 616, and these reversers in series are coupling between the M signal PD_INT and the second inhibit signal PD_LNG.Each reverser 602,604,606,608,610,612,614 and 616 is coupling between VDD and the VSS.Response internal electric source supply switch controlling signal PD_VDDI_H produces internal electric source supply VDDI through a PMOS transistor 618, and PMOS transistor 618 is coupling between external power source supply VDD and the internal electric source supply VDDI.Respond internally voltage switch control signal PD_VSSI_L, produce internally voltage VSSI through a nmos pass transistor 620, nmos pass transistor 620 is coupling in externally voltage VSS and internally between the voltage VSSI.
Fig. 7 is according to one embodiment of the invention, and legend shows the x code translator 302 of startup of the present invention/cut-out mechanism.X code translator 302 comprises a circuit module 702, and it receives an input signal A, and on word line WL, produces the output signal.In the circuit module 702, a PMOS transistor 704 has externally power supply unit VDD of its source-coupled, and its drain coupled is in the drain electrode of a nmos pass transistor 708, and wherein, the grid of PMOS transistor 704 and nmos pass transistor 708 is controlled by input signal A.PMOS transistor 706 has externally power supply unit VDD of its source-coupled, and its drain coupled is at an input end of node 710 and reverser 712.The output terminal of reverser 712 is coupled to the grid of PMOS transistor 714 and nmos pass transistor 716.PMOS transistor 714 has its drain coupled to the drain electrode at the nmos pass transistor 716 of node 718, and has its source-coupled to external power source supply VDD.PMOS transistor 720 is coupling between external power source supply VDD and the node 718.The grid of PMOS transistor 720 is controlled by enable signal EN.PMOS transistor 722 is coupling between external power source supply VDD and the node 718, and its grid is controlled by pulldown signal PD_L.Reverser 724 is connected between VDD/VDDI and the VSS, and has an input end and be coupled to node 718, and an output terminal is coupled to word line WL.Nmos pass transistor 726 is coupling in word line WL and externally between the voltage VSS, its grid is drawn signal PD_H to control.
With reference to Fig. 3 and Fig. 4, in the dump program, see (assert) dump signal PD off and convert memory element 300 to standby mode simultaneously, and dump signal PD is poured into dump selection module 304 and dump control module 306.Dump signal PD is reverse through reverser 402,404 and 406; And produce the initial pulldown signal PD_L_int be positioned at low level, and through reverser 402,404,406 and 408 reverse and produce and be positioned at one of high levels and draw signal PD_H_int on initially.Draw signal PD_H_int to pour into dump on initial and select module 304.
With reference to Fig. 3, Fig. 5, Fig. 6 and Fig. 7, dump signal PD turns to into through reverser 502,504,506,516,518 and 524 and draws a signal PD_H and a drop-down signal PD_L on one, with control circuit module 702 simultaneously.On draw signal PD_H open NMOS transistor 726, therefore promote voltage to the voltage externally on the word line WL, make and in the dump pattern, can keep the data integrity of memory element.
Draw signal PD_H_int to pour into delay chain 310 through load 316c on initial, to produce one first inhibit signal PD_MD, the first inhibit signal PD_MD feeds back to dump through load 316d and selects module 304.Select in the module 304 at dump, the first inhibit signal PD_MD converts an internal electric source supply switch controlling signal PD_VDDI_H to through reverser 530 and 532, and it pours into x code translator 302 through load 312d then.Because internal electric source supply switch controlling signal PD_VDDI_H responds the first inhibit signal PD_MD and produces, the sequential of internal electric source supply switch controlling signal PD_VDDI_H will lag behind the sequential of drawing signal PD_H and pulldown signal PD_L.As a result, the voltage on the power supply Control Node will startup/cut-out before the VDD switch cuts out.
Select in the module 304 at dump, the first inhibit signal PD_MD converts a M signal PD_INTL to through reverser 534 and 536, and M signal PD_INTL pours into delay chain 308 through load 320c.In delay chain 308, M signal PD_INTL becomes the second inhibit signal PD_LNG through reverser 602,604,606,608,610,612,614 and 616, and the sequential of the second inhibit signal PD_LNG lags behind the sequential of the first inhibit signal PD_MD.The second inhibit signal PD_LNG pours into dump and selects module 304 to produce internally voltage switch control signal PD_VSSI_L; Internally voltage switch control signal PD_VSSI_L bestows the grid of nmos pass transistor 314; To produce ground voltage control signal VSSI_in, to close the ground voltage switch.Because internally voltage switch control signal PD_VSSI_L responds the second inhibit signal PD_LNG and produces, internally the sequential of voltage switch control signal PD_VSSI_L will lag behind the sequential of internal electric source supply switch controlling signal PD_VDDI_H.As a result, after the VDD switch cuts out, the VSS switch will be closed.
Like above discussion, embodiments of the invention have disclosed a kind of circuit, its in the power-off program, on draw the power supply Control Node and close VDD switch and VSS switch successively.This can be avoided the surging on the word line that known dump mechanism produced.Therefore, dump sequential machine of the present invention is guaranteed the data integrity of the memory cell array in the memory element in the dump program.
Above description provides the embodiment of multiple various embodiment or embodiment of the present invention different qualities.Description to specific components and program among the embodiment is in order to make the present invention clearer.So undeniable, these are embodiment, and can't limit the described invention scope of claim.
Though the present invention is described as embodiment at this with one or more example illustration; The details shown in yet the present invention is not limited to; Because, can carry out the change of various modifications and structure under spirit of the present invention and scope at the equivalent of claim.Therefore, the claim of enclosing can be followed the mode of scope of the present invention and explain widely, and is of following claim.
Symbol description
100 internal electric source control circuits, 102,104,106 reversers
108,162,164 PMOS transistors, 110 nodes
130 VSS switches, 132 nmos pass transistors
160 VDD switches, 300 memory elements
302 x code translators, 304 dumps are selected module
306 dump control modules, 308,310 delay chains
312a, 312b, 312c, 312d load 314 nmos pass transistors
316a, 316b, 316c, 316d load
320a, 320b, 320c, 320d load
402,404,406,408 reversers, 410 diodes
502、504、506、508、510、512、514、516、518、520、522、
524 reversers
526,528 circuit
602,604,606,608,610,612,614,616 reversers
618 PMOS transistors, 620 nmos pass transistors
702 circuit modules
704,706,714,720,722,730 PMOS transistors
708,716,726 nmos pass transistors
710,718,736,738,740,756,758,760 nodes
712,724 reversers, 728 power supply unit on-off circuits
732,734,752,754 resistance
742,744,746,762,764,766 electric capacity
750 voltage generation circuit A internally, the B input signal
EN enable signal PD dump signal
The last signal PD_L pulldown signal of drawing of PD_H
PD_H_int initial on draw the initial pulldown signal of signal PD_L_int
PD_INT M signal PD_LNG second inhibit signal
PD_MD first inhibit signal
PD_VDDI_H internal electric source supply switch controlling signal
PD_VSSI_L is the voltage switch control signal internally
The PDL first power supply unit control signal
PDR second source supply control signal
WL, WLR word line VDD external power source supply
VDDI internal electric source supply VSS is voltage externally
VSSI is voltage internally.
Claims (15)
1. the method for a word-line signal of control one memory element in a dump program comprises:
Said word-line signal is pulled down to a low logic state;
After said word-line signal has been pulled down to said low logic state, cut off current path from external power source supply to an internal electric source supply; And
Cutting off fully from said external power source supply to the current path of said internal electric source supply, cutting off from voltage to one current path of voltage internally externally.
2. method according to claim 1; Comprise and produce a dump signal; To open a PMOS transistor; Import node so that an outside supply voltage is passed to one of a reverser from said external power source supply, said reverser becomes to be positioned at the word-line signal of said low logic state with said outside supply voltage transitions.
3. method according to claim 2; Also comprise and produce an internal electric source supply switch controlling signal; Supply to cut off current path from said external power source supply to said internal electric source supply; Wherein,, said dump signal just produces said internal electric source supply switch controlling signal after producing.
4. method according to claim 3; Also comprise internally voltage switch control signal of generation one; Supply to cut off current path from said voltage externally to said internally voltage; Wherein,, said internal electric source supply switch controlling signal just produces said internally voltage switch control signal after producing.
5. the method for a word-line signal of control one memory element in a power initiation program comprises:
Connection is from voltage to one current path of voltage internally externally;
Connecting after said voltage externally to the current path of said internally voltage, connect current path from external power source supply to an internal electric source supply; And
Connecting after said external power source supply to the current path of said internal electric source supply, a word line is maintained a normal manipulation mode.
6. method according to claim 5 also comprises internally voltage switch-over control signal of generation one, supplies to connect the current path from said voltage externally to said internally voltage.
7. method according to claim 6; Also comprise and produce an internal electric source supply switch controlling signal; Supply to connect current path from said external power source supply to said internal electric source supply; Wherein,, said internally voltage switch control signal just produces said internal electric source supply switch controlling signal after producing.
8. method according to claim 7; Wherein, The step that said word line is maintained said normal manipulation mode comprises generation one dump signal; The PMOS transistor between the input node that is coupling in a said external power source supply and a reverser is closed in confession, and said reverser responds an input signal and produces said word-line signal.
9. memory element comprises:
One dump control module supplies response one dump signal and produces one and draw signal on initial;
One dump is selected module, with said dump control module coupling, supplies to produce on one and draws signal, so that the power control response is drawn signal on said and produced a word-line signal that is positioned at a low logic state;
One first delay chain; Select the module coupling with said dump control module and said dump; The response of said first delay chain is said draws signal on initial and produces one first inhibit signal; And said first inhibit signal is sent to said dump selects module; Said dump is selected said first inhibit signal of module responds and is produced an internal electric source supply switch controlling signal, and the sequential of wherein said internal electric source supply switch controlling signal lags behind the sequential of drawing signal on said;
One second delay chain; Select the module coupling with said dump; Supply the said dump of response to select the M signal that module produced and produce one second inhibit signal; Said second inhibit signal feeds back to said dump and selects module, and to produce a voltage switch control signal internally, the sequential of wherein said internally voltage switch control signal lags behind the sequential of said internal electric source supply switch controlling signal; And
One code translator; Select the module coupling with said dump; Supply response to draw signal on said and with said word-line signal be pulled down to a low logic state, after said word-line signal has been pulled down to said low logic state; Respond said internal electric source supply switch controlling signal and cut off from the current path of external power source supply to an internal electric source supply; And after said external power source supply to the said current path of said internal electric source supply has been completely severed, responds said internally voltage switch control signal and cut off from voltage to one current path of voltage internally externally.
10. memory element according to claim 9; Comprise one first nmos pass transistor, said first nmos pass transistor has the one source pole that is connected to said voltage externally, is connected to a drain electrode of said code translator and a grid that receives said internally voltage switch control signal control through a load.
11. memory element according to claim 10, wherein, after seeing said dump signal off, said internally voltage switch control signal is positioned at a low logic state to close said first nmos pass transistor.
12. memory element according to claim 11, wherein, said code translator comprises a power supply unit switch, and confession responds said internal electric source supply switch controlling signal and produces an internal electric source supply voltage.
13. memory element according to claim 12; Wherein, Said power supply unit switch comprises one the one PMOS transistor, and a said PMOS transistor has the one source pole that is coupled to an external power source supply, a grid that receives said internal electric source supply switch controlling signal control and a drain electrode that is coupled to one first resistance string.
14. memory element according to claim 13, wherein, said code translator comprises one second resistance string, and said second resistance string has an input end that is coupled to a ground voltage control signal, and an output terminal that produces said internally voltage.
15. memory element according to claim 9, wherein, said code translator comprises a reverser, and said reverser has an output terminal that is coupled to a word line, and receives an input end of a decoded signal in order to the outside from said code translator.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/119,092 | 2008-05-12 | ||
| US12/119,092 US7663959B2 (en) | 2007-11-29 | 2008-05-12 | Power up/down sequence scheme for memory devices |
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| Publication Number | Publication Date |
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| CN101582293A CN101582293A (en) | 2009-11-18 |
| CN101582293B true CN101582293B (en) | 2012-05-30 |
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| TW (1) | TWI425520B (en) |
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| CN1232986A (en) * | 1998-01-29 | 1999-10-27 | 柯尼卡株式会社 | Lens-fitted film unit |
| US6281745B1 (en) * | 1999-09-01 | 2001-08-28 | Samsung Electronics Co., Ltd. | Internal power supply voltage generating circuit of semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101582293A (en) | 2009-11-18 |
| TWI425520B (en) | 2014-02-01 |
| TW200947453A (en) | 2009-11-16 |
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