CN101573974B - Hardware architecure for video conferencing - Google Patents
Hardware architecure for video conferencing Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/14—Session management
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/14—Systems for two-way working
- H04N7/15—Conference systems
- H04N7/152—Multipoint control units therefor
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/14—Systems for two-way working
- H04N7/15—Conference systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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Abstract
Video processing architectures, systems, and methods for a multipoint control unit are provided. In one example, a video processing system includes a motherboard and at least one daughterboard, each daughterboard having a plurality of processors interconnected via a daughterboard switch, where the daughterboard switch is configured to switch data between the plurality of processors and between themotherboard and daughterboard. The video processing system may further include a plurality of daughterboards each having an identical hardware and/or mechanical configuration. The plurality of daught erboards may be configured to be mechanically and electrically couplable together in any order, and may be stackable to form a series chain of daughterboards extending from the motherboard, each respective daughterboard switch being further configured to switch data to a daughterboard switch on another daughterboard to permit data flow along said series chain.
Description
Related application
The application relates to and requires GB patent application No.0623096.5,0623097.3,0623098.1 and 0623100.5 rights and interests, the exercise question of all these patent applications is " Hardware Architecture for Video Conference (hardware structure that is used for video conference) ", and submit on November 20th, 2006, for all purposes, mode by reference is herein incorporated all these patent applications.
Technical field
Present invention relates in general to be used for the hardware structure and the associated method of multipoint control unit.
Background technology
Video conference and associated hardware are divided into two camps substantially.In first camp, " meeting " only takes place between two participants, and the data network of participant by certain form is connected to each other directly.In the network of this form, only relate to two end points, and and if only if real meeting just takes place when being in two end points websites one in a plurality of participant.Under the situation of low side technology, the example of such meeting be to use such as
Or
The end points that enables of the PC of software interconnection, and for example under the situation of higher-end, be to use equipment via the dedicated endpoint hardware of isdn link interconnection.
In second camp, two of video conference permissions are mutual each other with upper extreme point.This realizes by the focal point that provides at least one to concentrate; These videos and audio stream are made up in the mode of expecting from the what is called " multipoint control unit (MCU) " of end points receiver, video and audio stream, and the Composite tone/video flowing of combination is retransferred to the participant.Usually, it is identical for each end points to send the meeting view of end points to.Should synthetic can change in time, but identical to all participants.
It is a prominent question that single synthesizing only is provided, and is adjusted to and can be flowed by the video conference that the end points of the lowest performance in the meeting is accepted because therefore each participant must receive.Therefore, in this case, many end points are not fully used, and may therefore experience the image and the audio frequency of deterioration.
Recently, such as Codian MCU
The modern MCU of series has been designed to allow for the view that each participant generates uniqueness (unique).This allows the over-all properties of each end points to be used, and also allows to synthesize at different participants' difference, so that the emphasis of the particular participant for example in meeting can be different for different user.Yet the real-time processing of video data is the task of high processor intensity.It also comprises moving of mass data.In case data have been extracted when carrying out high-quality processing, this is especially like this.Therefore, disposal ability and bandwidth constraint are remarkable bottlenecks in the generation of the high-quality video meeting MCU that allows a plurality of meeting views of generation.
Fig. 1 shows the MCU framework of typical prior art.This exemplary architecture has a plurality of digital signal processors 2 such as the TMS of Texas Instrument series, and they are via 4 interconnection of Time Division Multiplexing bus.Controller and network interface 6 also are connected to the TDM bus.Each DSP2 has been assigned with one or more time slots on the TDM bus.Should be appreciated that the TDM bus is significant bottleneck.Though can be implemented as MCU raising processing power by adding how powerful DSP or additional DSP, between the DSP and at the mobile a limited number of time slot that must be adapted on the TDM bus 4 of all data between network 8 and the DSP.Therefore, the general convergent-divergent of the framework of this form, and can't adapt to the processing requirements that each participant is synthesized.
Fig. 2 shows alternative prior art arrangement.In this example, each among a plurality of DSP 2-1 is connected to periphery component interconnection (PCI) bus 10-1.Similarly, a plurality of DSP 2-2,2-3 and 2-4 are connected to corresponding pci bus 10-2,10-3 and 10-4.Pci bus 10-2,10-3 and 10-4 and then be connected to further pci bus 14 via buffer 12.This framework is that DSP in group 2-1 can communicate each other than the remarkable advantage of framework shown in Figure 1, and unique bottleneck is pci bus 10-1.To group 2-2,2-3 and 2-4 also is like this.Yet,, must use pci bus 14 if the DSP in group 2-1 wishes to communicate by letter with for example DSP in group 2-3.Therefore, though this framework is significantly improved than framework shown in Figure 1 with regard to the ability of scalability and a plurality of DSP of effective use, but still pci bus 14 must be used for some combination that inner DSP communicates by letter, and therefore may become Limiting-Performance Factors for the MCU framework.
Made and to have handled from the trial of DSP unloading.For example, IDT generating portion number is " the preliminary treatment exchange (PPS) " of IDT 70K2000, is used for using with DSP.PPS carried out predetermined function before being delivered to such as DSP or FPGA.Determine to handle based on the address realm on the interchanger that is sent at bag.Chip is designed to for example use in the 3G phone, and is designed to for example from the common basic task of being carried out by the DSP less efficiently of DSP unloading.U.S. Patent No. 6,883,084 also suggestion use path processing; Yet in this case, it is suggested to substituting of von Neumann type sequence processor.
Summary of the invention
According to an aspect of the present invention, provide a kind of Video processing framework and system that is used for multipoint control unit.In one example, processing system for video comprises motherboard and at least one daughter board, each daughter board has a plurality of processors via daughter board interchanger interconnection, and wherein, the daughter board interchanger is configured at swap data between a plurality of processors and between motherboard and daughter board.In one example, processor comprises digital signal processor (DSP).
This processing system for video may further include a plurality of daughter boards, and each daughter board has identical hardware and/or mechanical arrangements.A plurality of daughter boards can be configured to can random order mechanically and electrically being coupled in together, and can be stackable, to form from the series chain of the daughter board of motherboard extension, each corresponding daughter board interchanger further is configured to data are exchanged to daughter board interchanger on another daughter board, to allow the data flow along described series chain.Motherboard may further include the motherboard interchanger that is arranged to swap data between a plurality of daughter boards.Motherboard interchanger and/or daughter board interchanger can comprise field programmable gate array to small part.
According to a further aspect in the invention, provide a kind of method that is used for handling video at multipoint control unit.Multipoint control unit can comprise motherboard and at least one daughter board, each daughter board in this at least one daughter board has a plurality of processors via the interconnection of daughter board interchanger, and this method is included between a plurality of processors that are associated with daughter board and swap data between motherboard and daughter board.This method may further include data are exchanged to daughter board interchanger on another daughter board, to allow along the data flow of the series chain of the stackable daughter board that extends from motherboard.
According to a further aspect in the invention, the processing system for video that is used for multipoint control unit comprises a plurality of processors of being suitable for carrying out to the processing of the data of representing video image, with a plurality of links of a plurality of processors interconnection (for example, at the physical link between the processor, switching fabric etc.) and the stream handle (for example, processor or processing unit) that is configured to processing said data when data are passed between a plurality of processors by link.
This stream handle can form the part of field programmable gate array.And, stream handle can be located on the field programmable gate array together or at the scene the memory outside the programmable gate array be associated.Stream handle can comprise predetermined logic, and by with one or two bit mask and data load in described memory, be programmable in operation to small part.
This stream handle can further can be operated the video flowing that passes processor is carried out bandwidth reduction and/or decompression.And stream handle can be associated with memory, and this memory can be operated and store the historical information relevant with the first forward part of the video flowing that passes processor.
According to a further aspect in the invention, provide a kind of method that is used for the video image through convergent-divergent is sent to the various objectives ground that is in different corresponding level of zoom.In one example, carry out this method via MCU with a plurality of processors, a plurality of processors can be operated the processing of carrying out the data of representing video image, a plurality of processors are by a plurality of link interconnects, and a plurality of stream handle can operate processing said data when data are passed between processor by a plurality of links.This method is included in the first-class processor in the stream handle desired first level of zoom in video data video scaling to the first destination, and use second stream handle with described video data zoom to subsequently be used for second destination second, littler level of zoom.This method may further include the network map of data that storage keeps represent the network topology of this framework, and makes convergent-divergent with reference to this map and determine.
According to a further aspect in the invention, a kind of processing system for video that is used for multipoint control unit comprises a plurality of processors, these a plurality of processors are suitable for carrying out the processing to the data of representing video image, these a plurality of processors interconnect via interchanger, and interchanger can be operated between the clean culture of the data that receive and the transmission of multicast forward direction and select.
This processing system for video may further include the topology storage, this topology storage comprises the data of representative in link between processors, and wherein, the storage of interchanger visit topology, determine to make route, and also between the unicast or multicast forward direction of data transmits, make a choice.In another example, processing system for video can comprise the topology storage, and this topology storage comprises the data of the link of representative between processor and controller; And controller, this controller can be operated before the data relevant with the expectation route of crossing over described link are transmitted routing iinformation is attached to described data.
According to a further aspect in the invention, provide a kind of method that is used at multipoint control unit route video data with a plurality of signal processors.This method comprises storage or retrieval network map, this network map keeps the data of representative with the network topology of signal processor interconnection, and optionally switch one or more in a plurality of interchangers, with according to network map with unicast or multicast pattern swap data between signal processor.This method may further include with unicast mode and transmits information until arriving the route origin that data need be advanced along a plurality of links at its place, and sentences the multicast pattern in this route origin then and transmit information.
In addition, provide a kind of coding to be useful in having the multipoint control unit of a plurality of signal processors the computer-readable medium of the computer program instructions of operation and route video data here.This computer program instructions can comprise the instruction that is used to carry out one or more methods described herein.
After the following description of having checked in conjunction with the accompanying drawings for specific embodiment of the present invention, other aspects and features of the present invention will become apparent for those skilled in the art.
Description of drawings
Fig. 1 is the schematic block diagram of the MCU framework of prior art;
Fig. 2 is the schematic block diagram of the MCU framework of the prior art that substitutes;
Fig. 3 is the schematic block diagram that illustrates according to motherboard and a plurality of daughter boards of an example of the present invention;
Fig. 4 is the schematic block diagram according to the daughter board of an example of the present invention; And
Fig. 5 illustrates the exemplary computer system that can be used to be implemented in the processing capacity among the embodiment mentioned herein.
Embodiment
Those of ordinary skill in the art presents following description, so that can make and use various aspects of the present invention and example.Description for particular device, technology and application only provides as example.Various modifications for example described herein will be conspicuous for those of ordinary skill in the art, and under the situation that does not break away from the spirit and scope of the present invention, defined herein General Principle can be applied to other examples and application.Therefore, of the present invention and be not intended to and be limited to example described herein and that illustrate, but should be endowed the scope consistent with claim.
With reference to figure 3, motherboard 20 has field programmable gate array (FPGA) and other assemblies that is associated.Motherboard 20 can comprise control circuit system, and control circuit system for example makes automatic value crewman (auto attendant) interface can be generated with the permission user and disposes MCU, and it also can control the data flow among the MCU.As known in the present technique, these assemblies can be alternatively on plate independently.
Motherboard 20 also comprises connector, and described connector allows to install one or more daughter boards 22.In one example, four daughter boards can be connected to motherboard 20.This connection for example can use pluggable connector to make.By using a plurality of such connectors, in a preferred embodiment, daughter board electrically couples and mechanically is installed to motherboard by such connector.
Motherboard 20 has FPGA 24, and FPGA 24 carries out routing function (except other functions).Mainly, FPGA 24 route data between controller (not shown), network interface (not shown) and a plurality of daughter board 22.In one example, FPGA 24 has four high-bandwidth link 26, and high-bandwidth link 26 can have for example 3Gb/ second or higher bandwidth, and motherboard 20 is connected with the ground floor of daughter board.Notice that link 26 (and hereinafter 38) can comprise physical link, switching fabric or be used to connect other suitable structures or the system of motherboard, daughter board and DSP.As hereinafter being explained in more detail, extremely the data flow of terminal daughter board is routed by the ground floor of daughter board.
In one example, and also with reference to figure 4, each daughter board 20 has four DSP 28, and each DSP 28 has the memory 30 that is associated.Each daughter board also has incorporates the FPGA 32 that interchanger 34 is arranged into.Interchanger 34 can comprise structure or the logic that is used for receiving in the input grouping, and with selectable mode for example with the similar mode of network switch, outwards send grouping.FPGA 32 comprises the stream handle of hereinafter describing in more detail 36 (for example, being configured to the processor or the processing unit of processing said data when data are passed between a plurality of processors by link), and two high-bandwidth link 38.
In one example, each of daughter board 22 is a machinery and electric identical, and link 38 can be used to be connected to another daughter board or motherboard 20.In this way, only just extra disposal ability can be added into this framework by adding other daughter board.In the configuration of minimum, single daughter board can be installed on the motherboard.In the configuration of maximum, in this example, four daughter boards can be installed in motherboard, and each daughter board can have stack other daughter board (being three in this example) thereon.As explained above, each daughter board itself can comprise four DSP, and therefore,, comprises in the configuration of four daughter boards that this configuration can have 64 DSP in this specific example.Certainly, can use the DSP and/or the daughter board of various numbers, and maximum configured is only with reference to the specific example of these 16 daughter boards, each daughter board comprises four DSP.
Can use several strategies, to eliminate the bandwidth congestion in link between the DSP or interconnection.In an illustrated examples, each link between daughter board or interconnection are with 3Gb/ second or higher bandwidth operation, and this bandwidth is higher than bandwidth of the prior art in fact.In addition, each daughter board can have four DSP, and four DSP share local interconnects, is communicating each other under the situation of the bandwidth of local interconnect on can any other interconnection in not using this framework.Therefore, utilize suitable resource allocation, can experience high usage the integral body of framework not being caused under the situation of remarkable bandwidth influence at the DSP on any daughter board.In addition, under the situation of the bandwidth of not using other branches to use, data can flow between the DSP in any one of four branches shown in Figure 3.
On the other hand with example in, each in the daughter board 22 comprises each the stream handle 36 that is arranged in daughter board FPGA 32.Stream handle 36 is configured to utilize the unusual feature of video conference as explained below, and can comprise any suitable processor or processing unit, this processor or processing unit are configured to processing said data when data are passed between a plurality of processors by link.
Usually, because the constraint of bandwidth, the data that flow between the end points in video conference for example, are had the end points of Internet connection by high compression.Yet this compression has prevented the manipulation to image usually.Therefore, in MCU inside, on incompressible data, carry out Video processing.Usually, this makes data volume increase with certain multiple between 10 to 100, and increases with about 80 multiple usually.Therefore, for example, typical video flowing can have the 50Mb/ bandwidth requirement of second.This is the peculiar prominent question of video conference, carries out because handle for many simultaneous streams, and executed in real time.Yet owing to the final result of handling will be transmitted with the form of compression, and also usually by lossy network, it is acceptable carrying out compression in MCU inside.Such compression can be loss-free, under the essential situation of given output network, is lossy perhaps.Therefore, in the example that is provided herein,, can alleviate the conventional bandwidth constraint in MCU by in MCU, carrying out compression and decompression in the data that transmit between the DSP.Yet this is expensive on calculating.Therefore, in the example that is provided herein, example system is included in the stream handle 36 that forms among each daughter board FPGA 32, and stream handle 36 can comprise any type of processing unit.When carrying out compression, Media Stream processor 36 can act on some pixels, and therefore, FPGA can preserve the part of frame or frame of video in associated memory 40, makes that the stream handle 36 in this pattern is not strictly to be stream handle.And stream handle 36 can comprise any suitable processor or the processing unit that is configured to processing said data when data are passed between a plurality of processors by link.
In another example, the data of going to some different DSP can be sent out with unicast format, and up to requiring route origin, in this case, some data can be sent out with the multicast form.This has been avoided a plurality of streams of identical data to pass through along same link.For example, if the daughter board 22 of the leftmost side of Fig. 3 wish with the daughter board 22 of the bottom of this figure ' on DSP communicate by letter, " communicate by letter; then data can be by clean culture; arrive motherboard 20 up to it; at this point, it can be multicasted to each of two corresponding branches of the daughter board that radiates from motherboard, and carries out clean culture along each branch then and also with daughter board 22 in the rightmost side of this figure.This step can be in FPGA 24 as its routing algorithm and carry out.In order to make this point easier, each interchanger can for example be safeguarded the representative of the topology of whole M CU framework with tree-shaped form, and can operate suitable multicast or the unicast format of controlling this tree and being identified for next jumping or a plurality of jumpings.Alternatively, this route can be determined in data source, and carries out decipher by interchanger on the way with the routing iinformation that data are carried.
Media Stream processor 36 also can use the factor convergent-divergent, to assist to reduce the communication bandwidth between DSP.For example, if the synthetic identical image that requires the different zoom version of different participants, such as shortening half into and shorten 1/4th into for another participant's image for participant's image, FPGA can be configured to make wise convergent-divergent decision.In this example, FPGA can shorten entire image into half, therefore the data that reduce are sent to route origin, this route origin is at the DSP that will handle described half image and will handle between the DSP of described 1/4th images and select, and this point, further image is dwindled into 1/4th, to forward to the DSP that handles this 1/4th downscaled images.
Carry out intelligent route, multicast and convergent-divergent/squeeze operation by each daughter board FPGA, and therefore, the processing that is used for these intelligent route decisions loads between each daughter board and distributes.
By this method, therefore, be dispensed to local DSP ideally by guaranteeing data, and must guarantee under situation about transmitting between the farther DSP that in data data transmit with effective form, above-mentioned framework can increase or maximize the utilization of DSP.In addition, by using the very high bandwidth link between DSP, greatly avoided bandwidth bottleneck.Therefore, this framework provides high-resolution height scalable and very powerful processing platform for each participant who constitutes many video conference sessions.
Certainly, other feature and advantage will be apparent for those skilled in the art.The system survey of front has been represented some exemplary realizations, but realize will be apparent for those skilled in the art for other, and all are so alternative that be considered to be equal to and in the spirit and scope of the present invention defined by the claims only.
Those skilled in the art will further recognize, according to circumstances use hardware, software, firmware or their combination can realize the operation of various embodiment.For example, use processor or other digital circuits under software, firmware or hard wire logic control can carry out some processing.(as carry out the function put down in writing those skilled in the art recognized, term herein " logic " refers to mounting hardware, FPGA (Field Programmable Gate Array) and/or their appropriate combination).Can be on computer-readable medium with software and firmware stores.As known for one of ordinary skill in the art, use analog circuit can realize some other processing.In addition, memory or other memories, and communications component can be used for embodiments of the invention.
Fig. 5 illustrates the typical computing system 500 that can be used to realize processing capacity in embodiments of the present invention.Such computing system can be used among for example MCU, controller, motherboard, daughter board or the DSP any one or a plurality of in.Those skilled in the relevant art also will recognize how to use other computer systems or framework to realize embodiments of the invention.Computing system 500 can comprise one or more processors, such as processor 504.Use universal or special processing engine (such as, for example microprocessor, microcontroller or other control logics) can realize processor 504.In this example, processor 504 is connected to bus 502 or other communication medias.
In alternate embodiment, information storage system 510 can comprise other similar assemblies, is used for allowing computer program or other instructions or data to be loaded into computing system 500.Such assembly can comprise, for example, removable memory cell 522 and interface 520, such as program cartridge and cassette memory interface, removable memory (for example, flash memory or other removable memory modules) and memory bank, and allow software and data to transfer to the removable memory cell 522 and the interface 520 of computing system 500 from removable memory cell 518.
In this document, term " computer program ", " computer-readable medium " etc. can be usually used for referring to such as for example medium of memory 508, memory device 518 or memory cell 522.These or other forms of computer-readable medium can be stored one or more instructions of using for processor 504, so that processor is carried out assigned operation.Such instruction is commonly referred to as " computer program code " (it can be grouped into form or other groupings of computer program), when being performed, makes computing system 500 can carry out the function of embodiments of the invention.Notice that code can directly make processor carry out assigned operation, compiled and carry out assigned operation, and/or carry out assigned operation with other softwares, hardware and/or firmware components (storehouse that for example, is used for the operative norm function) combination.
Using software to realize among the embodiment of element, use for example removable memory driver 514, driver 512 or communication interface 524, software can be stored in the computer-readable medium, and can be with software loading in computing system 500.Control logic (in this example, software instruction or computer program code) makes processor 504 carry out the function of embodiments of the invention as described herein when being carried out by processor 504.
Should be appreciated that top description has been described embodiments of the invention with reference to different function units and processor for purpose clearly.Yet, apparent, under the situation that does not break away from embodiments of the invention, can use any appropriate functional between different function units, processor or territory to distribute.For example, illustrated processor or the performed function of controller by separation can be carried out by identical processor or controller.Therefore, only should be regarded as for the quoting of the appropriate device of the function that is used to provide a description for quoting of specific functional units, but not strict logic OR physical structure or the tissue of expression.
Though described embodiments of the invention in conjunction with some embodiment, the present invention also is not intended to the particular form that is limited to this place elaboration.On the contrary, the scope of embodiments of the invention is only limited by claim.In addition, though seem and to describe feature in conjunction with specific embodiment, one of ordinary skill in the art appreciates that the various features of described embodiment can make up according to embodiments of the invention.
In addition, though list individually, multiple arrangement, element or method step can be realized by for example individual unit or processor.In addition, though individual characteristics may be comprised in the different claims, these may advantageously be made up, and comprise in different claims and do not hint that combination of features is infeasible and/or favourable.And the feature that comprises in the claim of a kind does not hint and is limited to this classification that on the contrary, according to circumstances, this feature can be applied to other claim classifications equally.
Claims (10)
1. processing system for video that is used for multipoint control unit, described processing system for video comprises:
Motherboard; And
A plurality of daughter boards, described a plurality of daughter board is stackable to form from the series chain of the daughter board of described motherboard extension, each daughter board has a plurality of processors via the interconnection of daughter board interchanger, described daughter board interchanger is configured to swap data between described a plurality of processors, between described motherboard and daughter board, and data are exchanged to daughter board interchanger on another daughter board to allow the data flow along described series chain.
2. processing system for video according to claim 1, wherein, each in described a plurality of daughter boards has identical hardware configuration.
3. processing system for video according to claim 1, wherein, each in described a plurality of daughter boards has identical mechanical arrangements.
4. processing system for video according to claim 1, wherein, described a plurality of daughter boards are configured to and can and electrically be coupled in together daughter board with any sequential machine ground.
5. processing system for video according to claim 1, wherein, described motherboard comprises the motherboard interchanger that is arranged to swap data between described a plurality of daughter boards.
6. processing system for video according to claim 5, wherein, described motherboard interchanger comprise field programmable gate array to small part.
7. processing system for video according to claim 1, wherein, described daughter board interchanger comprise field programmable gate array to small part.
8. processing system for video according to claim 1, wherein, described a plurality of processors comprise digital signal processor.
9. method that is used for handling video at multipoint control unit, described multipoint control unit has motherboard and a plurality of daughter board, described a plurality of daughter board is stackable to form from the series chain of the daughter board of described motherboard extension, each daughter board has a plurality of processors via the interconnection of daughter board interchanger, and described method comprises:
With described a plurality of processors that described daughter board is associated between, between described motherboard and daughter board swap data, and data are exchanged to daughter board interchanger on another daughter board to allow along the data flow of the series chain of described daughter board.
10. method according to claim 9, wherein, described motherboard comprises the motherboard interchanger, described motherboard interchanger can operate swap data between a plurality of daughter boards.
Applications Claiming Priority (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0623098A GB0623098D0 (en) | 2006-11-20 | 2006-11-20 | Hardware architecture for video conferencing |
| GB0623097.3 | 2006-11-20 | ||
| GB0623097A GB0623097D0 (en) | 2006-11-20 | 2006-11-20 | Hardware architecture for video conferencing |
| GB0623096.5 | 2006-11-20 | ||
| GB0623098.1 | 2006-11-20 | ||
| GB0623096A GB0623096D0 (en) | 2006-11-20 | 2006-11-20 | Hardware architecture for video conferencing |
| GB0623100A GB0623100D0 (en) | 2006-11-20 | 2006-11-20 | Hardware architecture for video conferencing |
| GB0623100.5 | 2006-11-20 | ||
| PCT/GB2007/004404 WO2008062164A2 (en) | 2006-11-20 | 2007-11-19 | Hardware architecure for video conferencing |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011100080977A Division CN102065270B (en) | 2006-11-20 | 2007-11-19 | Hardware architecture for video conferencing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101573974A CN101573974A (en) | 2009-11-04 |
| CN101573974B true CN101573974B (en) | 2011-07-13 |
Family
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| CN2007800492644A Active CN101573974B (en) | 2006-11-20 | 2007-11-19 | Hardware architecure for video conferencing |
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| CN (1) | CN101573974B (en) |
| GB (2) | GB0623100D0 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9179095B2 (en) | 2012-09-27 | 2015-11-03 | Avaya Inc. | Scalable multi-videoconferencing system |
| CN103034613A (en) * | 2012-12-12 | 2013-04-10 | 深圳市华力特电气股份有限公司 | Data communication method between processors and FPGA (field programmable gate array) equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1372416A (en) * | 2002-03-29 | 2002-10-02 | 武汉邮电科学研究院 | Soft exchange based video conference system multipoint controller |
| US6584077B1 (en) * | 1996-01-16 | 2003-06-24 | Tandberg Telecom As | Video teleconferencing system with digital transcoding |
| CN1553710A (en) * | 2003-06-05 | 2004-12-08 | 浙江南望图像信息产业有限公司 | Flow converting system and method for video frequency meet |
| US6883084B1 (en) * | 2001-07-25 | 2005-04-19 | University Of New Mexico | Reconfigurable data path processor |
| CN1805537A (en) * | 2005-01-05 | 2006-07-19 | 科点有限公司 | Video multi-conference unit (mcu) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993014459A1 (en) * | 1992-01-17 | 1993-07-22 | Caelum Research Corporation | Modular parallel processing system |
| US7136475B1 (en) * | 1999-07-27 | 2006-11-14 | Aspect Communications Corporation | Call Management system with call control from user workstation computers |
| WO2002057921A1 (en) * | 2001-01-19 | 2002-07-25 | Hitachi,Ltd | Electronic circuit device |
| CA2480081C (en) * | 2002-03-22 | 2007-06-19 | Michael F. Deering | Scalable high performance 3d graphics |
-
2006
- 2006-11-20 GB GB0623100A patent/GB0623100D0/en not_active Ceased
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2007
- 2007-11-19 CN CN2007800492644A patent/CN101573974B/en active Active
- 2007-11-20 GB GB0722698A patent/GB2443966B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6584077B1 (en) * | 1996-01-16 | 2003-06-24 | Tandberg Telecom As | Video teleconferencing system with digital transcoding |
| US6883084B1 (en) * | 2001-07-25 | 2005-04-19 | University Of New Mexico | Reconfigurable data path processor |
| CN1372416A (en) * | 2002-03-29 | 2002-10-02 | 武汉邮电科学研究院 | Soft exchange based video conference system multipoint controller |
| CN1553710A (en) * | 2003-06-05 | 2004-12-08 | 浙江南望图像信息产业有限公司 | Flow converting system and method for video frequency meet |
| CN1805537A (en) * | 2005-01-05 | 2006-07-19 | 科点有限公司 | Video multi-conference unit (mcu) |
Also Published As
| Publication number | Publication date |
|---|---|
| GB0722698D0 (en) | 2007-12-27 |
| GB2443966B (en) | 2009-01-07 |
| GB0623100D0 (en) | 2006-12-27 |
| CN101573974A (en) | 2009-11-04 |
| GB2443966A (en) | 2008-05-21 |
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