CN101572272B - Chemical vapor deposition manufacturing flow and pre-deposition layer structure of membrane transistor - Google Patents
Chemical vapor deposition manufacturing flow and pre-deposition layer structure of membrane transistor Download PDFInfo
- Publication number
- CN101572272B CN101572272B CN2008100278295A CN200810027829A CN101572272B CN 101572272 B CN101572272 B CN 101572272B CN 2008100278295 A CN2008100278295 A CN 2008100278295A CN 200810027829 A CN200810027829 A CN 200810027829A CN 101572272 B CN101572272 B CN 101572272B
- Authority
- CN
- China
- Prior art keywords
- silicon nitride
- layer
- nitride layer
- chamber
- deposition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention relates to a manufacturing flow and a pre-deposition layer structure of a membrane transistor, in particular to a chemical vapor deposition manufacturing flow and a pre-deposition layer structure of a membrane transistor. A substrate is transmitted to a loading cavity of a machine board; and after vacuum pumping and heating, a step of pre-deposition is firstly carried out on a processing procedure of a cavity loading table, and then subsequent chemical vapor deposition of the membrane transistor is carried out. A pre-deposition layer can comprise multilayered deposition of silicon nitride and amorphous silicon so as to effectively prevent influencing the electrical characteristics of the membrane transistor by washing residual fluorine, chlorine, adulterants, and the like in the cavity.
Description
Technical field
The present invention relates generally to a kind of thin-film transistor and makes flow process and preliminary sedimentation lamination structure thereof, especially flow process and preliminary sedimentation lamination structure thereof are made in the chemical vapour deposition (CVD) that refers to a kind of thin-film transistor, utilize pre-deposition and prevent that residue influences the electrical characteristic person of the thin-film transistor in the chamber.
Background technology
See also shown in Figure 1, it mainly is the conductive pattern eucalyptus layer that at first forms an one source pole (source) 12 and a drain (drain) 14 on a glass substrate 10, and the surface forms a n+ doped amorphous silicon (n+doped amorphous silicon respectively on source electrode 12 and drain 14; N+a-Si) layer 125,145;
Afterwards, on unitary construction, cover an amorphous silicon (amorphous silicon; A-Si) layer 17 and one silicon nitride (silicon nitride; SiNx) layer 18; Between source electrode 12 on the silicon nitride layer 18 and drain 14 positions, form the conductive pattern of a gate (gate) 16 at last.
Wherein, amorphous silicon (a-Si) layer 17 is a semiconductor layer, and 18 on silicon nitride (SiNx) layer is a dielectric layer.When gate 16 applies a voltage, can form a passage in the semiconductor layer of amorphous silicon layer 17 formations, make source electrode 12 become a conductive path for 14 of drains.
Generally speaking, n+ doped amorphous silicon layer 125,145, amorphous silicon layer 17 and silicon nitride layer 18 are to adopt plasma enhanced chemical vapor deposition (Plasma EnhancedChemical Vapor Deposition in the thin-film transistor structure; PECVD) system grows up, and its board is generally collection clump formula framework.
See also shown in Figure 2, it is mainly constructed is to include one first to be written into chamber (loadingchamber) 20, one second and to be written into chamber 21, a heated chamber (heating chamber) 22,1 first process chamber (process chamber) 23,1 second process chamber 24, one the 3rd process chamber 25 and a transfer chamber (transfer chamber) 26, in this transfer chamber 26 and be provided with a mechanical arm (robot) 27;
Wherein, this first is written into chamber 20 and second is written into chamber 22 main systems in order to glass substrate is written in the board with this, and implements the program that vacuumizes, makes this first year eight chamber 20 and this second be written into and reach the required pressure of processing procedure in the chamber 22;
After evacuation is finished, utilize this mechanical arm 27 in this transfer chamber 26 that this glass substrate 10 is sent to this heated chamber 22 and heat, use the hydrone of removing glass substrate 10 surface attachment; After heating is finished, with this mechanical arm 27 this glass substrate 10 is sent to this first process chamber 23, this second process chamber 24 and the 3rd process chamber 25 respectively again, carry out the plasma enhanced chemical vapor deposition of each layer structure respectively, as n+ doped amorphous silicon layer 125,145, amorphous silicon layer 17 and silicon nitride layer 18 or the like;
After each processing procedure is finished, again this glass substrate 10 is sent to this and first is written into chamber 20 and this second and is written into chamber 22, this glass substrate 10 can be taken out behind the vacuum breaker.
See also shown in Figure 3ly, its step of making flow process at first is written into chamber for the gia glass substrate is sent to this, as step 301; After being written into this glass substrate, implement evacuation, make this be written into and reduce to the required pressure of processing procedure in the chamber, as step 303;
After pressure is reached demand, utilize this mechanical arm that this glass substrate is sent to this heated chamber, as step 305; In this heated chamber, this glass substrate is heated, use and remove the hydrone that is attached to this glass baseplate surface, as step 307;
Afterwards, be formal thin film deposition, with this mechanical arm this glass substrate is sent to the material deposition that each process chamber is scheduled to respectively, the amorphous silicon deposition of carrying out the n+ doping for example in this first process chamber, carry out the deposition of amorphous silicon layer in this second process chamber, the 3rd process chamber then carries out the deposition of silicon nitride layer, as step 309;
After film growth is finished, this glass substrate is sent to this is written into chamber, as step 311; In being written into chamber, this lowers the temperature and the vacuum breaker program, as step 313; Then be that this glass substrate that will finish processing procedure takes out at last, as step 315; And carry out the work of this chamber clean (clean), be beneficial to carrying out of successive process, as step 317.
Generally after chemical vapor deposition process, need carry out the cleaning procedure of chamber, use that previous processing procedure material residual in the chamber is removed.Cleaning process mainly is to feed purge gas (cleaninggas), as fluorine-based (Fluorine-base; F-base) or chloro (Chlorine-base; Cl-base) gas carries out electric paste etching (plasma etch).
Yet which kind of cleaning way no matter all can have residual (the dopant residues) of residual fluorine or chlorine or other alloys unavoidably.And these residues are easy to cause the remnant ionic soil in chemical vapor deposition process, make the element of follow-up film forming produce defective (defect), electrically also can cause adverse influence for thin-film transistor element.
Summary of the invention
The present invention's main purpose is, provides a kind of chemical vapour deposition (CVD) of thin-film transistor to make flow process, and it mainly is to utilize a pre-deposition program, uses and gets rid of the residual person of foreign matter.
Another object of the present invention is, provides a kind of chemical vapour deposition (CVD) of thin-film transistor to make flow process, and it mainly is to utilize a pre-deposition program, and can optimize the electrical characteristic person of the thin-film transistor element.
The present invention's another purpose is, provides a kind of chemical vapour deposition (CVD) of thin-film transistor to make flow process, and the multilayer deposition can be adopted by its pre-deposition program system, uses and improves the effect that foreign matter is got rid of or covered.
The present invention's another purpose is, provides a kind of chemical vapour deposition (CVD) of thin-film transistor to make flow process, and its preliminary sedimentation lamination can include an at least one silicon nitride layer and an amorphous silicon layer person.
The present invention's another purpose is, provides a kind of chemical vapour deposition (CVD) of thin-film transistor to make flow process, and its pre-deposition series of strata are silicon nitride layer, amorphous silicon layer, the three-decker person of the silicon nitride layer.
The present invention's another purpose is, provides a kind of chemical vapour deposition (CVD) of thin-film transistor to make flow process, and its pre-deposition series of strata are dielectric layer, semiconductor layer, the three-decker person of the dielectric layer.
For reaching above-mentioned purpose, the technical solution adopted in the present invention is: a kind of preliminary sedimentation lamination structure is provided, and it mainly is to include: one first silicon nitride layer is formed on one of the process chamber plummer; One amorphous silicon layer is formed on this first silicon nitride layer; And one second silicon nitride layer, be formed on this amorphous silicon layer.
The present invention still provides the chemical vapour deposition (CVD) of thin-film transistor to make flow process, and its key step includes: at least one substrate is sent to one of board by a tool is written into chamber; This is written into chamber is evacuated to a predetermined pressure; Substrate is heated to a predetermined temperature; The plurality of process chamber is carried out the step of a pre-deposition; Substrate is orderly sent to each process chamber, and carries out each deposition step of thin-film transistor in each process chamber respectively; Substrate is sent to this is written into chamber; And carry out the step of vacuum breaker, and substrate is sent back in this tool.
Beneficial effect of the present invention is, provide a kind of chemical vapour deposition (CVD) of thin-film transistor to make flow process and preliminary sedimentation lamination structure thereof, it mainly lies in the chamber that is written into that substrate is sent to board, after vacuumizing and heating, earlier the process chamber plummer is carried out the step of a pre-deposition, carry out the chemical vapour deposition (CVD) of follow-up thin-film transistor again; The preliminary sedimentation lamination can include layer deposition more than silicon nitride and the amorphous silicon, can effectively prevent to clean in the chamber residual fluorine, chlorine and alloy etc. influence the electrical characteristic person's of thin-film transistor effect.
Description of drawings
Fig. 1 is the organigram of a thin-film transistor
Fig. 2 is the schematic diagram of collection clump formula framework board
Fig. 3 is the chemical vapour deposition (CVD) flow chart of known thin-film transistor
Fig. 4 is the structure and the plummer schematic diagram of the thin-film transistor of the present invention's one better embodiment
Fig. 5 is the local enlarged diagram of preliminary sedimentation lamination structure shown in Figure 4
Fig. 6 is the schematic diagram of the batch board of the present invention's one better embodiment use
Fig. 7 is the making flow chart of the present invention's one better embodiment
Fig. 8 is the pre-deposition flow chart of the present invention's one better embodiment
Embodiment
At first, see also shown in Figure 4, the present invention's making flow process, main system is prior to forming a pre-deposition (pre-deposition) layer 75 on the plummer 70 of board process chamber; The making flow process of this preliminary sedimentation lamination 75, can be in the pre-deposition program residual (the dopant residues) of residual (the Fluorineor Chlorine residues) of the fluorine or chlorine of previous processing procedure and cleaning procedure or other alloys be got rid of, or covered, can effectively completely cut off thin-film transistor (the Thin Film Transistor of retained foreign body to chemical vapour deposition (CVD) (Chemical VaporDeposition) film forming; TFT) harmful effect of element;
Finish after the preliminary sedimentation lamination 75 of this plummer 70, again this glass substrate 40 is written in the process chamber of board and carries out follow-up thin-film transistor deposition formation.
Present embodiment is the conductive pattern eucalyptus layer prior to formation one gate (gate) 46 on the glass substrate 40, and covers a silicon nitride (silicon nitride on gate 46 and glass substrate 40; SiNx) layer 445.Cover an amorphous silicon (amorphous silicon in these gate 46 top positions afterwards; A-Si) layer 47 and one n+ doped amorphous silicon (n+doped amorphous silicon; N+a-Si) layer 48;
This source electrode (source) 42 and 44 of drains (drain) are covered in n+ doped amorphous silicon layer 48 tops and both sides respectively, and the surface forms an insulating protective layer 425 respectively on source electrode 42 and drain 44 at last;
Wherein, this amorphous silicon (a-Si) layer 47 is a semiconductor layer, and 445 on this silicon nitride (SiNx) layer is a dielectric layer; When this gate 46 applies a voltage, can form a passage in the semiconductor layer of these amorphous silicon layer 47 formations, make this source electrode 42 become a conductive path for 44 of this drains.
See also shown in Figure 5ly, the preferred construction of this preliminary sedimentation lamination 75 of the present invention is a multilayer preliminary sedimentation lamination; Wherein, the three-decker with dielectric layer, semiconductor layer, dielectric layer is the best; Wherein, the gross thickness h of three-decker should be controlled in 200 how in the rice (nm); Wherein, the gross thickness h of three-decker again with less than 100 how rice be preferable.
Present embodiment system adopts ground floor and is this silicon nitride (SiNx) layer 751, and the second layer is that this amorphous silicon (a-Si) layer is the structure of this silicon nitride layer 755 for 753, the three layers; Can effectively get rid of, isolated or fluorine (F), chlorine (Cl) or other alloys residual that cover previous processing procedure, these plummer 70 surfaces of good dielectricity are provided for follow-up film forming processing procedure.
In the present invention's the thin-film transistor structure, each element all adopts plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition; PECVD) system grows up, and can adopt the board of batch (batch type) framework.
See also shown in Figure 6, the main structure system of its batch board 60 includes one and is written into chamber (loadingand lock chamber) 62, one plural process chamber (process chamber) 66 and one transfer chamber (transfer chamber) 64, in this transfer chamber 64 and be provided with a mechanical arm (robot) 67;
Wherein, this is written in chamber 62 and this each process chamber 66 and all is provided with a plurality of plummers 621,70, in order to carry a plurality of glass substrates 40; Because a chamber all can hold a plurality of glass substrates 40 simultaneously and carry out processing procedure simultaneously, the production capacity of its equipment processing procedure can significantly improve.
This be written into chamber 62 be in order to this glass substrate 40 by being written into board in the tool (cassette), and be positioned over respectively in each plummer 621; After this glass substrate 40 was written into, the program of implementing earlier to vacuumize made this be written into reaching the required pressure of processing procedure in the chamber 62; After evacuation is finished, then be heated to the program of predetermined temperature, and this each process chamber 66 is carried out pre-deposition;
After pre-deposition is finished, utilize this mechanical arm 67 in this transfer chamber 64 that this glass substrate 40 is orderly sent to this each process chamber 66 again, and be positioned on this plummer 70 of correspondence; This each process chamber 66 carries out the plasma enhanced chemical vapor deposition (PECVD) of each layer structure respectively, as this gate 46, this silicon nitride layer 445, this amorphous silicon layer 47, this n+ doped amorphous silicon layer 48, this source electrode 42, this drain 44 and this insulating protective layer 425 or the like.
After each processing procedure is finished, again this glass substrate 40 is sent to this and is written in the chamber 62, lower the temperature and vacuum breaker after this glass substrate 40 can be taken out.
See also shown in Figure 7ly, the step that the present invention makes flow process at first is written into chamber 62 for a plurality of glass substrates 40 are sent to this, as step 701; After this is written into glass substrate 40, implement evacuation, make this be written into and reduce to the required pressure of processing procedure in the chamber 62, as step 703; Again,
After pressure is reached demand, begin to heat this glass substrate 40 and make it the process temperatures that reaches predetermined, can remove the hydrone that is attached to glass baseplate surface simultaneously, as step 705; After heating is finished, can begin this each process chamber 66 is implemented the pre-deposition flow process, on this plummer 70, form a preliminary sedimentation lamination 75 respectively, as step 707; Again,
After finishing pre-deposition, be the thin film deposition of formal element; With this mechanical arm 67 this glass substrate 40 is sent to the material deposition that this each process chamber 66 is scheduled to respectively, for example this gate 46, this silicon nitride layer 445, this amorphous silicon layer 47, this n+ doped amorphous silicon layer 48, this source electrode 42, this drain 44 and this insulating protective layer 425 or the like are as step 709; Again,
After film growth is finished, this glass substrate 40 is sent to this is written into chamber 62, as step 711; In being written into chamber 62, this lowers the temperature and the vacuum breaker program, as step 713; Then be that this glass substrate 40 that will finish processing procedure takes out at last, and place back in the tool, as step 715; Need carry out the work of this chamber clean (clean) in addition, be beneficial to carrying out of successive process, as step 717.
See also shown in the 8th figure, because the present invention's pre-deposition series of strata are preferable with multilayer preliminary sedimentation lamination effect, wherein, the fruit with three layers of preliminary sedimentation lamination of dielectric layer, semiconductor layer, dielectric layer is the best again.The pre-deposition flow process system of its best as shown in the figure.
Pre-deposition one silicon nitride layer 751 on this plummer 70 of this each process chamber 66 at first is as the ground floor dielectric layer, as step 771; Pre-deposition forms an amorphous silicon layer 753 on this silicon nitride layer 751 again, as semi-conductor layer, as step 773; At last, pre-deposition and form a silicon nitride layer 755 on this amorphous silicon layer 753 then, and finish three layers of preliminary sedimentation laminations structure of dielectric layer, semiconductor layer, dielectric layer, as step 775.
Wherein, predetermined pressure in the pre-deposition flow process needs between 0.2 to 3.0 person of outstanding talent's crust (mbar) or between 1.0～2.0 milli-torrs (mTorr), and with between 0.4 to 2.0 person of outstanding talent's crust or be the best between 1.2～1.5 milli-torrs (mTorr).The predetermined temperature of pre-deposition flow process needs between 100 to 400 degree Celsius.
The film forming procedure of ground floor silicon nitride layer 751, amorphous silicon layer 753 and second layer silicon nitride layer 755 needs to import silane (SiH4), ammonia (NH3), hydrogen (H2), nitrous oxide (N20) and nitrogen (N2) in each process chamber 66.And in respectively being written into chamber 66, importing an electric slurry source radio-frequency power (RFPower), this electricity slurry source radio-frequency power system is preferable less than 2000 watts (W).
Through experiment confirm, the thin-film transistor that the present invention's making flow process is produced has the quite electrical characteristic of excellence compared to general production procedure person.
Aforementioned the present invention's making flow process also can be used in the formula framework board of gathering together as shown in Figure 2, or in order to make thin-film transistor as shown in Figure 1, all can significantly improve the electrical characteristic of thin-film transistor.
The above person, only be one of the present invention better embodiment, it is not the scope that is used for limiting the invention process, be all, all should be included in the present invention's the Shen claim scope according to impartial for it variation of the described shape of claim of the present invention, structure, feature, method and spiritual institute and modification.
Claims (15)
1. a preliminary sedimentation lamination is constructed, and it consists predominantly of: one first silicon nitride layer, an amorphous silicon layer and one second silicon nitride layer; It is characterized in that this first silicon nitride layer is formed on the plummer of a process chamber; This amorphous silicon layer is formed on this first silicon nitride layer; This second silicon nitride layer is formed on this amorphous silicon layer.
2. preliminary sedimentation lamination according to claim 1 structure, wherein, this first silicon nitride layer, amorphous silicon layer and the second silicon nitride layer gross thickness are less than 200 rice how.
3. preliminary sedimentation lamination according to claim 2 structure, wherein, the gross thickness of this first silicon nitride layer, amorphous silicon layer and second silicon nitride layer is less than 100 rice how.
4. flow process is made in the chemical vapour deposition (CVD) of a membrane transistor, it is characterized in that its key step includes:
At least one substrate is sent to one of a board by a tool is written into chamber;
This is written into chamber is evacuated to a predetermined pressure, this predetermined pressure is between 0.2 to 3.0 person of outstanding talent's crust or between 1.0～2.0 milli-torrs (mTorr);
Substrate is heated to a predetermined temperature, and this predetermined temperature is between 100 to 400 degree Celsius;
The plurality of process chamber is carried out the step of a pre-deposition, wherein this pre-deposition step is to deposit one first silicon nitride layer earlier on a plurality of plummers of each process chamber, form an amorphous silicon layer again on this first silicon nitride layer, form one second silicon nitride layer at last on this amorphous silicon layer;
Substrate is orderly sent to each process chamber, and carries out each deposition step of membrane transistor in each process chamber respectively;
Substrate is sent to this is written into chamber; And
Carry out the step of vacuum breaker, and substrate is sent back in this tool.
5. making flow process according to claim 4, wherein, this predetermined pressure is with between 0.4 to 2.0 person of outstanding talent's crust or between 1.2～1.5 milli-torrs (mTorr).
6. making flow process according to claim 4, wherein, the deposition step of this first silicon nitride includes:
Import silane, ammonia, hydrogen, nitrous oxide and nitrogen in each process chamber;
Import an electric slurry source radio-frequency power in each process chamber; And
Form this first silicon nitride layer.
7. making flow process according to claim 6, wherein, this electricity slurry source radio-frequency power is less than 2000 watts.
8. making flow process according to claim 4, wherein this amorphous silicon deposition step includes:
Import silane, ammonia, hydrogen, nitrous oxide and nitrogen in each process chamber;
Import an electric slurry source radio-frequency power in each process chamber; And
Form this amorphous silicon layer.
9. making flow process according to claim 8, wherein, this electricity slurry source radio-frequency power is less than 2000 watts.
10. making flow process according to claim 4, wherein, this second silicon nitride deposition step includes:
Import silane, ammonia, hydrogen, nitrous oxide and nitrogen in each process chamber;
Import an electric slurry source radio-frequency power in each process chamber; And
Form this second silicon nitride layer.
11. making flow process according to claim 10, wherein, this electricity slurry source radio-frequency power is less than 2000 watts.
12. making flow process according to claim 4, wherein, in this pre-deposition step, the gross thickness of this first silicon nitride layer, amorphous silicon layer and second silicon nitride layer is less than 200 rice how.
13. making flow process according to claim 4, wherein, the gross thickness of this first silicon nitride layer, amorphous silicon layer and second silicon nitride layer is less than 100 rice how.
14. making flow process according to claim 4, wherein, this making flow process still includes the cleaning step of each chamber.
15. making flow process according to claim 4, wherein this board is a batch type board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100278295A CN101572272B (en) | 2008-04-30 | 2008-04-30 | Chemical vapor deposition manufacturing flow and pre-deposition layer structure of membrane transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100278295A CN101572272B (en) | 2008-04-30 | 2008-04-30 | Chemical vapor deposition manufacturing flow and pre-deposition layer structure of membrane transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101572272A CN101572272A (en) | 2009-11-04 |
| CN101572272B true CN101572272B (en) | 2011-10-26 |
Family
ID=41231563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100278295A Active CN101572272B (en) | 2008-04-30 | 2008-04-30 | Chemical vapor deposition manufacturing flow and pre-deposition layer structure of membrane transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101572272B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107527864B (en) * | 2017-08-31 | 2019-03-12 | 长江存储科技有限责任公司 | A kind of memory device, tungsten forming core layer and preparation method thereof |
| CN111485224A (en) * | 2019-01-29 | 2020-08-04 | 北京石墨烯研究院 | Chemical vapor deposition apparatus |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1440081A (en) * | 1994-10-20 | 2003-09-03 | 株式会社半导体能源研究所 | Semiconductor device and manufacture thereof |
| CN1467303A (en) * | 2002-07-09 | 2004-01-14 | 统宝光电股份有限公司 | Method for depositing film using plasma chemical gas phase deposition method |
| CN1963996A (en) * | 2006-11-24 | 2007-05-16 | 哈尔滨工业大学 | A method for orientation growth of VO2 film of pulse laser deposition Si base |
-
2008
- 2008-04-30 CN CN2008100278295A patent/CN101572272B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1440081A (en) * | 1994-10-20 | 2003-09-03 | 株式会社半导体能源研究所 | Semiconductor device and manufacture thereof |
| CN1467303A (en) * | 2002-07-09 | 2004-01-14 | 统宝光电股份有限公司 | Method for depositing film using plasma chemical gas phase deposition method |
| CN1963996A (en) * | 2006-11-24 | 2007-05-16 | 哈尔滨工业大学 | A method for orientation growth of VO2 film of pulse laser deposition Si base |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101572272A (en) | 2009-11-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105679665B (en) | Non-crystalline silicon A-si seasoning effect for improving sin run-to-run uniformity | |
| US9287137B2 (en) | Methods for depositing a silicon containing layer with argon gas dilution | |
| WO2010141814A2 (en) | Passivation process for solar cell fabrication | |
| JP2011527826A (en) | Solar cell and method and apparatus for forming the same | |
| TW200840071A (en) | Multi-junction solar cells and methods and apparatuses for forming the same | |
| KR20100095426A (en) | Plasma treatment between deposition processes | |
| CN103972327A (en) | In situ silicon surface pre-cleaning for high performance passivation of silicon solar cells | |
| JPH04266019A (en) | Film formation | |
| WO2012057906A1 (en) | A surface treatment process performed on a transparent conductive oxide layer for solar cell applications | |
| CN101572272B (en) | Chemical vapor deposition manufacturing flow and pre-deposition layer structure of membrane transistor | |
| CN102629555B (en) | Gate insulation layer and preparation method thereof, TFT and preparation method thereof, array substrate and display device | |
| JPWO2010023948A1 (en) | Photoelectric conversion device manufacturing method, photoelectric conversion device, and photoelectric conversion device manufacturing system | |
| KR20090091819A (en) | Method for silicon thin film formation | |
| US9224783B2 (en) | Plasma densification of dielectrics for improved dielectric loss tangent | |
| CN112349792B (en) | Monocrystalline silicon passivation contact structure and preparation method thereof | |
| CN101740498B (en) | Semiconductor device with contact etching stop layer and forming method thereof | |
| Higashi et al. | Low-Temperature Formation of Device-Quality SiO2/Si Interfaces Using Electron Cyclotron Resonance Plasma-Enhanced Chemical Vapor Deposition | |
| KR101031759B1 (en) | Method for crystallizing of Si, and methode for fabricating of poly-TFT | |
| US20160240708A1 (en) | Solar cell with a hetero-junction structure and method for manufacturing the same | |
| CN101487114B (en) | Low temperature polysilicon thin-film device and method of manufacturing the same | |
| KR20190101880A (en) | Method and apparatus for forming silicon film, germanium film, or silicon germanium film | |
| CN102420131B (en) | Silicon wafer back silicon nitride growth method integrated in FEOL (front end of line) | |
| JP3272681B2 (en) | Solar cell manufacturing method | |
| CN104465346A (en) | Grid electrode forming method | |
| TWI481042B (en) | Manufacturing method of poly silicon based thin film applied on solar cell |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |