CN101567760A - System for generating low density parity check codes - Google Patents

Abstract

The invention discloses a system for generating low density parity check codes. A method for reliably carrying out communication and supporting communications such as live satellites and data services through a satellite (111) is disclosed. An input message is coded to generate code message of structured low density parity check codes (LDPC). The coded message is modulated according to a high-order modulation solution which has a signal star sign representing a signal point, for example, 8-PSK and 16-QAM have more than two signs. The system comprises emitter (200) configured to broadcast the modulated signals through the satellite (111). The method is particularly suitable for a communication system with a limited bandwidth but requiring a high data rate.

Description

Utilize the satellite communication system of low density parity check code

The application is that application number is 03132884.9, and the applying date is on July 24th, 2003, and denomination of invention is divided an application for the patent application of " utilizing the satellite communication system of low density parity check code ".

Technical field

The present invention relates to communication system, more particularly, relate to a kind of satellite communication system of utilizing the linear block coding techniques.

Background technology

Satellite communication system is supported the feasible solution of every broadband services and is occurred as a kind of.In itself, can provide reliable communication in order to make satellite communication system in noisy communication channel, modulation and coding method with high power efficiency and bandwidth efficiency are sought after.These communication channels show a kind of fixing ability, and it can be represented as under given signal to noise ratio, the bit number of every hertz of per second (bps/Hz), this parameter-definition a theoretic upper limit [being called mountain farming (Shannon) limit].Therefore, code Design is a target with the speed that realization approaches this mountain farming limit.A kind of can be exactly low-density checksum (LDPC) sign indicating number near this category code of the mountain farming limit.

From traditionally,, make the LDPC sign indicating number not be widely used as yet owing to there are many shortcomings.Wherein, a shortcoming is exactly that the LDPC coding techniques is a high complexity.Use the generator matrix to come the LDPC sign indicating number encoded and to need to store very large, a non-sparse matrix.In addition, the LDPC sign indicating number requires big data block to become effectively; Thereby, even the parity matrix of LDPC sign indicating number is sparse, stores these matrixes and remain problematic.From the angle of implementing, storage problem is the major reason why the LDPC sign indicating number is generally promoted in practice as yet.In LDPC sign indicating number implementation procedure one main challenge is exactly how to realize connecting network between the several processing engine (node) in decoder.

Consumers are to the demand of more and more higher data rate, for example, and for the volatile growth of every broadband services has been facilitated in the multimedia application of supporting them (such as video flowing, surf the web, or the like).Therefore, communication service providers need a kind of infrastructure that can support high data rate, particularly in the system of limited bandwidth.The high order modulation technique of two above bits of each symbols carry can provide more efficiently bandwidth availability ratio such as 8-phase shift keying (8-PSK) and 16-quadrature amplitude modulation (16-QAM).Unfortunately, conventional LDPC communication system is used a kind of modulation scheme of carrying binary system or quaternary modulation, and the signal waveform of its representative information is diametical (anti-podal), perhaps mutually orthogonal with binary system.

Therefore, need a kind of satellite communication system of using simple Code And Decode to handle, can make simultaneously cost minimization.This also needs to use effectively the LDPC sign indicating number, to support high data rate, does not introduce bigger complexity simultaneously.Also need in system's (for example satellite communication system) of a limited bandwidth, improve power efficiency and bandwidth efficiency.

Summary of the invention

These and other demands are all given to solve by the present invention, wherein, a kind of method is provided, be used to utilize structured low density parity check (LDPC) sign indicating number, and in conjunction with the high order modulation scheme with each signal constellation (in digital modulation) via satellite communication system communicate, above-mentioned each signal constellation (in digital modulation) all has the two or more symbols (symbol) by a signaling point (signalling point) expression.By parity matrix being defined as the triangle of Lower Half, provide the structure of LDPC sign indicating number.This method can advantageously be utilized the unequal error protection ability of LDPC sign indicating number to each bit of being sent out; so that to high order modulation scheme, provide extra error protection such as each bit of the comparison fragility of 8-phase shift keying (8-PSK) and 16-quadrature amplitude modulation (16-QAM).Said method provides a kind of modulation technique with high bandwidth efficiency and power efficiency, and they are applicable to direct broadcasting satellite or wideband satellite communication well.According to every link parameter of whole system, this method can realize high power efficiency and/or bandwidth efficiency with the simple decoding hardware that can carry out high-speed computation.

An aspect according to an embodiment of the invention, disclose a kind ofly be used on satellite, communicating reliably, to support the method for communication service.This method comprises: input message is encoded, so that the low-density checksum of export structureization (LDPC) coded message.This method also comprises according to a kind of high order modulation scheme, the message of having encoded is modulated, and send modulated signal via satellite.

Another aspect according to an embodiment of the invention, disclose a kind ofly on satellite, communicate reliably, to support the ICBM SHF satellite terminal of communication service.This terminal comprises an encoder, and it is configured in response to input message, the low-density checksum of export structureization (LDPC) coded message.This terminal also comprises a modulator, and it is configured to according to high order modulation scheme the message of having encoded be modulated, and wherein, modulated signal is sent out via satellite.

Another aspect according to an embodiment of the invention discloses a kind of satellite communication system of supporting communication service.This system comprises one first terminal, it is configured to input message is encoded, and with low-density checksum (LDPC) coded message of export structureization, and according to high order modulation scheme the message of having encoded is modulated, wherein, modulated signal is sent out via satellite.Equally, native system comprises one second terminal, and it is configured to receive the signal that sends via satellite.

Another aspect according to an embodiment of the invention, disclose a kind ofly on satellite, communicate reliably, to support the system of communication service.This system comprises: be used for input message is encoded, so that the low-density checksum of export structureization (LDPC) coded message, and according to a kind of high order modulation scheme, the device that the message of having encoded is modulated, above-mentioned high order modulation scheme has a signal constellation (in digital modulation), and on behalf of each signaling point, it plural symbol is arranged.This system also comprises transmitter, and it is configured to propagate via satellite modulated signal.

From following detailed description, by some certain embodiments of diagram and embodiment, comprise being conceived to be used to carry out optimal mode of the present invention that will make other aspects of the present invention, it is more obvious that feature and advantage become.Under the prerequisite that does not deviate from spirit of the present invention and scope, the present invention that can also comprise other with different embodiment, and some details are made amendment aspect tangible at each.Correspondingly, from nature, accompanying drawing and explanation all are considered to illustrative, rather than restrictive.

Description of drawings

In each view of accompanying drawing, by means of example, rather than, the present invention is described, and therein, identical reference number refers to similar elements by means of restriction, in the accompanying drawings:

Figure 1A and 1B are respectively figure according to an embodiment of the invention, that be configured the communication system of using low-density checksum (LDPC) sign indicating number, and use LDPC encodes, can provide the figure of the satellite communication system of high data rate;

Fig. 2 is the figure of the exemplary transmitter in the system of Figure 1A;

Fig. 3 is the figure of the exemplary receiver in the system of Figure 1A;

Fig. 4 is in according to one embodiment of present invention, the figure of a sparse parity matrix;

Fig. 5 is the figure that two parts of LDPC sign indicating number of the matrix of Fig. 4 constitute;

Fig. 6 is the figure of a submatrix of a sparse parity matrix according to an embodiment of the invention, and wherein, this submatrix contains the parity check numerical value of the delta-shaped region that only limits to Lower Half;

Fig. 7 is the expression code that uses unconfined parity matrix (H matrix) to the performance figure relatively between the code of the constrained H matrix with submatrix as shown in Figure 6;

Fig. 8 A and 8B are respectively the figure of a non-Gray 8-phase shift keying modulation scheme, and the figure of a Gray 8-phase shift keying modulation scheme, and each in the middle of them may be used among the system of Figure 1A;

Fig. 9 is that expression uses the code of Gray's mark to the figure relatively of the performance between the code of non-Gray's mark;

Figure 10 is in according to one embodiment of present invention, uses the workflow diagram of the LDPC decoder of non-gray mappings;

Figure 11 is in being illustrated in according to one embodiment of present invention, the flow chart of the working condition of the LDPC decoder of use gray mappings;

Figure 12 A-12C is in according to one embodiment of present invention, the interactive figure between each check-node and each bit node;

Figure 13 A-13C is illustrated in according among each embodiment of the present invention, the simulation result of each the LDPC sign indicating number that is produced;

During Figure 14 A-14B is illustrated respectively in according to one embodiment of present invention, be configured in order to support the structuring access, with the top sides edge of the memory that is implemented in the randomness in the LDPC coding and the figure on bottom sides edge;

Figure 15 is the performance figure relatively that the LDPC coding of different encoding schemes is adopted in expression;

Figure 16 is in being illustrated in according to one embodiment of present invention, can carry out the figure of the computer system that the Code And Decode of LDPC sign indicating number handles.

Embodiment

The system, method and the software that are used for producing effectively structurized low-density checksum (LDPC) sign indicating number are described below.In the following description, for illustrative purposes, many specific details will be enumerated, so that provide to thorough of the present invention.Yet, apparent for a person skilled in the art, when enforcement is of the present invention, can perhaps take a kind of design arrangement of equivalence without these specific details.In other each examples, represent some well-known construction and devices with the form of block diagram, unclear to avoid that the present invention is thickened.

Figure 1A is figure according to an embodiment of the invention, that be configured to use the communication system of low-density checksum (LDPC) sign indicating number.Digital communication system 100 comprises transmitter 101, and it produces various signal waveforms, is sent to receiver 105 by a communication channel 103.In this discrete communication system 100, transmitter 101 has a message source, and it produces a discrete set of various possible message; In the various possible message each all has a corresponding waveform.These signal waveforms are decayed by communication channel 103, or are changed.In order to overcome the noise in channel 103, used the LDPC sign indicating number.

Can under the condition that does not cause any performance loss, realize the high speed embodiment by the LDPC sign indicating number that transmitter 101 produces.Avoid distributing check-node (check node) in a small amount from the structurized LDPC sign indicating number of transmitter 101 outputs, because used modulation scheme (for example, the 8-phase shift keying) makes each bit node occur channel error code easily to each bit node (bit node).

But such LDPC sign indicating number has a kind of decoding algorithm (being different from the turbo sign indicating number) of parallelization, and advantageously it relates to such as addition, comparison and such simple operation of tabling look-up.And well-designed various LDPC sign indicating numbers can not show the flat any sign of error code.

According to one embodiment of present invention, transmitter 101 uses a kind of relatively simple coding techniques, produces the LDPC sign indicating number based on each parity matrix (it helps effective memory access in decode procedure), so that communicate with receiver 105.Transmitter 101 uses the LDPC sign indicating numbers, as long as the length of piece is enough big, and their on performance, all be better than linking together turbo+RS (Read-Solomon) sign indicating numbers of (concatenated).

Figure 1B represents according to one embodiment of present invention, uses LDPC to encode, can provide the figure of a satellite communication system of high data rate.Satellite system 110 uses the LDPC sign indicating numbers to support, for example, and 111 data and telephone service via satellite.Satellite 111 has the load (not shown), comprising a demodulator, in order to from each ICBM SHF satellite terminal (ST) 113,115 signals that receive carry out demodulation, a switch (not shown) is sent to a suitable transponder (not shown) with demodulated signal, and a modulator (not shown), it is modulated the signal from switch, so that transmit by the transponder (not shown).Equally, ST 103 can be used as a central station (or Network Operation Centre), and its manages the access of communicating by letter, safety and charging with ST 115.

Modulator and demodulator uses low-density checksum (LDPC) sign indicating number, by utilizing a kind of structurized LDPC scheme and in conjunction with the modulation scheme of high-order-according to one embodiment of present invention, support high data rate, modulation scheme can be 8-phase shift keying (8-PSK) or 16-quadrature amplitude modulation (16-QAM).

Can come arrangement satellite system 110 like this, to support multiple application and configuration: directly video broadcasting; Very low pore size satellite (VSAT) type system; And handle satellite on the star.Under directly video broadcasting and VSAT disposed, satellite 110 showed as a repeater system, handled communication service with the switch of design arrangement and use in its load of handling satellite on the clock star.

For example, in order to support direct broadcasting satellite (DBS) provider, system 110 can from as the central station 113 of front end to each ICBM SHF satellite terminal 115 broadcast TV program, each ICBM SHF satellite terminal 115 can contain a set-top box 117, in order to television indicator 119 interfaces.Concerning direct broadcasting satellite or broadband satellite application, power efficiency and bandwidth efficiency all are important.From traditionally, research and develop the multiple scheme that using form is encoded or the turbo form is encoded and supported above-mentioned various satellite application, attempt to realize high power efficiency and bandwidth efficiency.These encoding schemes have been brought bigger complexity.Compare therewith, the LDPC coding can be issued to high power efficiency and bandwidth efficiency in the condition that does not increase complexity, thereby reduces cost.Concerning the link (for example being used for those links that broadband satellite is used) of high speed, the LDPC scheme can make itself enter parallel execution mode, and in the technology of form coding or turbo form coding (trellis coding), this will be exceedingly difficult.

On star in the processing configuration, the switch that resides among the satellite 111 is a fast packet switching machine; For example, an ATM(Asynchronous Transfer Mode) switch, a gigabit Ethernet switch, a frame relay switch, or the like.Being included among the load is a processor, and it is carried out such as every capacity management function and the such function of every safety function.

According to one embodiment of present invention, the LDPC sign indicating number that satellite communication system 110 will have high power efficiency combines with high order modulation scheme, is used for broadband satellite and uses.High order modulation scheme is supported a kind of signal constellation (in digital modulation) (constellation), and it uses each signaling point to represent two signaling points that above symbol is such, such as 8-PSK or 16-QAM.Under higher signal noise ratio (SNR), the LDPC sign indicating number can provide the performance that is better than the turbo form type code, and does not have perceptible error code flat (error floor).According to one embodiment of present invention, with the outer sign indicating number of a kind of Read-Solomon (RS) the LDPC sign indicating number is coupled together and to obtain bigger throughput.Yet the LDPC sign indicating number does not need (for example, with the outer sign indicating number of RS) to connect, and in the turbo sign indicating number, need satisfy the requirement of digital video broadcasting usually with the outer sign indicating number of RS.In other words, can replace outside RS sign indicating number, perhaps fully phase out outside RS sign indicating number with a kind of relatively simple code.Therefore, only need parity check symbol seldom, perhaps they can be cancelled from transmission.As a result of this specific function, typically data throughout can be improved about 5-7%.

Also have, under higher bit rate, the LDPC decoder implements than the turbo decoder and wants much simple.But the LDPC decoder also has a kind of architecture of height parallelization, makes itself can carry out high-speed computation.

At first cataloged procedure is described below, and in Fig. 3, the LDPC decoder is described with reference to Fig. 2.

Fig. 2 is the figure of an exemplary transmitter in the system of Figure 1A.A LDPC encoder 203 has been installed in transmitter 200, and it accepts input from information source 201, and exports the encoding stream with high redundancy degree, is suitable for carrying out in receiver 105 correction process.Information source 201 produces k group signal from a discrete alphabetical X.Specify each LDPC sign indicating number with each parity matrix.On the other hand, the coding of LDPC sign indicating number need be specified the generator matrix usually.Even might use Gaussian reduction to obtain the generator matrix from each parity matrix, resulting matrix will no longer be sparse, and it may be complicated storing a big generator matrix simultaneously.

Encoder 203 uses a kind of simple coding techniques to produce each signal from alphabetical Y, is sent to modulator 205, and above-mentioned coding techniques only uses parity matrix, and its method is that structure is put on parity matrix.Specifically, be defined as triangle, this parity matrix is applied a kind of constraints by certain part with this matrix.In Fig. 6, will a kind of like this structure of parity matrix be described more fully below.The performance loss that a kind of like this constraint is brought is negligible, therefore, forms a kind of attractive compromise.

The message that modulator 205 will have been encoded is mapped to the signal waveform that is sent to transmitting antenna 207 from encoder 203, and transmitting antenna 207 is launched these waveforms on communication channel 103.The message of correspondingly, having encoded is modulated and be assigned to transmitting antenna 207.Transmission from transmitting antenna 207 propagates into a receiver, and this will discuss below.

Fig. 3 is the figure of an exemplary receiver in the system of Figure 1A.Receiving a side, receiver 300 comprises a demodulator 301, and it carries out demodulation to the signal that has received from transmitter 200.These signals are received at reception antenna 303 places and are used for demodulation.Through after the demodulation, the signal that has received is sent to a decoder 305, and it produces message X ' by combining with a bit metric generator (bit metric generator) 307, attempts the original source message of reconstruct.Under the condition of non-gray mappings, bit metric generator 307 (iterates ground) repeatedly with decoder 305 exchange probabilistic informations in decode procedure, and this will be described in detail in Figure 10.Can supply alternatively, if use gray mappings (according to one embodiment of present invention), then once enough by bit metric generator 307, therein, after the LDPC decoder iterated each time, the further trial that bit metric produces may only produce limited improvement in performance; Below in conjunction with Figure 11 this method is described more fully.In order to understand all benefits provided by the present invention, how the investigation LDPC sign indicating number of advising returning home greatly produces, as discussing among Fig. 4.

Fig. 4 is in according to one embodiment of present invention, the figure of a sparse parity matrix.The LDPC sign indicating number is to have sparse parity check matrix H _{(n-k) x n}Length, linear block codes.Typically, the length n of piece is in the scope of bit from thousands of to tens thousand of.For example, being used for length n=8 of LDPC sign indicating number and speed is that 1/2 parity matrix is shown in Fig. 4.The figure that same code can be equivalently constitutes with two parts of Fig. 5 represents.

Fig. 5 is the figure that two parts of LDPC sign indicating number of the matrix of Fig. 4 constitute.The parity check equation formula is implying such meaning, that is, concerning each check-node, all each adjacent bit nodes [on Galois territory (GF) (2)] sum equals zero.As what seen in the drawings, each bit node occupies the left side of figure, and is associated with one or more check-nodes according to a kind of predetermined relation.For example, corresponding to check-node m ₁, concerning each bit node, following expression formula is set up:

n ₁+n ₄+n ₅+n ₈＝0

Get back to receiver 303, the LDPC decoder is considered to a message by the type decoder, and thus, decoder 305 is a target with the numerical value that finds each bit node.In order to finish this task, each bit node communicates mutually repeatedly with each check-node.The characteristic of this communication will be illustrated below.

To each bit node, each check-node all provides based on a kind of estimation (" suggestion ") about the numerical value of this bit node from the information of other adjacent each bit nodes to an adjacent bit node from each check-node.For example, in above-mentioned example, if for m ₁, n ₄, n ₅And n ₈Sum " seems " 0, then m ₁Will be to n ₁Show n ₁Numerical value (because the n that will be considered to 0 ₁+ n ₄+ n ₅+ n ₈=0); Otherwise, m ₁Will be to n ₁Show n ₁Numerical value will be considered to 1.In addition, concerning soft judgement decoding, increased the reliability measure.

To each check-node, each bit node is all retransmitted based on a kind of estimation about itself numerical value of feedback of other adjacent each check-nodes from it to an adjacent check-node from each bit node.In above-mentioned example, n ₁Have only two adjacent check-node m ₁And m ₃If from m ₃To n ₁Feedback show n ₁Numerical value may be 0, n then ₁To notify m ₁: n ₁Numerical value itself be estimated as 0.The situation that check-node adjacent more than two is arranged for this bit node, bit node is before the check-node report judged result of communication with it, bit node will carry out the voting that once the minority is subordinate to the majority (soft judgement) based on the feedback of other each adjacent check-nodes from it.Repeat said process, till all bit nodes all are considered to correctly (that is, satisfying all parity check equation formulas), perhaps until reaching predetermined maximum iterative times, till declaration is once decoded and failed thus.

Fig. 6 is the figure of a submatrix of a sparse parity matrix according to an embodiment of the invention, and wherein, this submatrix contains the parity check numerical value of the delta-shaped region that only limits to Lower Half.As mentioned above, each numerical value of the delta-shaped region of the Lower Half by limiting parity matrix, (Fig. 2's) encoder 203 just can use a kind of simple coding techniques.According to one embodiment of present invention, the constraints that parity matrix applied is had following form:

H _(n-k)xn＝[A _(n-k)xkB _(n-k)x(n-k)]

In the formula, B is the delta-shaped region of Lower Half.

Any block of information i=(i ₀, i ₁..., i _K-1) all use Hc ^T=0 is encoded as a code word c=(i ₀, i ₁..., i _K-1, p ₀, p ₁..., p _N-k-1), and recursively find the solution each parity check bit; For example,

$a_{00}{\mathrm{<figure-callout\; id="0"\; label="i"\; filenames="A20091020385500311.png,A20091020385500313.png"\; state="\{\{state\}\}">i</figure-callout>}}_0+a_{01}{\mathrm{<figure-callout\; id="1"\; label="i"\; filenames="A20091020385500311.png,A20091020385500312.png"\; state="\{\{state\}\}">i</figure-callout>}}_1+...+a_{0,k-1}{i}_{k-1}+{\mathrm{<figure-callout\; id="0"\; label="p"\; filenames="A20091020385500311.png,A20091020385500313.png"\; state="\{\{state\}\}">p</figure-callout>}}_0=0\&DoubleRightArrow;$ Find the solution p ₀

$a_{10}{\mathrm{<figure-callout\; id="0"\; label="i"\; filenames="A20091020385500311.png,A20091020385500313.png"\; state="\{\{state\}\}">i</figure-callout>}}_0+a_{11}{i}_1+...+a_{1,k-1}{\stackrel{\&CenterDot;}{i}}_{k-1}+b_{10}{\mathrm{<figure-callout\; id="0"\; label="p"\; filenames="A20091020385500311.png,A20091020385500313.png"\; state="\{\{state\}\}">p</figure-callout>}}_0+{\mathrm{<figure-callout\; id="1"\; label="p"\; filenames="A20091020385500311.png,A20091020385500312.png"\; state="\{\{state\}\}">p</figure-callout>}}_1=0\&DoubleRightArrow;$ Find the solution p ₁

To p ₂, p ₃..., p _N-k-1, method for solving similarly.

Fig. 7 is that expression uses the code of unconfined parity matrix (H matrix) to the figure relatively of performance between the code of constrained H matrix shown in Figure 6.The figure shows two kinds of performances between the LDPC sign indicating number relatively: a kind of have a common parity matrix, and another kind then has one and only limits to the leg-of-mutton parity matrix of Lower Half, so that simplify coding.The employed encoding scheme of this emulation is 8-PSK.Performance loss is in 0.1dB.Therefore, based on the constraints of the leg-of-mutton H matrix of Lower Half, performance loss can be ignored, and the benefit that the simplification of coding techniques brings is significant.Therefore, be expert at and/or be listed as and be equivalent to a Lower Half triangle in arranging or the leg-of-mutton any parity matrix of the first half may be used to identical purpose.

Fig. 8 A and 8B are respectively the figure of a non-Gray 8-phase shift keying modulation scheme, and the figure of a Gray 8-phase shift keying modulation scheme, and each in the middle of them may be used among the system of Figure 1A.The non-Gray 8-phase shift keying modulation scheme of Fig. 8 A can be used for the receiver of Fig. 3, so that the system of the very low frame error rate (FER) of requirement is provided.Shown in Fig. 8 B, by using a kind of Gray 8-phase shift keying modulation scheme, and with a kind of such as Bao Si (Bose), Chu Heli (Chaudhuri) and He Kunhan (Hocq uenghem) (BCH), Hamming (hamming), Read-Solomon (Reed-Solomon) (RS) the such outer sign indicating number of sign indicating number combine, also can satisfy this requirement.

Can realize the Gray 8-phase shift keying scheme of Fig. 8 B with a kind of outer sign indicating number for alternatively.In suc scheme, need between LDPC decoder 305 (Fig. 3) and the bit metric generator 307 that can use 8-PSK to modulate, not iterate.Outside not possessing under the situation of sign indicating number, it is flat to use the LDPC decoder 305 of Gray's mark to present a kind of error code early, as following shown in Figure 9.

Fig. 9 is the figure that the code of the use Gray mark of presentation graphs 8A and 8B compares the performance between the code of no Gray's mark.Suppose the correct feedback of existence from LDPC decoder 305, all follow non-Gray's mark far apart owing to have these two kinds of 8-PSK symbols of two known bits, so it will be more accurate adopting the regeneration of bit metric of the 8-PSK of non-Gray's mark, error code is flat to be exactly to derive from this fact.This also can be regarded as under the condition that works in higher signal to noise ratio (snr) equivalently.Therefore, even the error asymptote of the identical LDPC sign indicating number of the Gray who uses or non-Gray's mark (labeling) has same slope (that is, parallel to each other), have that of non-Gray's mark is a kind of can both to pass through the lower frame error rate under any signal to noise ratio.

On the other hand, for those systems that do not require the extremely low frame error rate, because before the LDPC decoder iterates each time, the regeneration of 8-PSK bit metric all brings additional complexity, so, will be more suitable between LDPC decoder 305 and 8-PSK bit metric generator 307 without any the Gray's mark that iterates.And when using Gray's mark, before the LDPC decoder iterated each time, the regeneration of 8-PSK bit metric only produced very faint improvement in performance.As previously mentioned, as long as outer sign indicating number is achieved, the Gray's mark that does not iterate just can be applied to require those systems of extremely low FER.

The characteristic of LDPC sign indicating number is also depended in selection between Gray's mark and the non-Gray's mark.Typically, because under the condition of non-Gray's mark, the order of node is high more, just big more from the deterioration degree of the initial feedback of LDPC decoder 305 to 8-PSK (the perhaps modulation system of similar higher order) bit metric generator 307, so, the order of bit node or check-node is high more, and the effect of Gray's mark is just good more.

When 8-PSK (perhaps similar higher order) modulation was used with binary decoder, people recognized that 3 (or more) bits of a symbol are not received under " impartial noise " condition.For example, under the condition of Gray 8-PSK mark, the 3rd bit that enters a symbol of decoder is considered to be higher than other two bits on noise level.Therefore, in LDPC sign indicating number design, do not distribute edge (edge) in a small amount, make that those bits are unlikely and be in double minus advantage to those each bit nodes by " noise level is higher " the 3rd bit representative of 8-PSK symbol.

Figure 10 is in according to one embodiment of present invention, uses the workflow diagram of the LDPC decoder of non-gray mappings.In this scheme, LDPC decoder and bit metric generator alternately iterate.In this example, use the 8-PSK modulation, yet identical principle also can be applied to other various high order modulation schemes.In this case, suppose distance vector d of demodulator 301 output, each symbolic point that contains noise that its expression has received and to the distance between the 8-PSK symbolic point of bit metric generator 307, thus, each component of vector is represented as:

$d_i=-\frac{E_s}{N_0}\{{(r_x-s_{i,x})}^2+{(r_y-s_{i,y})}^2\},i=\mathrm{0,1},...7.$

8-PSK bit metric generator 307 communicates with LDPC decoder 305, so that exchange priori probability information and posterior probability information, they are represented as u and a respectively.In other words, vector u and a represent the prior probability and the posterior probability of the log-likelihood ratio value of each bit of having encoded respectively.

8-PSK bit metric generator 307 is that the method for the priori likelihood score ratio that produces of each group of 3 bits is as follows.At first, obtain extrinsic information about each bit of having encoded:

e _j＝a _j-u _j j＝0，1，2

Secondly, determine 8-PSK symbol probability P _iI=0,1 ..., 7.

^＊y _j＝-f(0，e _j) j＝0，1，2

In the formula, and f (a, b)=max (a, b)+LUT _f(a b), has again,

LUT _f(a，b)＝ln(1+e ^-|a-b|)

^*x _j＝y _j+e _j j＝0，1，2

^*p ₀＝x ₀+x ₁+x ₂ p ₄＝y ₀+x ₁+x ₂

p ₁＝x ₀+x ₁+y ₂ p ₅＝y ₀+x ₁+y ₂

p ₂＝x ₀+y ₁+x ₂ p ₆＝y ₀+y ₁+x ₂

p ₃＝x ₀+y ₁+y ₂ p ₇＝y ₀+y ₁+y ₂

Secondly, the log-likelihood ratio value of the priori of bit metric generator 307 definite each bit of having encoded, as the input of being sent to LDPC decoder 305, its expression formula is as follows:

u ₀＝f(d ₀+p ₀，d ₁+p ₁，d ₂+p ₂，d ₃+p ₃)-f(d ₄+p ₄，d ₅+p ₅，d ₆+p ₆，d ₇+p ₇)-e ₀

u ₁＝f(d ₀+p ₀，d ₁+p ₁，d ₄+p ₄，d ₅+p ₅)-f(d ₂+p ₂，d ₃+p ₃，d ₆+p ₆，d ₇+p ₇)-e ₁

u ₂＝f(d ₀+p ₀，d ₂+p ₂，d ₄+p ₄，d ₆+p ₆)-f(d ₁+p ₁，d ₃+p ₃，d ₅+p ₅，d ₇+p ₇)-e ₂

Be noted that and estimate function f (.) with recursive fashion with two above variablees; For example, and f (a, b, c)=f (f (a, b), c).

The working condition of the LDPC decoder 305 that uses non-gray mappings is described now.In step 1001, before carrying out iterating the first time according to following expression formula (and shown in Figure 12 A), the log-likelihood ratio value of each bit v that 305 pairs of LDPC decoders have been encoded is carried out initialization:

$v_{n\&RightArrow;k_i}=u_n,$ N=0,1 ..., N-1, i=1,2 ..., deg (bit node n)

Here,

Its adjacent check-node k is sent in expression from bit node n _iMessage, u _nExpression is at the demodulator output of bit n, and N is the size of code word.

In step 1003, k upgrades to check-node, and thus, input v produces output w.Shown in Figure 12 B, from its d _cThe message that individual adjacent bit node is sent to the arrival of check-node k is represented as ${\mathrm{<figure-callout\; id="1"\; label="v\; n"\; filenames="A20091020385500311.png,A20091020385500312.png"\; state="\{\{state\}\}">v</figure-callout>}}_{n_{}},{\mathrm{<figure-callout\; id="2"\; label="v\; n"\; filenames="A20091020385500311.png,A20091020385500312.png"\; state="\{\{state\}\}">v</figure-callout>}}_{n_{}},...,v_{n_{\mathrm{dc}}\&RightArrow;k}.$ Its target is to calculate to turn back to d from check-node k _cThe output message of individual adjacent bit node.These message are represented as $w_{k\&RightArrow;{\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="A20091020385500311.png,A20091020385500312.png"\; state="\{\{state\}\}">n</figure-callout>}}_1},w_{k\&RightArrow;{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="A20091020385500311.png,A20091020385500312.png"\; state="\{\{state\}\}">n</figure-callout>}}_2},...,w_{k\&RightArrow;n_{\mathrm{dc}}},$ In the formula

$w_{k{\&RightArrow;n}_i}=g({\mathrm{<figure-callout\; id="1"\; label="v\; n"\; filenames="A20091020385500311.png,A20091020385500312.png"\; state="\{\{state\}\}">v</figure-callout>}}_{n_{}},{\mathrm{<figure-callout\; id="2"\; label="v\; n"\; filenames="A20091020385500311.png,A20091020385500312.png"\; state="\{\{state\}\}">v</figure-callout>}}_{n_{}},....,v_{n_{i-1}\&RightArrow;k},v_{n_{i+1}\&RightArrow;k},....,v_{n_{\mathrm{dc}}\&RightArrow;k}).$

The definition of function g () is provided by following formula:

g(a，b)＝sign(a)×sign(b)×{min(|a|，|b|)}+LUT _g(a，b)，

In the formula, LUT _g(a, b)=ln (1+e ^{-| a+b}|)-ln (1+e ^{-| a-b|}).Similar with function f, can estimate function g with recursive fashion with two above variablees.

Once more, in each step 1005, decoder 305 is all exported a posterior probability information (Figure 12 C), makes:

$a_n=u_n+\underset{j}{\mathrm{\&Sigma;}}{w}_{k_j\&RightArrow;n}$

In each step 1007, determine whether to satisfy all parity check equation formulas.If do not satisfy these parity check equation formulas, then in step 1009, decoder 305 is derived 8-PSK bit metric and channel input u again _nThen, shown in step 1011, this bit node is upgraded.Shown in Figure 13 C, from d _vThe message that individual adjacent check-node is sent to the arrival of bit node n is represented as ${\mathrm{<figure-callout\; id="1"\; label="w\; k"\; filenames="A20091020385500311.png,A20091020385500312.png"\; state="\{\{state\}\}">w</figure-callout>}}_{k_{}},{\mathrm{<figure-callout\; id="2"\; label="w\; k"\; filenames="A20091020385500311.png,A20091020385500312.png"\; state="\{\{state\}\}">w</figure-callout>}}_{k_{}},....,w_{k_{\mathrm{dv}}\&RightArrow;n}.$ Calculated and sent back to d from the message of sending outside of bit node n _vIndividual adjacent check-node; These message are represented as $v_{n\&RightArrow;{\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="A20091020385500311.png,A20091020385500312.png"\; state="\{\{state\}\}">k</figure-callout>}}_1},v_{n\&RightArrow;{\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="A20091020385500311.png,A20091020385500312.png"\; state="\{\{state\}\}">k</figure-callout>}}_2},....,v_{n\&RightArrow;k_{\mathrm{dv}}},$ Computing formula is as follows:

$v_{n\&RightArrow;k_i}=u_n+\underset{j\&NotEqual;i}{\mathrm{\&Sigma;}}{w}_{k_j\&RightArrow;n}$

In step 1013, decoder 305 output hard judged results (under the situation that satisfies all parity check equation formulas):

${\hat{c}}_n=\left\{\begin{array}{cc}0,& a_n\&GreaterEqual;0\\ 1,& a_n<0\end{array}\right.$

If $H{\hat{c}}^T=0,$ Then stop.

When using non-Gray's mark, such scheme is suitable.Yet, when adopting Gray's mark, should carry out the processing procedure of Figure 11.

Figure 11 is in being illustrated in according to one embodiment of present invention, the flow chart of the working condition of the LDPC decoder of Fig. 3 of use gray mappings.When using Gray's mark, because after the LDPC decoder iterated each time, the regeneration of each bit metric can only produce inappreciable improvement in performance, so before the LDPC decoder iterated, each bit metric was advantageously only produced once.Shown in the step 1001 among Figure 10 and 1003, the initialization of the log-likelihood ratio value of each the bit v that has encoded, and in each step 1101 and 1103, all carry out the renewal of check-node.Subsequently, shown in step 1105, carry out the renewal of bit node n.After this, a decoder output posterior probability information (step 1107).In step 1109, determine whether to satisfy all parity check equation formulas; If satisfy, then decoder is exported hard judged result (step 1111).Otherwise, repeated execution of steps 1103-1107.

Figure 13 A-13C is illustrated in according among each embodiment of the present invention the figure of the simulation result of each the LDPC sign indicating number that is produced.Particularly, Figure 13 A-13C represents to have the modulation of higher order and code check is 3/4 (QPSK, 1.485 bit/symbol), 2/3 (8-PSK, 1.980 bit/symbol), and each LDPC sign indicating number of 5/6 (8-PSK, 2.474 bit/symbol) performance.

In order to realize interconnected between each check-node and each bit node, there are two kinds of global schemas: the scheme that (1) is parallel entirely, and (2) partly parallel scheme, in complete parallel architecture, all nodes and interconnected between them are all realized with physics mode.The advantage of this architecture is speed.

Yet complete parallel architecture is realizing may relating to bigger complexity on all nodes and interconnected between them.Therefore, in complete parallel architecture, can require less block size, so that reduce complexity.In this case, concerning identical clock frequency, may cause the proportional reduction aspect throughput, and in FER some decline to the aspect of performance of Es/No.

The second kind of scheme that realizes the LDPC sign indicating number is exactly only to realize from physics on a subclass of node sum, and only uses this a limited number of " physics " node to handle all " function " nodes of this code.Even can make the computing of LDPC decoder become extreme simple, and can carry out with parallel mode, but how still exist the further challenge that between each bit node that " randomly " distributes and each check-node, establishes a communications link in design.According to one embodiment of present invention, the decoder 305 of Fig. 3 is by going reference to storage to solve this problem in a kind of structurized mode, so that realize a kind of lip-deep random code.With reference to Figure 14 A and 14B, this scheme is described below.

Figure 14 A and 14B are respectively the structure charts on edge, memory top and bottom sides edge, and according to one embodiment of present invention, this memory is supported the structuring access, to realize the randomness of LDPC coding.Can be by concentrating on the generation of parity matrix, just can the implementation structure access, and needn't sacrifice the performance of real random code.In general, can specify a parity matrix by each check-node and being connected of each bit node.For example, each bit node is divided into per 392 one group (392 are used for illustration purpose) herein.And, for instance, suppose that with order be that each check-node that first bit node of 3 is connected is numbered as a, b and c, each check-node that is connected with second bit node just is numbered as a+p so, b+p and c+p, each check-node that is connected with the 3rd bit node just is numbered as a+2p, b+2p and c+2p, or the like.For 392 bit nodes of next group, each check-node that is connected with first bit node is different from a, b, and c, thus by selecting suitable p, make all check-nodes all have identical order.To each freely constant carry out random search, thereby final LDPC sign indicating number is exactly cycle-4 and cycle-6 freely.

Above-mentioned arrangement helps the memory access in processing procedure of check-node and bit node.In the figure that these two parts constitute, the numerical value at each edge can be stored in storage medium, for example among the random-access memory (ram).Should be noted in the discussion above that and to conduct interviews singly with the numerical value of random fashion each edge for the sign indicating number of LDPC at random real in check-node and the bit node processing procedure.Yet it is too slow that this access mode just seems for high data rate applications.The RAM of Figure 14 A and 14B is formed in such a way, and it places very big one group of relevant edge within the clock cycle; Correspondingly, these numerical value will be placed " together " in memory.What can see is, in fact, for one group of check-node (and each bit node), even adopt real random code, relevant edge numerical value also can side by side be deposited in RAM, but among the dependence edge adjacent with one group of bit node (and each check-node) will be distributed in RAM randomly along numerical value.Therefore, " together " of indication of the present invention comes from the design of parity matrix itself.That is to say that the design of check matrix has guaranteed that the dependence edge of one group of bit node and check-node is along side by side being put together in RAM.

Shown in Figure 14 A and 14B, each frame all contains the numerical value at an edge, and it is many bits (for example, 6 bits).According to one embodiment of present invention, edge RAM is divided into two parts: top sides along RAM (Figure 14 A) and bottom sides along RAM (Figure 14 B).Bottom sides is 2 each bit node and the edge between each check-node along containing order for example among the RAM.Top sides then contains order along RAM and is higher than 2 each bit node and the edge between each check-node.Therefore, for each check-node, have two adjacent edges to be stored in bottom sides among RAM, remaining edge then is stored in top sides among RAM.

Example above continuing once selects 392 bit nodes and 392 check-nodes to handle as one group.For the processing of 392 check-nodes, from top sides along visit q row in succession the RAM, simultaneously from bottom sides along two row in succession of visit the RAM.In this example, q+2 is exactly the order of each check-node.For the processing of bit node, if the order of the group of 392 bit nodes is 2, then their edge just is located in bottom sides along in two row in succession of RAM.If order d＞2 of each bit node, then their edge just be located in top sides along the d of RAM capable among.The address that this d is capable can be stored in nonvolatile memory, for example among the read-only memory (ROM).Wherein the edge of certain delegation is corresponding to first edge of 392 bit nodes, and the edge of another row is then corresponding to second edge of 392 bit nodes, and the rest may be inferred.And for each row, the column index (index) that belongs to the edge of first bit node in the group of 392 bit nodes also can be stored among the ROM.Corresponding to the index at each edge of second, third node such as bit such as grade, also following the index of initial row in the mode of a kind of " coiling ".For example, j edge in if be expert at belongs to first bit node, and then (j+1) individual edge just belongs to second bit node, and (j+2) individual edge just belongs to the 3rd bit node, ...., and (j-1) individual edge just belongs to the 392nd bit node.

Adopt above-mentioned composition mode (being shown in Figure 14 A and 14B), in the LDPC cataloged procedure, the access speed of memory is improved widely.Also have, in the Code Design comparison diagram of Figure 15, the feature performance benefit of LDPC sign indicating number is more obvious.

Figure 15 is a LDPC coding and the performance comparison diagram of different encoding scheme.Specifically, the figure shows 2 speed and be 5/6 LDPC sign indicating number and be the two bit error rate (BER) performance of 5/6 turbo trellis code with the speed that the outer sign indicating number of Read-Solomon is connected, more than all adopt the 8-PSK modulation.As can be seen, the LDPC sign indicating number is better than with outer yard turbo sign indicating number that is connected of Read-Solomon.The LDPC sign indicating number can not only carry out work under low Es/No, and, for example concerning the transponder of a 27MHz, also provide 3Mbps above additional throughput.

As discussed above, the decoding complexity of LDPC sign indicating number does not advantageously increase along with the length of code.This characteristic allows to use very long code so that obtain preferable performance, till this kind repayment reduces.From the viewpoint of practicality, long code must need bigger buffer storage, also must introduce long delay simultaneously.But along with the swift and violent improvement of memory technology, the buffer storage and the relevant delay thereof of hundreds of kilobit magnitude are inessential, particularly, and for high-speed figure video broadcasting or any broadcasting satellite link.

Though top speed of showing is 5/6 LDPC sign indicating number to be used for the point-like wave beam and to use, the effective isotropic radiant power of its satellite (EIRP) is greater than traditional ConUS (CONUS) wave beam, but as Figure 15 describes in detail, algorithm in order to the LDPC sign indicating number that produces any code rate and any length, from the viewpoint of system, on performance, all be not subjected to too big infringement.The good candidate that is used for the CONUS wave beam be exactly the speed that produces 2.25 bit/symbol be 3/4 code, and the speed that produces 2 bit/symbol is 2/3 code.Be noted that the LDPC sign indicating number can support to use a kind of several data speed of common decoding architecture, compare therewith that for example, convolution code needs to use puncturing technique could obtain medium rates.

Can find out obviously that from Figure 15 according to the link parameter of whole system, the LDPC coding utilizes the hardware of quite simply decoding just can obtain than better power efficiency of other encoding schemes and/or bandwidth efficiency.Utilize the LDPC sign indicating number and the decoding algorithm of appropriate design, decoder 305 just can be with high speed operation, and its speed is considerably beyond other conventional systems that use the standard digital logical circuit.

Figure 16 illustrates that can be realized a computer system 1600 according to an embodiment of the invention thereon.Computer system 1600 contains bus 1601 or other are used to the communicator of the information of transmitting, and is connected on the bus 1601, is used for the processor 1603 of process information.Computer system 1600 also comprises the main storage 1605 that is connected to bus 1601, and for example a random-access memory (ram) or other dynamic storage device are prepared various information and the instruction carried out by processor 1603 in order to storage.In the process of processor 1603 execution commands, main storage 1605 also can be used to store various temporary transient variablees or other average informations.Computer system 1600 also comprises read-only memory (ROM) 1607 or other static memories that are connected to bus 1601, with thinking processor 1603 storage static information and instructions.Storage device 1609, for example disk or CD also are connected to bus 1601, by way of parenthesis in order to storing various information and instruction.

Computer system 1600 can be connected to display 1611 via bus 1601, cathode ray tube (CRT) for example, and LCD, Active Matrix Display or plasma scope are in order to computer user's display message.Input unit 1613 for example comprises the keyboard of alphanumeric and other keys being connected to bus 1601, is used for conveying a message and various command is selected to processor 1603.Another type of user input apparatus is exactly a cursor control 1615, mouse for example, tracking ball, perhaps cursor guiding key etc., also can be used for passing on directional information and various command to select to processor 1603, and in order to control cursor moving on display 1611.

According to one embodiment of present invention, computer system 1600 provides the generation of LDPC sign indicating number in response to the arrangement of a series of instructions in the processor 1603 execution main storages 1605.These instructions can be read among the main storage 1605 from other computer-readable mediums (for example storage device 1609).The arrangement of a series of instructions that execution is comprised in main storage 1605 makes processor 1603 carry out various processes as herein described.One or more processors in the multiprocessor design is arranged also can be used to carry out the instructions that is contained in the main storage 1605.In can supplying each embodiment that substitutes, can replace software instruction with hardware connecting circuit, perhaps combine with software instruction, realize embodiments of the invention.So, various embodiments of the present invention just are not limited to any specific compound mode of hardware circuit and software.

Computer system 1600 also comprises the communication interface 1617 that is connected to bus 1601.Communication interface 1617 provides bidirectional data communication, and it is connected to a local network 1621 by network link 1619.For example, communication interface 1617 may be a Digital Subscriber Line card or modulator-demodulator, an integrated services digital network (ISDN) card, a cable modem, perhaps one telephone modem provides data communication to connect with the telephone line to respective type.As another example, communication interface 1617 also may be the Local Area Network card (card that for example is used for Ethernet or ATM(Asynchronous Transfer Mode) net) that a local area network (LAN) to a compatibility provides data communication to connect.Radio Link also can be realized.In any such embodiment, communication interface 1617 sends and receives electric, electromagnetic or optical signal, and these signals are all carrying the digital data stream of representing different types of information.And communication interface 1617 can comprise external interface device, USB (USB) interface for example, PC memory Card Internation Association (PCMCIA) interface or the like.

Network link 1619 typically provides data communication by one or more networks to other data sets.For example, network link 1619 can provide towards the connection of master computer 1623 by local network 1621, master computer 1623 and network 1625 are (for example, wide area network (WAN) or global block data communication net are called as " internet " now at large) or the data equipment of service provider operation link to each other.Local network 1621 and network 1625 the two all use electric, electromagnetic or optical signal to transmit various information and instruction.With the signal that passes through diverse network, the signal on network link 1619 of computer system 1600 exchange numerical datas, and the signal of process communication interface 1617, all be the exemplary form of carrying the carrier wave of various information and instruction.

Computer system 1600 can be passed through network, and network link 1619 and communication interface 1617 send message and receive data, comprising program code.In the example of internet, the server (not shown) can send the required code that belongs to an application program by network 1625, local network 1621 and communication interface 1617, so that realize one embodiment of the present of invention.Processor 1603 can be carried out the code that is sent that is receiving, and/or with this code storage among storage device 1609 or other Nonvolatile memory devices, be provided with the back and carry out.By this way, computer system 1600 may obtain application code with the form of carrier wave.

Here employed term " computer-readable medium " refers to any medium of the instructions that participation is provided for carrying out to processor 1603.Such medium has a lot of forms, includes but not limited to non-volatile media, Volatile media and transmission medium.Non-volatile media comprises that for example, CD or disk are such as storage device 1609.Volatile media comprises dynamic memory, such as main storage 1605.Transmission medium comprises various coaxial cables, copper cash and optical fiber, comprises the lead that constitutes bus 1601.Transmission medium also can be taked sound wave, and light wave or form of electromagnetic wave are such as the various ripples that produced in radio frequency (RF) and infrared (IR) data communication.The general type of computer-readable medium comprises, for example, floppy disk, flexible disk, hard disk, tape, any other magnetic medium, read-only optical disc (CD-ROM), CD-RW (CDRW), Digital video disc (DVD), any other optical medium, punched card, paper tape, the optical markings list, and have the figure in hole or other physical mediums of the mark that other available optical meanss are discerned, RAM, PROM and EPROM, FLASH-EPROM, any other memory chip or cartridge, carrier wave, or computer-readable any other medium.

When providing executable instruction, may relate to multi-form computer-readable medium to processor.For example, the instruction that is used to implement at least a portion of the present invention may at first be carried in the disk of remote computer.In this case, remote computer is loaded into instruction on the main storage, and uses modulator-demodulator to send instruction by telephone line.The modulator-demodulator of local computer system receives the data that transmit on telephone line, and use infrared transmitter that data transaction is become infrared signal, infrared signal is sent to portable computing, for example PDA(Personal Digital Assistant) and laptop computer.Infrared detector on portable computing receives the information and the instruction of being carried by infrared signal, and data are sent on the bus.Bus is sent to main storage with data, and processor takes out instruction again and carried out from main storage.The instruction that main storage receives can be stored among the storage device before or after processor is carried out.

Correspondingly, each different embodiment of the present invention provides a kind of method, in order to produce structurized low-density checksum (LDPC) sign indicating number, so that encoder is simplified.By parity matrix being defined as the Lower Half triangle, provide the structure of LDPC sign indicating number.Equally, this method can advantageously be used the unequal error protection ability of LDPC sign indicating number to each bit of being sent out, so that provide extra error protection to each more fragile bit of high order modulation constellation [such as 8-phase shift keying (8-PSK)].In addition, can use the every constant and the bitwise operation of storage in advance, produce parity matrix from algorithm.By representing that each edge information in succession from each check-node of parity matrix to each bit node stores on the position in succession of memory, just can realize effective decoding of LDPC.Such scheme has advantageously reduced complexity under the prerequisite of any sacrifice in performance not.

When the present invention will be described in conjunction with a plurality of embodiment and embodiment, therefore the present invention is not restricted, on the contrary, it has covered various tangible modifications and the various design arrangement that is equal to, and they all are in the scope of appending claims.

Claims (32)

1. method that communicates, supports communication service via satellite reliably, this method comprises:

Input message is encoded, so that the low-density checksum of export structureization (LDPC) coded message;

According to a kind of high order modulation scheme, the message of having encoded is modulated; And

(111) send modulated signal via satellite.

2. according to the method for claim 1, wherein, high order modulation scheme in modulation step has a signal constellation (in digital modulation), on behalf of each modulation symbol, this signal constellation (in digital modulation) signaling point more than 4 is arranged, wherein, if this signal constellation (in digital modulation) is one 2 dimensional signal space, then some signaling point can be non-orthogonal in other signaling point.

3. according to the process of claim 1 wherein, the high order modulation scheme in modulation step comprise 8-phase shift keying (8-PSK) and 16-quadrature amplitude modulation (16-QAM) at least one of them.

4. according to the method for claim 1, also comprise:

The outer sign indicating number of Read-Solomon (RS) is put on input message, so that the message that output has been encoded.

5. according to the method for claim 1, also comprise:

According to high order modulation scheme the signal that has sent is carried out demodulation; And the decoding scheme according to a kind of regulation is decoded to demodulated signal.

6. according to the process of claim 1 wherein, one of them is associated the signal that is sent out with a plurality of data rates, and according to carrying out decoding step with the decoding scheme of the irrelevant regulation of a plurality of data rates.

7. according to the process of claim 1 wherein, communication service comprises live telecast, and this method also comprises:

Optionally decoded signal is outputed to television indicator (119).

8. according to the process of claim 1 wherein, communication service comprises data service, and this method also comprises:

Decoded signal is outputed to computer (1600).

9. one kind is loaded with and is used for via satellite the computer-readable medium that (111) communicated, supported the instruction of communication service reliably, and described instruction in commission is arranged to make one or more processors to go enforcement of rights to require 1 method.

10. one kind is used for going up via satellite reliably the ICBM SHF satellite terminal that communicates, supports communication service, and this terminal comprises:

An encoder (203), it is configured in response to input message, the low-density checksum of export structureization (LDPC) coded message; And

A modulator (205), it is configured to according to a kind of high order modulation scheme the message of having encoded be modulated, and wherein, modulated signal (111) via satellite sends.

11. according to the terminal of claim 10, wherein, high order modulation scheme has a signal constellation (in digital modulation), on behalf of each modulation symbol, this signal constellation (in digital modulation) signaling point more than 4 is arranged, wherein, if this signal constellation (in digital modulation) is one 2 dimensional signal space, then some signaling point can be non-orthogonal in other signaling point.

12. according to the terminal of claim 10, wherein, high order modulation scheme comprise 8-phase shift keying (8-PSK) and 16-quadrature amplitude modulation (16-QAM) at least one of them.

13. according to the terminal of claim 10, wherein, encoder (203) is exported the message of having encoded by the outer sign indicating number of Read-Solomon (RS) is put on input message.

14. the terminal according to claim 10 also comprises:

A demodulator (301), it is configured to according to high order modulation scheme the signal that has sent be carried out demodulation; And

A decoder (305), it is configured to according to a kind of decoding scheme of regulation demodulated signal be decoded.

15. according to the terminal of claim 10, wherein, one of them is associated the signal that is sent out with a plurality of data rates, and according to the decoding scheme of the irrelevant regulation of a plurality of data rates, decode by decoder (305).

16. according to the terminal of claim 10, wherein, communication service comprises live telecast, and decoded signal is output to television indicator (119).

17. according to the terminal of claim 10, wherein, communication service comprises data service, and decoded signal is output to computer (1600).

18. a satellite communication system of supporting communication service, this system comprises:

One first terminal, it is configured to like this encodes to input message, so that the low-density checksum of export structureization (LDPC) coded message; And according to a kind of high order modulation scheme, the message of having encoded is modulated, wherein, modulated signal (111) via satellite sends.

One second terminal, it is configured to receive the signal that (111) via satellite send.

19. according to the system of claim 18, wherein, high order modulation scheme has a signal constellation (in digital modulation), on behalf of each modulation symbol, this signal constellation (in digital modulation) signaling point more than 4 is arranged, wherein, if this signal constellation (in digital modulation) is one 2 dimensional signal space, then some signaling point can be non-orthogonal in other signaling point.

20. according to the system of claim 18, wherein, high order modulation scheme comprise 8-phase shift keying (8-PSK) and 16-quadrature amplitude modulation (16-QAM) at least one of them.

21. according to the system of claim 18, wherein, first terminal also is configured to the outer sign indicating number of Read-Solomon (RS) is put on the message of having encoded.

22. according to the system of claim 18, wherein, second terminal is configured to according to high order modulation scheme the signal that has sent be carried out demodulation; And demodulated signal is decoded according to a kind of decoding scheme of regulation.

23. according to the system of claim 18, wherein, one of them is associated the signal that is sent out with a plurality of data rates, and according to the decoding scheme of the irrelevant regulation of a plurality of data rates, the signal that has sent is decoded.

24. according to the system of claim 18, wherein, communication service comprises live telecast, and decoded signal is outputed to television indicator (119).

25. according to the system of claim 18, wherein, communication service comprises data service, and decoded signal is outputed to computer (1600).

26. a system that is used for communicating reliably via satellite, supporting communication service, this system comprises:

Be used for input message is encoded, so that the low-density checksum of export structureization (LDPC) coded message, and according to a kind of high order modulation scheme, the device that the message of having encoded is modulated, above-mentioned high order modulation scheme has a signal constellation (in digital modulation), and on behalf of each modulation symbol, this signal constellation (in digital modulation) plural signaling point is arranged; And

Transmitter (200), it is configured to via satellite (111) and propagates modulated signal.

27. according to the system of claim 26, wherein, high order modulation scheme comprise 8-phase shift keying (8-PSK) and 16-quadrature amplitude modulation (16-QAM) at least one of them.

28., wherein, be used to encode and the device modulated puts on input message with the outer sign indicating number of Read-Solomon (RS), so that the message that output has been encoded according to the system of claim 26.

29. the system according to claim 26 also comprises:

Receiver circuit (300), it is configured to according to high order modulation scheme the signal that has sent be carried out demodulation, and according to a kind of decoding scheme of regulation demodulated signal is decoded.

30. according to the system of claim 26, wherein, one of them is associated the signal that is sent out with a plurality of data rates, and receiver circuit (300) is according to the decoding scheme of the irrelevant regulation of a plurality of data rates demodulated signal being decoded.

31. according to the system of claim 26, wherein, communication service comprises live telecast, this system also comprises:

Television indicator (119), it is configured to receive decoded signal.

32. according to the system of claim 26, wherein, communication service comprises data service, this system also comprises:

Computer (1600), it is configured to receive decoded signal.

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