CN101567699B - Decoding device - Google Patents

Abstract

There are provided a decoding device, a decoding method, and a program for realizing decoding of the LDPC code capable of suppressing the circuit size, suppressing the operation frequency to a sufficiently realizable range, and easily controlling memory access. The inspection matrix of the LDPC code is composed of a combination of a unit matrix p x p, the unit matrix in which one or more 1 have become 0, their cyclic shifts, a sum of them, and a 0 matrix of p x p. A check node calculation section (313) simultaneously performs P check node calculations while a variable node calculation section (319) simultaneously performs P variable node calculations.

Description

Decoding device

The application is that denomination of invention is " decoding device, coding/decoding method and program " (application number: 200480000601.7; The applying date: the dividing an application of application on April 19th, 2004).

Technical field

The present invention relates to a kind of decoding device, coding/decoding method and program.More specifically, the present invention relates to a kind of decoding device and coding/decoding method and program thereof of the code decoding for using low density parity check code (LDPC code) to encode.

Background technology

In recent years, for example, such as the communications field of mobile communication and deep space communication and remarkable such as the research progress in the broadcast world of land ripple or satellite digital broadcasting.What situation occurred together therewith is to have carried out energetically being used for making the research of error correction coding and the efficient coding theory of decoding.

As the theoretical limit of code performance, the Shannon limit that is represented by so-called Shannon (C.E.Shannon) channel coding theorem is well-known.Demonstrate purpose near the code of the performance of this Shannon limit for exploitation, carried out the research to coding theory.For example, in recent years, as the coding method that demonstrates near the performance of the Shannon limit, developed the technology that is commonly called " strengthening coding ", such as Parallel Concatenated Convolutional Code (PCCC) and Serial Concatenated Convolutional Code (SCCC).In addition, strengthen coding although developed this, known long coding method as people, low density parity check code (hereinafter referred to as " LDPC code ") has attracted attentiveness.

In " Low Density Parity Check Codes (low density parity check code) " (Cambridge, Massachusetts:M.I.T.Press, 1963) of R.G.Gallager, the LDPC code has been proposed first.Subsequently, " Good error correcting codes based on very sparsematrices (based on the good error correcting code of utmost point sparse matrix) " at D.J.C.Mackay (submits to IEEE Trans.Inf.Theory, IT-45, pp.399-431,1999) and M.G.Luby, M.Mitzenmacher, " Analysis of low density codes and improved designs usingirregular graphs (the improvement design of the analysis of low-density code and use irregular figure) " (Proceedingsof ACM Symposium on Theory of Computing of M.A.Shokrollachi and D.A.Spielman, pp.249-258,1998) in, LDPC has attracted attentiveness again.

According to this research recently, people acquaint oneself of, and for the LDPC code, coding is similar to strengthening, and when code length increases, can obtain the performance near the Shannon limit.In addition, because the LDPC code has minimum length and the proportional character of code length, therefore, they have such advantage: piece error probability characteristic is good, and so-called Error-floor (error floor) phenomenon of observing in the decoding characteristics that strengthens coding occurs hardly.

Now, will be discussed in more detail below such LDPC code.The LDPC code is linear code, and always is not two-dimentional, but, supposes that LDPC is the description that provides of two dimension here.

The maximum feature of LDPC code is: the parity matrix of definition LDPC code is sparse.Here, form sparse matrix in 1 the very little such mode of number in the matrix element.If sparse check matrix is expressed as H, then its example comprises such check matrix, wherein, as shown in Figure 1, the Hamming of every row (Hamming) weight (1 number; Weight) be " 3 ", and the Hamming weight of every row is " 6 ".

As mentioned above, the LDPC code by the fixing check matrix H definition of the Hamming weight of every row and every row is called as " regular LDPC code ".On the other hand, the LDPC code by the unfixed check matrix H definition of the Hamming weight of every row and every row is called as " abnormal LDPC code ".

Produce generation (generation) matrix G by the basis in check matrix H, and this generator matrix G be multiply by two-dimensional signal message and generated codeword, realize utilizing the coding of this LDPC code.More particularly, the encoding device that is used for utilizing the LDPC code to encode calculates generator matrix G, wherein, and for the transposed matrix H of check matrix H ^T, equation GH ^T=0 sets up.Here, when generator matrix G was k * n matrix, encoding device multiply by k position informational message (vectorial u) with generator matrix G, and generate n bit word c (=uG).Be mapped to the code bit that "+1 " will be worth for " 1 " and be mapped in the situation of " 1 " will being worth code bit for " 0 ", transmit the code word that encoding device thus generates, and, it received by the scheduled communication channel at receiver side.

On the other hand, can be by the message pass-algorithm, utilize the belief propagation (beliefpropagation) on the so-called Tanner figure to carry out the decoding of LDPC code, wherein, described Tanner figure is made of variable node (being also referred to as information node) and check-node; This message pass-algorithm is proposed by Gallager, and as " probabilistic decoding " and known.Hereinafter, variable node and check-node also are called node for short in suitable place.

Yet, in probabilistic decoding, because the message that exchanges is real number value, therefore, in order to find analytic solutions, be necessary to find out the probability distribution of the message of taking successive value between node.This is so that comprise the analysis of large difficulty and necessitate.Therefore, Gallager has proposed algorithm A or algorithm B as the algorithm that is used for the decoding of LDPC code.

Usually, carry out the decoding of LDPC code according to the process shown in Fig. 2.Here, will receive value representation is U ₀(u _0i), will be shown u from the message table of check-node output _j, and will be shown v from the message table of variable node output _iHere, described message is real number value, so that recently represent " 0 " similitude (1ikeness) of this value with so-called log-likelihood.

In the decoding of LDPC code, initial, as shown in Figure 2, and in step S11, reception value U ₀(u _0i) received, message u _jBe initialized to 0, and, integer is initialized to 0 as the variable k of the counter of iterative process.Then, process proceeds to step S12.At step S12, based on the reception value U of institute ₀(u _0i), determine message v by carrying out the calculating shown in the formula (1) _iIn addition, based on this message v _i, determine message u by carrying out the calculating shown in the formula (2) _j

$v_i=u_{0i}+\underset{j=1}{\overset{d_v-1}{\mathrm{\Σ}}}{u}_j---\left(1\right)$

$\tanh \left(\frac{u_j}{2}\right)=\underset{i=1}{\overset{d_c-1}{\mathrm{\Π}}}\tanh \left(\frac{v_i}{2}\right)---\left(2\right)$

Here, the d in formula (1) and (2) _vAnd d _cBe respectively the parameter of the number of 1 on the vertical direction (row direction) of indication check matrix H and the horizontal direction (directions of row), and, can select them according to desirable.For example, in the situation of (3,6) code, d _v=3 and d _c=6.

In each calculating of formula (1) and (2) and since from the message of rib (edge) input of output message be not used as and or the long-pending parameter of calculating, therefore, and or the long-pending scope of calculating be to d from 1 _v-1 or from 1 to d _c-1.In fact, by the function R (v shown in the prior establishment formula 3 ₁, v ₂) table, and as shown in Figure 4 continuously (recursively) use this table, carry out the calculating shown in the formula (2), wherein, described function R (v ₁, v ₂) by inputting v about two ₁And v ₂An output define.

x＝2tanh ^-1{tanh(v ₁/2)tanh(v ₂/2)}＝R(v ₁，v ₂) (3)

$u_j=R(v_1,R(v_2,R(v_3,...R(v_{d_c-2},v_{d_c-1}))))---\left(4\right)$

In addition, at step S12, variable k is increased by 1, then, process proceeds to step S13.At step S13, determine that variable k is whether more than or equal to the predetermined number N of iterative decoding.When step S13 determines that variable k is not greater than or equal to N, process is returned step S12, and again carries out same processing.

When step S13 determines variable k more than or equal to N, process proceeds to step S14, at this place, determine and output as the result who carries out the calculating shown in the formula (5) and message v last output, that serve as decoded result.This has finished the decode procedure of LDPC code.

$v_j=u_{0i}+\underset{j=1}{\overset{d_v}{\mathrm{\Σ}}}{u}_j---\left(5\right)$

Here, different from the calculating of formula (1), use the calculating of carrying out formula (5) from the input message of all ribs that are connected to variable node.

In such LDPC code decode procedure, for example, in the situation of (3,6) code, as shown in Figure 3, between node, exchange messages.In the node (variable node) by "=" expression in Fig. 3, carry out the calculating shown in the formula (1).In the node (check-node) by "+" expression, carry out the calculating shown in the formula (2).Specifically, in algorithm A, message is formed two dimension; In the node by "+" expression, carry out d _cThe XOR of-1 input message calculates; And in the node by "=" expression, for the reception value R of institute, as all d _vWhen-1 input message was different place value, symbol was by negate and be output.

In addition, in recent years, carried out the research to the implementation method of LDPC code decoding.Before describing implementation method, the decoding of LDPC code is described with the form of signal.

Fig. 4 shows the parity matrix example of (3,6) LDPC code (encoding rate is 1/2, and code length is 12).Can be by write out the parity matrix of LDPC code with Tanner figure, as shown in Figure 5.In Fig. 5, the node that is represented by "+" is check-node, and the node that is represented by "=" is variable node.Check-node and variable node correspond respectively to the row and column of parity matrix.Connecting line between check-node and the variable node is rib, and corresponding to " 1 " of check matrix.That is to say, when elements capable as the j of check matrix and the i row are 1, in Fig. 5, from i variable node (node of "=") the top and from the top j check-node (node of "+") be connected to each other by rib.Rib represents that the sign bit corresponding to variable node has the constraints corresponding to check-node.Fig. 5 shows the Tanner figure of the check matrix of Fig. 4.

In the sum-product algorithm as the method that the LDPC code is decoded, repeat the calculating of variable node and the calculating of check-node.

In variable node, as shown in Figure 6, carry out the calculating of formula (1).That is to say, in Fig. 6, by using the message u from all the other ribs that are connected to variable node ₁And u ₂, and received information u _0i, calculate the message v corresponding to the rib that will calculate ₁Message corresponding to other rib is also calculated similarly.

Before describing check node calculation, by use formula a * b=exp{ln (| a|)+ln (| b|) } * sign (a) * sign (b) comes rewriting formula (2), shown in (6), wherein, sign (x) o'clock is 1 in x 〉=0, and o'clock is-1 in x＜0.

$u_j={2\tanh }^{-1}\left(\underset{i=1}{\overset{d_c-1}{\mathrm{\Π}}}\tanh \left(\frac{v_i}{2}\right)\right)$

$={2\tanh }^{-1}\left[\exp \right\{\underset{i=1}{\overset{d_c-1}{\mathrm{\Σ}}}\ln \left(\right|\tanh \left(\frac{v_i}{2}\right)\left|\right)\}\×\underset{i=1}{\overset{d_c-1}{\mathrm{\Π}}}\mathrm{sign}\left(\tanh \left(\frac{v_i}{2}\right)\right)]---\left(6\right)$

$={2\tanh }^{-1}\left[\exp \right\{-(\underset{i=1}{\overset{d_c-1}{\mathrm{\Σ}}}-\ln \left(\tanh \left(\frac{\left|v_i\right|}{2}\right)\right))\left\}\right]\×\underset{i=1}{\overset{d_c-1}{\mathrm{\Π}}}\mathrm{sign}\left(v_i\right)$

In addition, in the situation of x 〉=0, when making definition

The time, because

Therefore, formula (6) can be written as formula (7).

$u_j={\mathrm{\Φ}}^{-1}\left(\underset{i=1}{\overset{d_c-1}{\mathrm{\Σ}}}\mathrm{\Φ}\left(\right|v_i\left|\right)\right)\×\underset{i=1}{\overset{d_c-1}{\mathrm{\Π}}}\mathrm{sign}\left(v_i\right)---\left(7\right)$

In check-node, as shown in Figure 7, carry out the calculating of formula (7).That is to say, in Fig. 7, by using the message v from all the other ribs that are connected to check-node ₁, v ₂, v ₃, v ₄And v ₅, calculate the message u corresponding to the rib that will calculate for it _jMessage corresponding to other rib is also calculated similarly.

Function

Also can be represented as And, when x＞0,

Work as function

With

When being used as the hardware realization, there is such situation, wherein, use LUT (look-up table) to realize them, and both is identical LUT for they.

When sum-product algorithm is used as the hardware realization, is necessary to utilize suitable circuit scale and with suitable frequency of operation, repeats the variable node calculating that is represented by formula (1) and the check node calculation that is represented by formula (7).

As the example that realizes decoding device, given first is to the description of in such a case implementation method, wherein, and by the calculating of carrying out successively in order simply each node decode (fully continuous decoding).

Here, for example, suppose code (encoding rate is 2/3, and code length the is 90) decoding that will be represented by 30 (OK) * 90 (row) check matrixes of Fig. 8.1 number of the check matrix of Fig. 8 is 269; Therefore, in Tanner figure, the number of rib becomes 269.Here, in the check matrix of Fig. 8, utilize ". " to represent 0.

Fig. 9 shows for the topology example with LDPC code decoding decoding device once.

In the decoding device of Fig. 9, for this equipment each clock (clock) with its operation, calculate the message corresponding to a rib.

More particularly, the decoding device of Fig. 9 comprise two memories 100 that are used for rib and 102, check node calculation devices 101, variable node calculator 103, one be used for memory 104 and a control assembly 105 of receiving.

In the decoding device of Fig. 9, read successively message data from the memory 100 or 102 that is used for rib, and, by using this message data, calculate the message data corresponding to desirable rib.Then, will be stored in successively by the message data of this calculative determination the memory 100 or 102 that is used for rib of rear class.In the time will carrying out iterative decoding, a plurality of for the decoding device of LDPC code decoding Fig. 9 once or by reusing the decoding device of Fig. 9 by continuous cascade, realize iterative decoding.Here, for example, suppose to connect the decoding device of a plurality of Fig. 9.

The message D100 that provides from variable node calculator 103 (not shown) of prime decoding device is provided the memory 100 that is used for rib in a certain order, and this sequentially is that the check node calculation device 101 of rear class reads their order.Then, in the check node calculation stage, the memory 100 that is used for rib offers check node calculation device 101 as message output D101 with their stored orders with message D100.

Based on the control signal D106 that provides from control assembly 105, check node calculation device 101 is by the message D101 that provides from the memory 100 that is used for rib being provided, calculating according to formula (7), and will offer by the message D102 of this calculative determination the memory 102 that is used for rib of rear class.

The message D102 that provides from the check node calculation device 101 of prime is provided the memory 102 that is used for rib in a certain order, and this sequentially is that the variable node calculator 103 of rear class reads their order.Then, in the variable node calculation stages, the memory 102 that is used for rib offers variable node calculator 103 with message D102 as message D103 and with the order of storing them.

In addition, control signal D107 is offered variable node calculator 103 from control assembly 105, and, received data D104 is offered variable node calculator 103 from the memory 104 that is used for receiving.Based on control signal D107, variable node calculator 103 is by message D103 and the received data D104 from providing for the memory 100 that receives that provides from the memory 100 that is used for rib is provided, calculate according to formula (1), and the message D105 that will obtain as result of calculation offers memory 100 (not shown) that are used for rib of the decoding device of rear class.

In the memory 104 that is used for receiving, the data that are converted into the LDPC code (LDPC code) that storage receives.Control assembly 105 will offer respectively check node calculation device 101 and variable node calculator 103 for the control signal D106 of control variable node calculating with for the control signal D107 that controls check node calculation.When the message of all ribs all is stored in memory 100 for rib, control assembly 105 offers check node calculation device 101 with control signal D106, and when the message of all ribs all was stored in memory 102 for rib, control assembly 105 offered variable node calculator 103 with control signal D107.

Figure 10 shows the topology example that is used for carrying out successively the check node calculation device 101 of check node calculation of Fig. 9.

In Figure 10, be quantified as together 6 altogether by supposing each message and sign bit, check node calculation device 101 is shown.In addition, in Figure 10, carry out the check node calculation by the LDPC code of the check matrix of Fig. 8 representative.In addition, clock ck is offered the check node calculation device 101 of Figure 10, this clock ck is provided for necessary piece.Each piece and clock ck synchronously process.

For example, based on 1 the control signal D106 that provides from control assembly 105, the check node calculation device 101 of Figure 10 is by using the message D101 that reads successively from the memory 100 that is used for rib to carry out calculating according to formula (7).

More particularly, in check node calculation device 101, read successively from 6 message D101 (message v corresponding to the variable node of each row of check matrix _i), as the absolute value D122 of its lower-order (lower-order) position (| v _i|) be provided for LUT 121, and be supplied to EXOR circuit 129 and FIFO (first-in first-out) memory 133 as the sign bit D121 of its highest order.In addition, control signal D106 is offered check node calculation device 101 from control assembly 105, and, this control signal D106 is offered selector 124 and selector 131.

LUT 121 read to absolute value D122 (| v _i|) carry out in the formula (7)

5 result of calculations of calculating gained

And provide it to adder 122 and FIFO memory 127.

Adder 122 is passed through result of calculation

With 9 place value D124 (integrate) result of calculation that adds up added together that is stored in the register 123

And thus obtained 9 aggregate-values are stored in the register 123 again.When added up from the message D101 of all ribs in the check matrix delegation absolute value D122 (| v _i|) result of calculation the time, register 123 is reset.

As the message D101 that reads successively in the check matrix delegation, and in the time of will being stored in the register 123 for the aggregate-value of the result of calculation D123 of delegation, the control signal D106 that provides from control assembly 105 changes into 1 from 0.For example, when row weight when being " 9 ", control signal D106 is " 0 " at the 1st to the 8th clock, and is " 1 " at the 9th clock.

When control signal D106 is " 1 ", the value of selector 124 Selective storages in register 123, i.e. message D101 (the message v of all ribs in the self checking matrix delegation always _i) determine

9 place value D124 of gained (

From i=1 to i=d _c), and should value output to register 125 as value D125, store thus it.Register 125 offers selector 124 and adder 126 with the value D125 that stores as 9 place value D126.When control signal D106 was " 0 ", the value D126 that provides from register 125 was provided for selector 124, and this value is outputed to selector 124, came thus again to store it.That is to say that register 125 will before add up

Offer selector 124 and adder 126, until added up message D101 (the message v of all ribs in the self checking matrix delegation always _i) determine

Till.

On the other hand, FIFO memory 127 is with the result of calculation of LUT 121 outputs

Postpone, until from the new value of register 125 outputs D126 (

From i=1 to i=d _c) till, and result of calculation D123 offered subtracter 126 as 5 place value D127.Subtracter 126 deducts the value D127 that provides from FIFO memory 127 from the value D126 that register 125 provides, and subtraction result is offered LUT 128 as 5 subtraction value D128.That is to say message D101 (the message v of subtracter 126 all ribs from the origin self checking matrix delegation _i) determined

Aggregate-value in, deduct by message D101 (the message v from the rib that will determine _i) determined

And with subtraction value (

From i=1 to i=d _c-1) offers LUT 128 as subtraction value D128.

LUT 128 output to subtraction value D128 (

From i=1 to i=d _c-1) carries out in the formula (7)

5 result of calculations of calculating gained

When carrying out above-mentioned processing, EXOR circuit 129 is stored in 1 place value D131 in the register 130 and the XOR of sign bit D121 by calculating, carries out the multiplication of sign bit, and 1 multiplication result D130 is stored in the register 130 again.The sign bit D121 of the message D101 of all ribs is all taken advantage of fashionablely on from check matrix delegation, and register 130 is reset.

As the multiply each other multiplication result D130 (∏ sign (v of gained of the sign bit D121 that has stored the message D101 of all ribs in the in the future self checking matrix delegation _i), from i=1 to i=d _c) time, the control signal D106 that provides from control assembly 105 changes into " 1 " from " 0 ".

When control signal D106 is " 1 ", the value of selector 131 Selective storages in register 130, that is, and the multiply each other value D131 (∏ sign (v of gained of the sign bit D121 of the message D101 of all ribs in the self checking matrix delegation in the future _i), from i=1 to i=d _c), and should value output to register 132 as 1 place value D133, store thus it.Register 132 offers selector 131 and EXOR circuit 134 with the value D132 that stores as 1 place value D132.When control signal D106 was " 0 ", the value D133 that provides from register 132 was provided for selector 131, and this value is outputed to register 132, came thus again to store it.That is to say that register 132 offers selector 131 and EXOR circuit 134 with previously stored value, until from message D101 (the message v of all ribs in the check matrix delegation _i) sign bit D121 taken advantage of till.

On the other hand, FIFO memory 133 postpones sign bit D121, until newly be worth D133 (∏ sign (v _i), from i=1 to i=d _c) offered EXOR circuit 134 from register 132 till, and it offers EXOR circuit 134 with this result as 1 place value D134.EXOR circuit 134 will be worth D133 divided by value D134, and 1 result of division will be exported as the value D135 that is divided by by the XOR of the value D134 that the value D133 that provides from register 132 is provided and provides from FIFO memory 133.That is to say, the sign bit D121 of the message D101 of all ribs in the EXOR circuit 134 in the future self checking matrix delegation (sign (| v _i|)) multiply each other value divided by from the sign bit D121 of the message D101 of the rib that will determine (sign (| v _i|)), and the value of will being divided by (∏ sign (v _i), from i=1 to i=d _c-1) as the value D135 output of being divided by.

In check node calculation device 101, will be altogether 6 as message D102 (message u _j) output, wherein, be 5 of lower-order from 5 result of calculation D129 of LUT 128 output, and be high-order positions from 1 value D135 that is divided by of EXOR circuit 134 outputs.

As mentioned above, in check node calculation device 101, carry out the calculating of formula (7), and definite message u _j

Because the capable weight maximum of the check matrix of Fig. 8 is 9, that is to say that owing to the maximum number that offers the message of check-node is 9, therefore, check node calculation device 101 has for 9 message

The FIFO memory 127 and the FIFO memory 133 that postpone.When wanting Determining Weights less than the message of 9 row, the retardation in FIFO memory 127 and the FIFO memory 133 is reduced to the value of capable weight.

Figure 11 shows the topology example for the variable node calculator 103 that carries out successively variable node calculating of Fig. 9.

In Figure 11, by supposing that each message and sign bit are quantified as together altogether 6 variable node calculator 103 is shown.In Figure 11, carry out being calculated by the variable node of the LDPC code of the check matrix of Fig. 8 representative.In addition, clock ck is offered the variable node calculator 103 of Figure 11, and this clock ck is provided for the piece of necessity.Each piece and clock ck synchronously process.

For example, based on 1 the control signal D107 that provides from control assembly 105, the variable node calculator 103 of Figure 11 carries out the calculating according to formula (1) by using message D103 and the receive data D104 from reading for the memory 104 that receives that reads successively from the memory 102 that is used for rib.

More particularly, in variable node calculator 103, read successively from 6 message D103 (message u corresponding to the check-node of the every delegation of check matrix _j), and message D103 offered adder 151 and FIFO memory 155.In addition, in variable node calculator 103, read successively 6 receive data D104 from the memory 104 that is used for receiving, and provide it to adder 156.In addition, control signal D107 is offered variable node calculator 103 from control assembly 105, and this control signal D107 is offered selector 153.

Adder 151 is passed through message D103 (message u _j) and be stored in 9 place value D151 in the register 152 accumulative total message D103 of coming added together, and 9 aggregate-values are stored in the register 152 again.During the message D103 of all ribs, register 152 is reset on having added up from check matrix delegation.

When the message D103 of all ribs and the value of message D103 gained that will add up row were stored in the register 152 on reading successively from check matrix delegation, the control signal D107 that provides from control assembly 105 changed into " 1 " from " 0 ".For example, when the row weight was " 5 ", control signal D107 was " 0 " at the 1st clock to the 4 clocks, and was " 0 " at the 5th clock.

When control signal D107 is " 1 ", the value of selector 153 Selective storages in register 152, that is, accumulative total is from message D103 (the message u of all ribs in the check matrix delegation _j) 9 place value D151 (∑ u of gained _j, from j=1 to j=d _v), and this value outputed to register 154, store thus it.Register 154 offers selector 153 and adder-subtracter 156 with the value D151 that stores as 9 place value D152.When control signal D107 was " 0 ", the value D152 that provides from register 154 was provided for selector 153, and this value is outputed to register 154, came thus again to store it.That is to say that the value that register 154 will before add up offers selector 153 and adder-subtracter 156, until added up message D103 (the message u from all ribs in the check matrix delegation _j) till.

On the other hand, the message D103 of FIFO memory 155 in the future self checking nodes postpones, until from the new value of register 154 outputs D152 (∑ u _j, from j=1 to j=d _v) till, and message D103 offered adder-subtracter 156 as 6 place value D153.Adder-subtracter 156 deducts the value D153 that provides from FIFO memory 155 from the value D152 that register 154 provides.That is to say that adder-subtracter 156 is message D103 (the message u of all ribs in the self checking matrix delegation always _j) aggregate-value in deduct message u from the rib that will determine _j, and definite subtraction value (∑ u _j, from j=1 to j=d _v-1).In addition, adder-subtracter 156 will be added to subtraction value (∑ u from the receive data D104 that provide for the memory 104 that receives _j, from j=1 to d _v-1) on, and with thus obtained 6 place values as message D105 (message v _i) output.

As mentioned above, in variable node calculator 103, carry out the calculating of formula (1), and definite message v _i

Because the row weight maximum of the check matrix of Fig. 8 is 5, that is to say, be 5 owing to offer the maximum number of the message of variable node, therefore, variable node calculator 103 has for postponing 5 message (u _j) FIFO memory 155.When wanting Determining Weights less than the message of 5 row, the retardation in the FIFO memory 155 is reduced to the value of row weight.

In the decoding device of Fig. 9, come to provide control signal from control assembly 105 according to the weight of check matrix.Decoding device according to Fig. 9, as long as be used for rib memory 100 and 102 and the capacity of the FIFO memory 127 of check node calculation device 101 and variable node calculator 103, l33 and 155 enough, just can the LDPC code of various check matrixes be decoded by only changing control signal.

Although not shown in the decoding device of Fig. 9, at the afterbody of decoding, carry out the calculating of formula (5) rather than the variable node of formula (1) and calculate, and result of calculation is exported as final decoded result.

When by the decoding device of reusing Fig. 9 the LDPC code being decoded, the check node calculation that hockets and variable node calculate.That is to say, in the decoding device of Fig. 9, variable node calculator 103 carries out variable node by the check node calculation result with check node calculation device 101 and calculates, and check node calculation device 101 carries out check node calculation by the variable node result of calculation with variable node calculator 103.

Therefore, once decode for the check matrix with 269 ribs with Fig. 8, need 269 * 2=538 clock.For example, in order to carry out iterative decoding 50 times, when receiving when 90 codes (receive data) are made as a frame of a frame, 538 * 50=26900 clock operation is essential, a wherein said frame is code length, thereby, about 300 (≈ 26900/90) that are approximately receive frequency doubly high high speed operation become essential.If supposing receive frequency is tens of MHz, then need the operation of GHz or more speed.

In addition, for example, the decoding device of 50 Fig. 9 of cascade with the situation with the decoding of LDPC code in, can carry out simultaneously a plurality of variable nodes and calculate and check node calculation.For example, when the variable node that carries out the first frame calculates, carry out the check node calculation of the second frame, and carry out the variable node calculating of the 3rd frame.In this case, when receiving 90 codes, owing to need to calculate 269 ribs, so decoding device need to operate with the doubly high frequency in 3 (≈ 269/90) that is approximately receive frequency, thereby very possible the realization.Yet in this case, briefly, it is large that circuit scale becomes 50 times of decoding device of Fig. 9.

Next, provide in the description of calculating to decode decoding device implementation method in the situation of (complete parallel decoding) by carrying out simultaneously all nodes.

For example, in " Parallel Decoing Architectures for Low Density Parity Check Codes (the parallel decoding framework of low density parity check code) " (Symposium on Circuits and Systems, 2001) of C.Howland and A.Blanksby, this implementation method has been described.

Figure 12 A to 12C shows the structure for the decoding device example of code (encoding rate is 2/3, and code length the is 90) decoding that will be represented by the check matrix of Fig. 8.Figure 12 A shows the general structure of decoding device.Figure 12 B show Figure 12 A decoding device by dotted line B around the detailed construction of figure middle and upper part.Figure 12 C show Figure 12 A decoding device by dotted line C around the detailed construction of figure middle and lower part.

The decoding device of Figure 12 A to 12C comprise a memory 205 that be used for to receive, two rib device for interchanging 200 and 203, two be used for the memory 202 and 206 of rib, by 30 check node calculation devices 201 ₁To 201 ₃₀The check node calculation device 201 that forms and by 90 variable node calculators 204 ₁To 204 ₉₀The variable node calculator 204 that forms.

In the decoding device of Figure 12 A to 12C, read simultaneously all message datas corresponding to 269 ribs from the memory 202 or 206 that is used for rib, and, by using this message data, calculate the new information data corresponding to these 269 ribs.In addition, will be stored in simultaneously as all new information data that result of calculation is determined the memory 206 or 202 that is used for rib of rear class.By reusing the decoding device of Figure 12 A to 12C, realized iterative decoding.Now, will be discussed in more detail below each parts.

The memory 206 that is used for rib is stored the variable node calculator 204 from prime simultaneously ₁To 204 ₉₀All message D206 ₁To D206 ₉₀, read message D206 at next clock (moment of next clock) ₁To D206 ₉₀As message D207 ₁To D207 ₉₀, and with them as message D200 (D200 ₁To D200 ₉₀) offer the rib device for interchanging 200 of rear class.Rib device for interchanging 200 rearranges the message D200 that (exchange) provides from the memory 206 that is used for rib according to the check matrix of Fig. 8 ₁To D200 ₉₀Order, and with them as D201 ₁To D201 ₃₀Offer check node calculation device 201 ₁To 201 ₃₀

Check node calculation device 201 ₁To 201 ₃₀By the message D201 that provides from rib device for interchanging 200 is provided ₁To D201 ₃₀Carry out the calculating according to formula (7), and the message D202 that will obtain as result of calculation ₁To D202 ₃₀Offer the memory 202 for rib.

The memory 202 that is used for rib is stored the check node calculation device 201 from prime simultaneously ₁To 201 ₃₀All message D202 that provide ₁To D202 ₃₀, and at the next one constantly with all message D202 ₁To D202 ₃₀As message D203 ₁To D203 ₃₀Offer the rib device for interchanging 203 of rear class.

Rib device for interchanging 203 rearranges the message D203 that provides from the memory 202 that is used for rib according to the check matrix of Fig. 8 ₁To D203 ₃₀Order, and with them as message D204 ₁To D204 ₉₀Offer variable node calculator 204 ₁To 204 ₉₀

Variable node calculator 204 ₁To 204 ₉₀By the message D204 that provides from rib device for interchanging 203 is provided ₁To D204 ₉₀, and the receive data D205 that provides from the memory 205 that be used for to receive ₁To D205 ₉₀, carry out the calculating according to formula (1), and the message D206 that will obtain as result of calculation ₁To D206 ₉₀Offer the memory 206 that is used for rib of rear class.

Figure 13 shows the check node calculation device 201 that is used for carrying out simultaneously check node calculation of Figure 12 A to Figure 12 C _m(m=1,2 ..., 30) topology example.

Check node calculation device 201 at Figure 13 _mIn, similar to the check node calculation device 101 of Figure 10, carry out the check node calculation of formula (7), and simultaneously all ribs are carried out check node calculation.

More particularly, at the check node calculation device 201 of Figure 13 _mIn, read simultaneously 200 that provide from the rib device for interchanging, from all the message D221 corresponding to the variable node of the every delegation of check matrix of Fig. 8 ₁To D221 ₉(v _i), and, will be as the absolute value D222 of 5 of its lower-orders separately ₁To D222 ₉(| v _i|) offer respectively LUT 221 ₁To 221 ₉Will be as message D221 ₁To D221 ₉(v _i) 1 bit sign position D223 of high-order position ₁To D223 ₉Offer respectively EXOR circuit 226 ₁To 226 ₉, and provide it to EXOR circuit 225.

LUT 221 ₁To 221 ₉Read respectively to absolute value D222 ₁To D222 ₉(| v _i|) carry out respectively in the formula (7)

Calculate 5 result of calculation D224 of gained ₁Extremely

And they are offered each adder 223 ₁To 223 ₉LUT 221 ₁To 221 ₉With result of calculation D224 ₁Extremely Offer adder 222.

222 couples of result of calculation D224 of adder ₁Extremely

The summation (for the summation of the result of calculation of delegation) of value calculate, and with 9 result of calculation D225 (

From i=1 to i=9) offer subtracter 223 ₁To 223 ₉Subtracter 223 ₁To 223 ₉From result of calculation D225, deduct respectively result of calculation D224 ₁Extremely

And with 5 subtraction value D227 ₁To D227 ₉Offer LUT224 ₁To 224 ₉That is to say subtracter 223 ₁To 223 ₉From by the message v from all ribs _iDetermined

Aggregate-value in deduct from by the message v from the rib that will determine _iDetermined And with subtraction value D227 ₁To D227 ₉(

From i=1 to i=8) offer respectively LUT 224 ₁To 224 ₉ LUT 224 ₁To 224 ₉Read subtraction value D227 ₁To D227 ₉Carry out in the formula (7)

Calculate 5 result of calculation D228 of gained ₁To D228 ₉, and export them.

On the other hand, EXOR circuit 225 is by calculating all sign bit D223 ₁To D223 ₉XOR, carry out sign bit D223 ₁To D223 ₉Multiply each other, and with 1 value D226 that multiplies each other (for the value that the multiplies each other (∏ sign (v of the sign bit of delegation _i), from i=1 to i=9)) offer each EXOR circuit 226 ₁To 226 ₉By calculating respectively multiply each other value D226 and sign bit D223 ₁To D223 ₉XOR, EXOR circuit 226 ₁To 226 ₉Determine to multiply each other value D226 respectively divided by sign bit D223 ₁To D223 ₉1 value D229 that is divided by of gained ₁To D229 ₉(∏ sign (v _i), from i=1 to i=8), and export them.

At check node calculation device 201 _mIn, with altogether 6 be output as the message D230 that obtains as the check node calculation result ₁To D230 ₉, wherein, make from LUT 224 ₁To 224 ₉5 result of calculation D228 of output ₁To D228 ₉Become separately 5 lower-order positions, and make from EXOR circuit 226 ₁To 226 ₉The value D229 that is divided by of output ₁To D229 ₉Become separately high-order position.

In the above described manner, at check node calculation device 201 _mIn, carry out the calculating of formula (7), and definite message u _j

In Figure 13, by hypothesis each message and sign bit are quantified as altogether 6 together check node calculation device 201 is shown _mThe circuit of Figure 13 is corresponding to a check-node.For the check matrix that will here process among Fig. 8, owing to have the check-node of 30 row, so the decoding device of Figure 12 A to 12C has 30 check node calculation devices 201 shown in Figure 13 _m, wherein, the 30th, the number of the row of check matrix.

Check node calculation device 201 at Figure 13 _mIn, can calculate simultaneously 9 message.For the capable weight of the check matrix that will here process among Fig. 8, the weight of the first row is 8, and the weight of the second row is 9, that is to say, having a kind of message number that offers check-node is 8 situation, is 9 situation and there are 9 kinds of message numbers.Therefore, the check node calculation device 201 ₁Have the circuit that can be similar to Figure 13 and the circuit structure that calculates simultaneously 8 message, and, remaining check node calculation device 20 disposed according to the mode identical with the circuit of Figure 13 ₁₂To 201 ₃₀

Figure 14 shows the variable node calculator 204 that is used for carrying out simultaneously variable node calculating of Figure 12 A to 12C _P(P=1,2 ..., 90) topology example.

Variable node calculator 204 at Figure 14 _PIn, similar to the variable node calculator 103 of Figure 11, the variable node that carries out formula (1) calculates, and simultaneously all ribs is carried out variable node and calculate.

More particularly, at the variable node calculator 204 of Figure 14 _PIn, read simultaneously 203 that provide from the rib device for interchanging, from all 6 the message D251 corresponding to the check-node of the every delegation of check matrix ₁To D251 ₅(message u _j), and these message are offered each adder 252 ₁To 252 ₅, and provide it to adder 251.In addition, receive data D271 is offered variable node calculator 204 from the memory 205 that is used for receiving _P, and receive data D271 offered adder-subtracter 252 ₁To 252 ₅

Adder 251 all message D251 of accumulative total ₁To D251 ₅(message u _j), and with 9 aggregate-value D252 (for total value (the ∑ u of the message of delegation _j, from j=1 to j=5)) offer adder-subtracter 252 ₁To 252 ₅Adder-subtracter 252 ₁To 252 ₅From additive value D252, deduct respectively message D251 ₁To D251 ₅(message u _j).That is to say adder-subtracter 252 ₁To 252 ₅Respectively from the message u from all ribs _jAggregate-value D252 in, deduct the message D251 from the rib that will determine ₁To D251 ₅(message u _j), and definite subtraction value (∑ u _j, from j=1 to j=4).

In addition, adder-subtracter 252 ₁To 252 ₅With receive data D271 (u _0i) be added to subtraction value (∑ u _j, from j=1 to j=4) on, and with 6 additive value D253 ₁To 253 ₅Export as variable node result of calculation.

In the above described manner, at variable node calculator 204 _PIn carry out the calculating of formula (1) and definite message v _i

In Figure 14, by hypothesis each message and sign bit are quantified as 6 together variable node calculator 204 is shown _PThe circuit of Figure 14 is corresponding to a variable node.For the check matrix among the Fig. 8 that will here process, owing to there are the variable nodes of 90 row, so the decoding device of Figure 12 A to 12C has 90 circuit shown in Figure 14, and wherein, 90 is the number of the row of check matrix.

Variable node calculator 204 at Figure 14 _PIn, might calculate simultaneously 5 message.With herein the reason Fig. 8 in check matrix have weight be respectively 5,3,2 and 1 15,45,29 and 1 row.Therefore, the variable node calculator 204 ₁To 204 ₉₀In 15 variable node calculators have the circuit structure identical with the circuit structure of Figure 14.Remaining 45,29 and 1 variable node calculator has the circuit that can be similar to Figure 14 and the circuit structure that calculates simultaneously 3,2 and 1 message.

Although also not shown in the decoding device in Figure 12 A to 12C, but, similar to the situation of Fig. 9, in the final stage of decoding, carry out the calculating of formula (5) rather than the variable node of formula (1) and calculate, and result of calculation is exported as final decoded result.

According to the decoding device of Figure 12 A to 12C, might calculate simultaneously all message corresponding to 269 ribs at a clock.

When decoding by the decoding device of reusing Figure 12 A to 12C, the check node calculation that hockets and variable node calculate, and can once decode with two clocks.Therefore, for example, in order to carry out 50 decodings, be 90 code when being the receive data of a frame when receiving code length wherein, decoding device need to 2 * 50=100 clock operation, like this, can use and the approximately uniform frequency of operation of receive frequency.Generally speaking and since the code length of LDPC code up to thousands of to tens thousand of, therefore, if use the decoding device of Figure 12 A to 12C, then can enlarge markedly the decoding number, and can expect to improve error-correcting performance.

Yet, in the decoding device of Figure 12 A to 12C, because the parallel message calculating of carrying out corresponding to all ribs of Tanner figure, so circuit scale and the proportional increase of code length.When the decoding device of Figure 12 A to 12C is configured to when having the equipment of the LDPC code decoding particular verified matrix, special code length and specific coding rate, this decoding device is difficult to have the decoding of LDPC code another check matrix, another code length and another encoding rate.That is to say that different from the decoding device of Fig. 9, the decoding device of Figure 12 A to 12C is difficult to deal with the decoding of various codes, also is so even only change control signal, and, high to the dependence of code.

Except the decoding device of Fig. 9 and Figure 12 A to 12C, for example, " VLSI Architectures for Iterative Decoders in Magnetic Recording Channels (the VLSI framework that is used for the iterative decoder of magnetic recording channels) " (IEEE Transactions on Magnetics at E.Yeo, P.Pakzad, B.Nikolic and V.Anantharam, Vol.37, No.2, March calendar year 2001) in, the implementation method that is used for calculating simultaneously as unit take 4 message rather than 1 message or entire message message has been described.In this case, usually, there is such problem: read when being difficult for avoiding from the different address of memory or write to the different address of memory the time, and, memory access control difficulty.

In addition, the method that realizes by approaching sum-product algorithm has also been proposed.Yet, in the method, cause mis-behave to occur.For sum-product algorithm is realized as hardware, as mentioned above, there is following methods: the method for carrying out continuously successively calculating corresponding to the message of rib (check node calculation and position node calculate); The method that parallel (complete parallel) carries out the calculating of all message; And the method that walk abreast (walking abreast) carries out message calculating with some units of being calculated as.

Yet, in carrying out successively the method for calculating corresponding to the message of rib, need high frequency of operation.Correspondingly, as the method that is used for increasing throughput, it is known being used for coming the method for advancing equipment with pipeline (pipeline) structure.In this case, circuit scale, specifically, memory (capacity) increases.

In the method for the parallel calculating of carrying out all message, the circuit scale that is used for logic increases, and high to the dependence of code.

In the method for the calculating of carrying out message that walks abreast with some units of being calculated as, memory access control difficulty.

Summary of the invention

Consider such situation and formed the present invention.The objective of the invention is frequency of operation is limited in the enough feasible scope, simultaneously restriction is used for the circuit scale of logic and memory, and easily control storage access.

Provide a kind of for the decoding device with the decoding of low-density checksum (LDPC) code, described LDPC code represents by the check matrix that is comprised of a plurality of submatrixs, described submatrix comprises P * P unit matrix, accurate unit matrix, shift matrix, and matrix, and P * P0 matrix, wherein accurate unit matrix is to have with 0 to have replaced one or more 1 unit matrix, shift matrix is unit matrix or the accurate unit matrix that is recycled displacement, with matrix be described unit matrix, described accurate unit matrix, with two or more in the described shift matrix and, described decoding device comprises: the first calculating unit, for carrying out simultaneously for P check node calculation with described LDPC code decoding; The second calculating unit, P the variable node that is used for carrying out simultaneously for described LDPC code decoding calculates; With the message stores parts, for the message data that reads and write corresponding to P bar rib, described message data obtains as the result of described P check node calculation or the calculating of described P variable node; Wherein, be 2 or larger submatrix for its weight, described message stores parts will be corresponding to the message stores of P bar rib at the identical address place, and described P bar rib belongs to adds up mutually that to form its weight be 2 or each unit matrix, accurate unit matrix and/or the shift matrix of larger described submatrix.

When following matrix when the submatrix, utilize the combination of a plurality of submatrixs to represent the check matrix of LDPC code, described matrix is: (the unit matrix of P * P); Accurate unit matrix has wherein replaced as one or more 1 of unit matrix element with 0; Shift matrix, wherein unit matrix or accurate unit matrix are recycled displacement; And matrix, its be the two or more of unit matrix, accurate unit matrix and shift matrix and; Or (0 matrix of P * P), decoding device of the present invention comprises: the first calculating unit is used for carrying out simultaneously P check node calculation that is used for the decoding of LDPC code; With the second calculating unit, be used for carrying out simultaneously P and be used for the variable node of LDPC code decoding is calculated.

The first calculating unit can have P check node calculation device that is used for carrying out check node calculation, and the second calculating unit can have P and be used for carrying out the variable node calculator that variable node calculates.

Decoding device can also comprise the message stores parts, is used for reading and to write simultaneously the message data corresponding to P bar rib, wherein, obtains described message data as the result of P check node calculation or P variable node calculating.

The message stores parts can be stored the message data corresponding to rib, wherein, and during check node calculation, on the direction of being expert at 1 filling (pack) of check matrix must more tight such mode be read described message data.

The message stores parts can be stored the message data corresponding to rib, and wherein, in the variable node computing interval, such mode reads described message data to get 1 filling of check matrix more closely on the direction of row.

When take weight as 1 unit matrix, accurate unit matrix or shift matrix and form represent to represent weight in the submatrix of check matrix as 2 or during larger submatrix, the message stores parts can be in the message of identical address place storage corresponding to P bar rib, wherein, to belong to weight be 1 unit matrix, accurate unit matrix or shift matrix to described P bar rib.

The message stores parts can comprise line number/P FIFO and columns/P FIFO, and described line number/P FIFO and columns/P FIFO have respectively a plurality of words corresponding to capable weight and the row weight of check matrix separately.

The message stores parts can comprise RAM (random access memory), and this RAM can be according to the message data filling being got more closely such mode according to reading sequential storage message data, and call over this message data according to the memory location.

Decoding device can also comprise reception information storage part spare, is used for the LDPC code information that storage receives, and reads simultaneously P reception information.

Receive information storage part spare and can store in such a manner received information, this mode is: can read received information according to calculate necessary order for variable node.

Decoding device can also comprise and rearrange parts, is used for rearranging the message that obtains as the result of P check node calculation or P variable node calculating.

Rearrange parts and can comprise barrel shifter (barrel shifter).

The first calculating unit and the second calculating unit can be determined the message corresponding to P bar rib.

The first calculating unit can carry out some of a described P check node calculation and P variable node calculating, and the second calculating unit can carry out described P variable node calculating some other.

The first calculating unit can comprise P calculator be used to some of carrying out that a described P check node calculation and P variable node calculate, and the second calculating unit can comprise be used to some other P the calculator that carries out described P variable node calculating.

Decoding device can also comprise middle (in-progress) result store parts of the first decoding, for the first decoding intermediate object program that reads and write simultaneously corresponding to P bar rib, wherein, the first calculating unit obtains described the first decoding intermediate object program by some of carrying out that a described P check node calculation and P variable node calculate.

The first decoding intermediate object program memory unit can get more closely such mode and stores corresponding to first of the rib intermediate object program of decoding according to go up in the row direction 1 filling with check matrix, wherein, when carry out that described P variable node calculate some other the time read described the first decoding intermediate object program.

The first decoding intermediate object program memory unit can be two single port RAM (random access memory).

Described two single port RAM can take first the decoding intermediate object program P as unit alternately store first the decoding intermediate object program.

Each can read the first decoding intermediate object program that is stored in the identical address place described two single port RAM (random access memory).

When take weight as 1 unit matrix, accurate unit matrix or shift matrix and form represent to represent weight in the submatrix of check matrix as 2 or during larger submatrix, the first decoding intermediate object program memory unit can be in the first decoding intermediate object program of identical address place storage corresponding to P bar rib, wherein, to belong to weight be 1 unit matrix, accurate unit matrix or shift matrix to described P bar rib.

Decoding device can also comprise the second decoding intermediate object program memory unit, for the second decoding intermediate object program that reads and write simultaneously corresponding to P bar rib, wherein, the second calculating unit obtains described the second decoding intermediate object program by some other that carries out that described P variable node calculate.

Decoding device can also comprise reception information storage part spare, is used for the LDPC code information that storage receives, and reads simultaneously P reception information.

Receive information storage part spare and can store in such a manner received information, this mode is: can read received information according to some other necessary order of calculating for described P variable node.

Decoding device can also comprise and rearrange parts, is used for rearranging by the first calculating unit by some first decoding intermediate object programs that obtain of carrying out a described P check node calculation and P variable node and calculating or second intermediate object programs of decoding of being obtained by some other that carries out described P variable node calculating by the second calculating unit.

Rearrange parts and can comprise barrel shifter.

The first calculating unit can carry out some of a described P check node calculation, and the second calculating unit can carry out some other and P variable node of a described P check node calculation and calculates.

The first calculating unit can comprise be used to some P the calculator that carries out a described P check node calculation, and the second calculating unit can comprise be used to some other and P P the calculator that variable node calculates of carrying out a described P check node calculation.

Decoding device can also comprise the first decoding intermediate object program memory unit, for the first decoding intermediate object program that reads and write simultaneously corresponding to P bar rib, wherein, the first calculating unit obtains described the first decoding intermediate object program by some of carrying out a described P check node calculation.

Decoding device can also comprise the second decoding intermediate object program memory unit, for the second decoding intermediate object program that reads and write simultaneously corresponding to P bar rib, wherein, the second calculating unit calculates to obtain described second intermediate object program of decoding by some other and P the variable node that carries out a described P check node calculation.

The second decoding intermediate object program memory unit can be stored the second decoding intermediate object program corresponding to rib, wherein, when some other and P the variable node that carry out a described P check node calculation calculate, read described second intermediate object program of decoding according on column direction, 1 filling of check matrix being got more closely such mode.

The second decoding intermediate object program memory unit can be two single port RAM (random access memory).

Described two single port RAM can take second the decoding intermediate object program P as unit alternately store second the decoding intermediate object program.

Each can read the second decoding intermediate object program that is stored in the identical address place described two single port RAM (random access memory).

When take weight as 1 unit matrix, accurate unit matrix or shift matrix and form represent to represent weight in the submatrix of check matrix as 2 or during larger submatrix, the second decoding intermediate object program memory unit can be in the second decoding intermediate object program of identical address place storage corresponding to P bar rib, wherein, to belong to weight be 1 unit matrix, accurate unit matrix or shift matrix to described P bar rib.

Decoding device can also comprise reception information storage part spare, is used for the LDPC code information that storage receives, and reads simultaneously P reception information.

In decoding device according to claim 36, receive information storage part spare and can store in such a manner received information, this mode is: can calculate necessary order according to some other and P the variable node for a described P check node calculation and read received information.

Decoding device can also comprise and rearrange parts, is used for rearranging by the first calculating unit some first decoding intermediate object programs that obtain by carrying out a described P check node calculation or second intermediate object program of decoding that is obtained by some other and P the variable node calculating of carrying out a described P check node calculation by the second calculating unit.

Rearrange parts and can comprise barrel shifter.

When following matrix when the submatrix, utilize the combination of a plurality of submatrixs to represent the check matrix of LDPC code, wherein said matrix is: (the unit matrix of P * P); Accurate unit matrix has wherein replaced as one or more 1 of unit matrix element with 0; Shift matrix, wherein unit matrix or accurate unit matrix are recycled displacement; And matrix, its be the two or more of unit matrix, accurate unit matrix and shift matrix and; Or (0 matrix of P * P); Coding/decoding method of the present invention comprises: the first calculation procedure, carry out simultaneously P check node calculation that is used for the decoding of LDPC code; And second calculation procedure, carry out simultaneously P and be used for the variable node of LDPC code decoding is calculated.

Program of the present invention comprises: the first calculation procedure, carry out simultaneously P check node calculation that is used for the decoding of LDPC code; And second calculation procedure, carry out simultaneously P and be used for the variable node of LDPC code decoding is calculated.

In the present invention, when following matrix when the submatrix, utilize the combination of a plurality of submatrixs to represent the check matrix of LDPC code, wherein said matrix is: (the unit matrix of P * P); Accurate unit matrix has wherein replaced as one or more 1 of unit matrix element with 0; Shift matrix, wherein unit matrix or accurate unit matrix are recycled displacement; And matrix, its be the two or more of unit matrix, accurate unit matrix and shift matrix and; Or (0 matrix of P * P) carries out P check node calculation that is used for the decoding of LDPC code simultaneously, and carries out simultaneously P and be used for the variable node of LDPC code decoding is calculated.

Description of drawings

Fig. 1 illustrates the check matrix H of LDPC code.

Fig. 2 is that diagram is used for the flow chart with the process of LDPC code decoding.

Fig. 3 illustrates message flow.

Fig. 4 illustrates the check matrix example of LDPC code.

Fig. 5 illustrates the Tanner figure of check matrix.

Fig. 6 illustrates variable node.

Fig. 7 illustrates check-node.

Fig. 8 illustrates the check matrix example of LDPC code.

Fig. 9 is the block diagram that illustrates for the topology example of the LDPC code decoding device that carries out successively node calculating.

Figure 10 is the block diagram that illustrates for the topology example of the check node calculation device that calculates successively message.

Figure 11 is the block diagram that illustrates for the topology example of the variable node calculator that calculates successively message.

Figure 12 A is the block diagram that illustrates for the topology example of the LDPC code decoding device that carries out simultaneously all nodes calculating.

Figure 12 B is the block diagram that illustrates for the topology example of the LDPC code decoding device that carries out simultaneously all nodes calculating.

Figure 12 C is the block diagram that illustrates for the topology example of the LDPC code decoding device that carries out simultaneously all nodes calculating.

Figure 13 is the block diagram that illustrates for the topology example of the check node calculation device that calculates simultaneously message.

Figure 14 is the block diagram that illustrates for the topology example of the variable node calculator that calculates simultaneously message.

Figure 15 illustrates the matrix that is divided into Unit 5 * 5.

Figure 16 A is the block diagram that the topology example of using decoding device embodiment of the present invention is shown.

Figure 16 B is the block diagram that the topology example of using decoding device embodiment of the present invention is shown.

Figure 16 C is the block diagram that the topology example of using decoding device embodiment of the present invention is shown.

Figure 17 is the flow chart of decode procedure of the decoding device of pictorial image 16A to 16C.

Figure 18 is the block diagram that the topology example of using decoding device embodiment of the present invention is shown.

Figure 19 is the block diagram that the topology example of check node calculation device is shown.

Figure 20 is the block diagram that the topology example of variable node calculator is shown.

Figure 21 is the block diagram that the calculator structure example of Figure 18 is shown.

Figure 22 is the block diagram that the calculator structure example of Figure 18 is shown.

Figure 23 is the block diagram that the memory construction example that is used for storage decoding intermediate object program of Figure 18 is shown.

Figure 24 is the sequential chart of the RAM operation that is used for storage decoding intermediate object program of diagram Figure 18.

Figure 25 is the flow chart of decode procedure of the decoding device of diagram Figure 18.

Figure 26 is the block diagram that the topology example of using decoding device embodiment of the present invention is shown.

Figure 27 is the block diagram that the topology example of check node calculation device is shown.

Figure 28 is the block diagram that the topology example of variable node calculator is shown.

Figure 29 is the block diagram of topology example that the calculator of Figure 26 is shown.

Figure 30 is the block diagram of topology example that the calculator of Figure 26 is shown.

Figure 31 is the block diagram that the memory construction example that is used for storage decoding intermediate object program of Figure 26 is shown.

Figure 32 is the sequential chart of the RAM operation that is used for storage decoding intermediate object program of diagram Figure 31.

Figure 33 is the flow chart of decode procedure of the decoding device of diagram Figure 26.

Figure 34 is the block diagram that the topology example of using computer-implemented example of the present invention is shown.

Embodiment

Below, describe application specific embodiment of the present invention in detail with reference to accompanying drawing.

Figure 15 shows the example of 30 * 9 check matrixes that are divided into 5 * 5 matrix units.The check matrix of Figure 15 is identical with the check matrix shown in Fig. 8.

In Figure 15, represent check matrix with the combination of following matrix: 5 * 5 unit matrixs; With 0 matrix (hereinafter, being called " accurate unit matrix " in suitable place) that has replaced the element-one or more 1 of unit matrix; Unit matrix or accurate unit matrix are recycled the matrix (hereinafter, being called " shift matrix " in suitable place) of displacement; Two or more (a plurality of) of unit matrix, accurate unit matrix and shift matrix and (hereinafter, being called " and matrix " in suitable place); With 5 * 50 matrix.Having 2/3 encoding rate and value by the LDPC code of the check matrix of Figure 15 representative is 9 code length.

Can say that the check matrix of Figure 15 is formed by 5 * 5 matrixes, accurate unit matrix, shift matrix and matrix and 0 matrix.Therefore, hereinafter, will call " submatrix " to these 5 * 5 matrixes that form check matrix in suitable place.

Figure 16 A to 16C shows the topology example for the decoding device embodiment of the LDPC code decoding that will be represented by the check matrix of Figure 15.Figure 16 A to 16C is the block diagram that the topology example of this decoding device embodiment is shown.Figure 16 A shows the general structure of decoding device.Figure 16 B show Figure 16 A decoding device by dotted line B around figure in the detailed construction of left part.Figure 16 C show Figure 16 A decoding device by dotted line C around figure in the detailed construction of right part.

The decoding device 300 of Figure 16 A to 16C comprises: switch 310 and 315, by 6 FIFO 311 ₁To 311 ₆The rib data storage 311 that forms, selector 312, by 5 check node calculation devices 313 ₁To 313 ₅The check node calculation device 313 that forms, two cyclic shift circuits 314 and 320, by 18 FIFO 316 _{1 to}316 ₁₈The rib data storage 316 that forms, selector 317, be used for receive data memory 318, variable node calculator 319 and the control assembly 321 of storage received information.

Before describing each parts of decoding device 300 in detail, will describe that at first data are stored in method in rib data storage 311 and 316.

Rib data storage 311 comprises 6 FIFO 311 ₁To 311 ₆, this number is that line number order 30 with check matrix is divided by line number order 5 gained.FIFO 311 _y(y=1,2 ..., 6) form by this way: can read simultaneously or write the message corresponding to 5 ribs, wherein, 5 is the number of the row and column of submatrix.Its length (level number) is 9, and this is the maximum number (Hamming weight) of 1 on the line direction of check matrix.

At FIFO 311 ₁In, with for every delegation, (on column direction) gets more closely such mode (to ignore 0 mode) with 1 filling and stores data corresponding to 1 the position of walking to the 5th row from the 1st of the check matrix of Figure 15 in the horizontal direction.That is to say, if the capable i tabulation of j is shown (j, i), then at FIFO 311 ₁The 1st element (first order) in, storage is corresponding to the data from 1 position of 5 * 5 unit matrixs of (1,1) to (5,5) of check matrix.In the 2nd element, storage is corresponding to the data from 1 position of the shift matrix of (1,21) to (5,25) of check matrix (with 5 * 5 unit matrixs shift matrix of loopy moving 3 to the right), and this shift matrix is the submatrix of check matrix.In addition, in the 3rd to the 8th element, similarly, store in such a manner data, so that corresponding to the submatrix of check matrix.In the 9th element, storage is corresponding to from (1 of check matrix, 86) to the shift matrix of (5,90) (with 0 replaced the first row in 5 * 5 unit matrixs 1, and with this unit matrix shift matrix of loopy moving 1 left) the data of 1 position.Here, from (1,86) of check matrix to the shift matrix of (5,90), owing to do not have 1 in the first row, therefore only to FIFO 311 ₁The first row, element number becomes 8, and for remaining row, element number becomes 9.

At FIFO 311 ₂In, storage is corresponding to the data of 1 the position of walking to the 10th row from the 6th of the check matrix of Figure 15.That is to say, at FIFO 311 ₂The 1st element in, storage corresponding to form check matrix from (6,1) to (10,5) and matrix (should and matrix be the first shift matrix and the second shift matrix and, wherein, in the first shift matrix, 5 * 5 unit matrixs are by loopy moving 1 to the right, in the second shift matrix, 5 * 5 unit matrixs are by loopy moving 2 to the right) the data of 1 position of the first shift matrix.In the second element, storage is corresponding to the data of 1 position of from (6,1) to (10,5) and the second shift matrix matrix that forms check matrix.

More particularly, be 2 or larger submatrix for weight, when with the two or more of following matrix and form when representing submatrix, will be that the data (corresponding to the message of the rib that belongs to unit matrix and matrix or shift matrix) of 1 position of 1 unit matrix, accurate unit matrix or shift matrix are stored in identical address (FIFO 311 corresponding to weight ₁To 311 ₆In identical FIFO) locate, wherein, described matrix is: weight is the 1 (unit matrix of P * P); Accurate unit matrix wherein, has replaced as one or more 1 of the element of unit matrix with 0; And shift matrix, wherein, unit matrix or accurate unit matrix are recycled displacement.

Subsequently, for the 3rd to the 9th element, store by this way data, so that corresponding to check matrix.For all row, FIFO 311 ₂Element number be 9.

Similarly, for FIFO 311 ₃To 311 ₆, store by this way data, so that corresponding to check matrix, and FIFO 311 ₃To 311 ₆Each length be 9.

Be used for storage rib data storage device 316 by 18 FIFO 316 ₁To 316 ₁₈Consist of, this number is that the line number order 90 of check matrix is divided by line number order 5 gained of submatrix.Consist of by this way FIFO 316 _x(x=1,2 ..., 18), this mode is: can read simultaneously or write the message corresponding to 5 ribs, this number is line number order and the column number of submatrix.

At FIFO 316 ₁In, with for each row, in vertical direction (in the row direction) upper 1 filling is got the data that more closely such mode (to ignore 0 mode) is stored check matrix corresponding to Figure 15 1 position from the 1st row to the 5th row.That is to say, at FIFO 316 ₁The first element (first order) in, storage is corresponding to the data of 1 position of 5 * 5 unit matrixs of check matrix from (1,1) to (5,5).In the second element, storage is corresponding to forming (6 of check matrix, 1) to (10,5) and matrix (should and matrix be the first shift matrix and the second shift matrix and, wherein, in the first shift matrix, 5 * 5 unit matrixs are by loopy moving 1 to the right, in the second shift matrix, 5 * 5 unit matrixs are by loopy moving 2 to the right) the data of 1 position of the first shift matrix.In the 3rd element, storage is corresponding to the data of 1 position of (6,1) to (10,5) and the second shift matrix matrix that forms check matrix.

More particularly, be 2 or larger submatrix for weight, when with the two or more of following matrix and form when representing submatrix, will be that the data (corresponding to the message of the rib that belongs to unit matrix, accurate unit matrix or shift matrix) of 1 position of 1 unit matrix, accurate unit matrix or shift matrix are stored in identical address (FIFO 316 corresponding to weight ₁To 316 ₁₈In identical FIFO) locate, wherein, described matrix is: weight is the 1 (unit matrix of P * P); Accurate unit matrix, wherein, with 0 element 1 that has replaced unit matrix; And shift matrix, wherein, unit matrix or accurate unit matrix are recycled displacement.

Subsequently, for the 4th and the 5th element, store equally by this way data, so that corresponding to check matrix.FIFO 316 ₁Element number (level number) be 5, this number is the maximum number (Hamming weight) of check matrix 1 on from the 1st row to the line direction of the 5th row.

In addition, for FIFO 316 ₂With 316 ₃, similarly, store by this way data, so that corresponding to check matrix, and each of its length (number of level) is 5.In addition, for FIFO316 ₄To 316 ₁₂, similarly, store by this way data, so that corresponding to check matrix, and each of its length is 3.In addition, for FIFO 316 ₁₃To 316 ₁₈, similarly, store by this way data, so that corresponding to check matrix, and each of its length is 2.Yet, because FIFO 316 ₁₈The 1st element corresponding to (1,86) of check matrix to (5,90), and in the 5th row ((1,90) of check matrix is to (5,90)), do not have 1, therefore, do not store data.

Now, with the description that provides in detail below the operation of each parts of the decoding device 300 of Figure 16 A to 16C.5 message (data) D319 is offered switch 310 from cyclic shift circuits 320.In addition, control signal D320 is offered switch 310 from control assembly 321, wherein, control signal D320 indication belongs to which information (matrix data) of check matrix about message (data).Based on control signal D320, from FIFO 311 ₁To 311 ₆Middle selection is used for the FIFO of storage 5 message (data) D319, and with these 5 message data D319 in order collective be stored among the selected FIFO.

Rib data storage 311 comprises 6 FIFO 311 ₁To 311 ₆ FIFO 311 at rib data storage 311 ₁To 311 ₆In, from switch 310 in order collective provide 5 message D319, and FIFO311 ₁To 311 ₆(simultaneously) collective stores this 5 message D319 in order.In addition, when wanting reading out data, rib data storage 311 is from FIFO 311 ₁In read in turn these 5 message (data) D311 ₁, and they are offered the selector 312 of rear class.From FIFO 311 ₁Read message D311 ₁After finishing, rib data storage 311 is also respectively from FIFO 311 ₁To 311 ₆Read in turn message D311 ₁To D311 ₆, and they are offered selector 312.

To select signal D321 to offer selector 312 from control assembly 321, and, also with 5 message (data) D311 ₁To D311 ₆Offer selector 312 from rib data storage 311, wherein, select signal D321 indication from FIFO 311 ₁To 311 ₆The FIFO (the current FIFO that therefrom reads data) of message data is therefrom read in middle selection.Selector 312 is according to selection signal D321 and from FIFO 311 ₁To 311 ₆The current FIFO that therefrom reads data of middle selection, and will offer check node calculation parts 313 as message D312 from 5 message datas that selected FIFO provides.

Check node calculation parts 313 comprise 5 check node calculation devices 313 ₁To 313 ₅5 message D312 are offered check node calculation parts 313 by selector 312, and message D312 is offered separately check node calculation device 313 ₁To 313 ₅Each.In addition, control signal D322 is offered check node calculation device 313 from control assembly 321, and control signal D322 is offered check node calculation device 313 ₁To 313 ₅Check node calculation device 313 ₁To 313 ₅By carrying out simultaneously the calculating according to formula (7) with message D312, and, determine the message D313 corresponding to 5 ribs as result of calculation.Check node calculation parts 313 are by check node calculation device 313 ₁To 313 ₅To offer cyclic shift circuits 314 as 5 message D313 that result of calculation obtains.

Offer the control signal D322 of check node calculation device 313 corresponding to the control signal D106 of Figure 10 from control assembly 321.Check node calculation parts 313 ₁To 313 ₅Disposed according to the mode identical with the check node calculation device 101 shown in Figure 10 separately.

5 message D313 that will calculate in check node calculation parts 313 offer cyclic shift circuits 314.In addition, control signal D323 is offered cyclic shift circuits 314 from control assembly 321, wherein, control signal D323 indication is about the information (matrix data) of such fact, and this fact is: connect rib corresponding to message D313 as the result of the unit matrix cyclic shift how many times that for example will form the check matrix basis.Cyclic shift circuits 314 with 5 message D313 cyclic shifts, and offers switch 315 with the result as message D314 according to control signal D323.

Control signal D324 is offered switch 315, and message D314 offered switch 315 from cyclic shift circuits 314, wherein, the information of which row of check matrix is provided about 5 message (data) D314 that provides from cyclic shift circuits 314 in control signal D324 indication.Based on control signal D324, switch 315 is from FIFO 316 ₁To 316 ₁₈Middle selection is used for the FIFO of storing message D314, and collective provides this 5 message D314 in order.

Rib data storage 316 comprises 18 FIFO 316 ₁To 316 ₁₈With 5 message D314 in order (simultaneously) offer the FIFO 316 of rib data storage 316 from switch 315 collectives ₁To 316 ₁₈, and FIFO 316 ₁To 316 ₁₈Collective stores this 5 message D314 in order.In addition, when wanting reading out data, be used for storage rib data storage device 316 from FIFO 316 ₁In read in turn 5 message D315 ₁, and they are offered the selector 317 of rear class.From FIFO 316 ₁After reading out data is finished, be used for storage rib data storage device 316 also from FIFO 316 ₁To 316 ₁₈Read in turn message D315 ₂To D313 ₁₈, and they are offered selector 317.

To select signal D325 to offer selector 317 from control assembly 321, and, also with message data D315 ₁To D313 ₁₈Offer selector 317 from rib data storage 316, wherein, select signal D325 indication from FIFO 316 ₁To 316 ₁₈Middle selection is used for reading the FIFO (the current FIFO that therefrom reads data) of message data.Based on selecting signal D325, selector 317 is from FIFO 316 ₁To 316 ₁₈The current FIFO that therefrom reads data of middle selection, and will offer from 5 message datas that selected FIFO provides the piece (not shown) of variable node calculating unit 319 and above-mentioned calculating be used to carrying out formula (5) as message D316.

On the other hand, the memory 318 that is used for received data from the information calculations that receives by communication channel reception LLR (log-likelihood ratio).5 reception LLR that calculate are offered variable node calculating unit 319 as received data D317 (LDPC code) collective (simultaneously) and be used for the piece (not shown) of the calculating of receiving type (5).The memory 318 that is used for received data calculates necessary order according to the variable node for variable node calculating unit 319 and reads received data D317.

Variable node calculating unit 319 comprises 5 variable node calculators 319 ₁To 319 ₅5 message D316 are offered variable node calculating unit 319 by selector 317, and message D316 is offered separately variable node calculator 319 ₁To 319 ₅Each.In addition, 5 received data D317 are offered variable node calculating unit 319 from the memory 318 that is used for received data, and received data D317 is offered separately variable node calculator 319 ₁To 319 ₅Each.In addition, control signal D326 is offered variable node calculating unit 319 from control assembly 321, and control signal D326 is offered variable node calculator 319 ₁To 319 ₅

Variable node calculator 319 ₁To 319 ₅By carrying out the calculating according to formula (1) with message D316 and received data D317, and, determine the message D318 corresponding to 5 ribs as result of calculation.Variable node calculating unit 319 will be as variable node calculator 319 ₁To 319 ₅5 message D318 obtaining of result offer cyclic shift circuits 320.

Here, offer the control signal D326 of variable node calculating unit 319 corresponding to the control signal D107 of Figure 11 from control assembly 521, and, variable node calculator 319 ₁To 319 ₅Disposed according to the mode identical with the variable node calculator 103 of Figure 11 separately.

5 message D318 are offered cyclic shift circuits 320 from variable node calculating unit 319.In addition, control signal D327 is offered cyclic shift circuits 320 from control assembly 321, this control signal D327 indication is about the information (matrix data) of such fact, and this fact is: connect rib corresponding to message D318 as the result of the unit matrix cyclic shift how many times that for example will form the check matrix basis.Based on control signal D327, cyclic shift circuits 320 rearranges the cyclic shift of message D327, and the result is offered switch 310 as message D319.

Control assembly 321 will select signal D320 to offer switch 320, and will select signal D321 to offer selector 312, in order to control respectively them.Control assembly 321 offers check node calculation parts 313 with control signal D322, and control signal D323 is offered cyclic shift circuits 314, and control signal D324 is offered switch 315, in order to control respectively them.In addition, control assembly 321 will select signal D325 to offer selector 317, and control signal D326 is offered variable node calculating unit 319, and control signal D327 is offered cyclic shift circuits 320, in order to control respectively them.

As the result with the aforesaid operations circulation primary, can carry out the decoding of a LDPC code.After the decoding device of Figure 16 A to 16C had been decoded the LDPC code pre-determined number, decoding device 300 was determined final decoded result (not shown) according to formula (5), and exports it.

For the part that lacks rib data (corresponding to the message of rib), in being stored in memory during (when data being stored in rib data storage 311 and 316), not storing message.In node computing interval (during the check node calculation at check node calculation parts 313 places and in variable node computing interval at variable node calculating unit 319 places), do not calculate.

Figure 17 is the flow chart of decode procedure of the decoding device 300 of pictorial image 16A to 16C.When the memory 318 that the data that will decode that receive is stored in for received data, begin this process.

In step S31, variable node calculating unit 319 carries out variable node and calculates.

More particularly, with 5 message D316 (message u _j) offer variable node calculating unit 319 by selector 317.That is to say that rib data storage 316 is from FIFO 316 ₁In read in turn 5 message D316 of step S39 (will describe afterwards) storage ₁, and, subsequently, also from FIFO 316 ₂To 316 ₁₈Read in turn message D316 ₂To D316 ₁₈, and they are offered selector 317.

To select signal D307 to offer selector 317 from control assembly 321, and wherein, select signal D307 indication from FIFO 316 ₁To 316 ₁₈The FIFO (the current FIFO that therefrom reads data) of message (data) will be therefrom read in middle selection, in addition, and with message data D316 ₁To D316 ₁₈Offer selector 317 from rib data storage 316.Based on selecting signal D307, selector 317 is from FIFO 316 ₁To 316 ₁₈The current FIFO that therefrom reads data of middle selection, and will offer variable node calculating unit 319 as message D316 from 5 message datas that selected FIFO provides.

When not yet the received data D309 that provides from memory 306 being carried out check node calculation and message D304 when not being stored in the rib data storage 316, variable node calculating unit 319 is with message u _jBe set to the initial value for variable node calculating.

With 5 received data D309 (reception value u of institute _0i) offer variable node calculating unit 319 from the memory 318 that is used for received data, and, received data D309 is offered separately variable node calculator 319 ₁To 319 ₅Each.In addition, control signal D315 is offered variable node calculating unit 319 from control assembly 321, and control signal D315 is offered variable node calculator 319 ₁To 319 ₅

Based on control signal D315, variable node calculator 319 ₁To 319 ₅By carrying out simultaneously the calculating according to formula (1) with message D316 and received data D309, and determine 5 message D319 as result of calculation.

That is to say, offered the control signal D315 of variable node calculating unit 319 by control assembly 321 corresponding to the control signal D107 that describes with reference to above-mentioned Figure 11.Variable node calculator 319 ₁To 319 ₅Each read an essential message D314 (D316) by selector 317 from rib data storage 316 according to control signal D309, and, 5 received data D309 that provide from the memory 318 that is used for received data also are provided respectively, carry out variable node and calculate, and determine simultaneously 5 message D319 as result of calculation.

After the processing of step S31, this process proceeds to step S32, and at this step place, variable node calculating unit 319 will be as variable node calculator 319 ₁To 319 ₅Variable node result of calculation and 5 message D319 (message v obtaining _i) offer cyclic shift circuits 320.Then, this process proceeds to step S33.

At step S33,5 message D318 cyclic shifts (rearranging) that cyclic shift circuits 320 will provide from variable node calculating unit 319.

More particularly, message D318 is offered cyclic shift circuits 320 from variable node calculating unit 319.In addition, control signal D327 is offered cyclic shift circuits 320 from control assembly 321, wherein, control signal D327 indication is about the information (matrix data) of such fact, and this fact is: as the unit matrix cyclic shift that for example will form the check matrix basis result of how many times connect the rib that connects corresponding to message D318.Based on control signal D327, cyclic shift circuits 320 is 5 message D327 cyclic shifts, and the result is offered switch 310 as message D319.

After the processing of step S33, this process proceeds to step S34, and at this step place, switch 310 will offer rib data storage 311 from 5 message D319 that cyclic shift circuits 320 provides.

More particularly, message (data) 304 are offered switch 310 from cyclic shift circuits 320, in addition, control signal D312 is offered switch 310, wherein, control signal D312 indication belongs to which information of check matrix about message D304.Based on control signal D312, switch 310 is from FIFO300 ₁To 300 ₆Middle selection is used for the FIFO of storing message D304, and in turn 5 message data D304 collectives is stored among the selected FIFO.

Then, the FIFO 300 of rib data storage 311 ₁To 300 ₁₈5 message data D304 that provide from switch 310 are provided in collective in order.

After the processing of step S34, this process proceeds to step S35, and at this step place, control assembly 321 determines whether variable node calculating unit 319 has calculated the message of the total number of rib.When the message of the total number of determining not calculate rib, this process is returned step S31, and again carries out above-mentioned processing.

On the other hand, when determining that at step S35 variable node calculating unit 319 has calculated the message of total number of rib, this process proceeds to step S36, and at this step place, check node calculation parts 313 carry out check node calculation.

More particularly, 5 message D302 are offered check node calculation parts 313 by selector 312.That is to say that rib data storage 311 is from FIFO 311 ₁Read in turn 5 message D311 of step S34 storage ₁(message v _i), subsequently, also from FIFO 311 ₂To 311 ₆Read in turn message data D311 ₂To D311 ₆, and it is offered selector 312.

To select signal D321 to offer selector 312 from control assembly 321, this control signal D321 indicates from FIFO 311 ₁To 311 ₆Middle selection is used for reading the FIFO (the current FIFO that therefrom reads data) of message data, in addition, and with message data D311 ₁To D311 ₆Offer selector 312 from rib data storage 311.Based on selecting signal D321, selector 301 is selected the current FIFO that therefrom reads data, and will offer check node calculation parts 313 as message D311 from 5 message datas that selected FIFO provides.

In addition, control signal D322 is offered check node calculation parts 313 from control assembly 321.Based on control signal D322, the check node calculation device 313 of check node calculation parts 313 ₁To 313 ₅Carry out simultaneously the check node calculation according to formula (7) by using message D302, and, determine 5 message D303 (message u as result of calculation _j).

More particularly, offer the control signal D322 of check node calculation parts 313 corresponding to the control signal D106 among above-mentioned Figure 10 by control assembly 321.Based on control signal D322, when check node calculation device 313 ₁To 313 ₅When reading an essential message D311 (D312) by selector 312 from rib data storage 311, they each carry out check node calculation, and determine simultaneously 5 message D313 as the result who calculates.

After the processing of step S37, this process proceeds to step S38, and at this step place, check node calculation parts 313 will output to cyclic shift circuits 314 as 5 message D313 that the check node calculation result obtains.Then, this process proceeds to step S38.

At step S38,5 message D313 cyclic shifts that cyclic shift circuits 314 will provide from check node calculation parts 313.

More particularly, message D313 is offered cyclic shift circuits 314 from check node calculation parts 313.In addition, control signal D314 is offered cyclic shift circuits 314 from control assembly 321, this control signal D314 indication is about the information (matrix data) of such fact, and this fact is: connect rib corresponding to message D313 as the result of the unit matrix cyclic shift how many times that for example will form the check matrix basis.Based on control signal D314, cyclic shift circuits 314 is 5 message D313 cyclic shifts, and the result is offered switch 315 as message D304.

After the processing of step S38, this process proceeds to step S39, and in this step, switch 315 will be stored in the rib data storage 316 from 5 message D304 that cyclic shift circuits 314 provides.

More particularly, 5 message (data) D304 is offered switch 316 from cyclic shift circuits 314, in addition, control signal D324 is offered switch 316 from cyclic shift circuits 314, and this control signal D324 indication belongs to which information of check matrix about message (data) D304.Based on control signal D324, switch 316 is from the FIFO 316 of rib data storage 316 ₁To 316 ₁₈Middle selection is used for the FIFO of storing message D304, and in order 5 message data D304 collectives is offered selected FIFO.

Then, the FIFO 316 of rib data storage 316 ₁To 316 ₁₈5 message data D304 that provide from switch 316 are provided in collective in order.

After the processing of step S39, this process proceeds to step S40, and in this step, control assembly 321 determines whether check node calculation parts 313 have calculated the message of the total number of rib.When the message of the total number of determining also not calculate rib, this process is returned step S36, and again carries out above-mentioned processing.

On the other hand, when the message of total number of rib of having determined check node calculation parts 313 as calculated at step S40 control assembly 321, this process is finished.

Carry out the terminal check node when calculating when decoding device 300 repeats described decoding number and check node calculation parts 313 with the decode procedure of Figure 17, will offer as the message D304 that the check node calculation result obtains the piece (not shown) of above-mentioned calculating be used to carrying out formula (5) from rib data storage 316 by selector 317.Also received data D309 is offered described (not shown) from the memory 306 that is used for received data.Described (not shown) be by carrying out the calculating of formula (5) with message D304 and received data D309, and with result of calculation as final decoded result output.

In the superincumbent description, although store rib data (although utilizing FIFO to form rib data storage 311 and 316) with FIFO, can replace FIFO with RAM.In this case, for RAM, need to read simultaneously the bit width of P rib information (corresponding to the message of rib) and total number/P word of rib.For being written among the RAM, determining when reading the data that will write, which position to read this data on the basis of check matrix information next time, and write data into that position.For reading from RAM, from the beginning of this address reading out data in turn.That is to say, in RAM, come in this order the storing message data, wherein, such mode reads this message data the message data filling is got more closely, and, read message data according to the memory location order.If replace FIFO with RAM, then selector 312 and 317 is not indispensable.

When the physical bit width of FIFO and RAM is inadequate, by providing identical control signal with a plurality of RAM, these logically can be assumed to be a RAM.

In the decoding device 300 of Figure 16 A to 16C, by using the message u that obtains as the check node calculation result _jCarry out variable node and calculate, and, by using the message v that obtains as this result of calculation _iCarry out check node calculation.Therefore, need to be used for all message u of storage _jWith all message v _i Rib data storage 311 and rib data storage 316, wherein, message u _jCorresponding to the rib that obtains as the check node calculation result, and message v _iCorresponding to the rib that obtains as variable node result of calculation.That is to say, in decoding device, need the nearly memory of the required capacity of 2 times message of 1 number of check matrix H of storage.

Therefore, in order further to reduce the circuit scale of decoding device, the decoding device that memory span is further reduced when comparing with the decoding device 300 of Figure 16 A to 16C is described below.

Figure 18 be illustrate use of the present invention, being used for will be by the block diagram of the topology example of another embodiment of the decoding device of the LDPC code decoding of the check matrix representative of Figure 15.

In the decoding device 400 of Figure 18, the rib data storage 311 of Figure 16 A and 16B is formed the memory 40 for storage decoding intermediate object program, and it has the capacity less than the capacity of rib data storage 311.

Decoding device 400 comprises: be used for the memory 400, cyclic shift circuits 411 of storage decoding intermediate object program, by 5 calculators 412 ₁To 412 ₅The calculating unit 412 that forms, the memory 413 that is used for storage decoding intermediate object program, cyclic shift circuits 414, by 5 calculators 415 ₁To 415 ₅The calculating unit 415 that forms, be used for the memory 416 and the control assembly 417 that receive.

Below, provide calculator 412 to the calculating unit 412 of Figure 18 with reference to Figure 19 to Figure 22 ₁To 412 ₅ Calculator 415 with calculating unit 415 ₁To 415 ₅, the check node calculation device 101 of Figure 10 and Figure 11 the description of variable node calculator 103 Relations Amongs.

Figure 19 is identical with Figure 11 that variable node calculator 103 is shown with Figure 10 that check node calculation device 101 is shown respectively with Figure 20.Figure 21 shows calculating unit 412 _k(k=1,2 ..., 5) topology example.Figure 22 shows calculating unit 415 _k(k=1,2 ..., 5) topology example.

In the decoding device 400 of Figure 18, calculator 412 _kCarry out some and variable node calculating of check node calculation, and calculating unit 415 _kSome other that carries out that variable node calculates, rather than calculator 412 _kCarry out check node calculation, and calculating unit 415 _kCarrying out variable node calculates.

More particularly, the calculator 412 of Figure 21 _kConsisted of by piece A ' and piece B '.Piece A ' by according to the check node calculation device 101 of Figure 19 be used for carry out the identical mode of the piece A of check node calculation and dispose.Piece B ' is disposed according to the mode identical with piece B, and wherein, piece B is the part of the variable node calculator 103 of Figure 20, is used for from the message u corresponding to all ribs of each row of check matrix _jAggregate-value in deduct message u corresponding to the rib that will determine _jOn the other hand, the calculator 415 of Figure 22 _kConsisted of by piece C '.Piece C ' is disposed according to the mode identical with piece C, and wherein, piece C is another part of the variable node calculator 103 of Figure 20, is used for accumulative total corresponding to the message u of the rib of each row of check matrix _j, and with the reception value u of institute _0iBe added on the aggregate-value.

The calculator 412 of Figure 21 _kWith the result of calculation of piece A and piece B, namely carry out the decoding intermediate object program u of some gained of check node calculation and variable node calculating _j, offer the memory 413 for storage decoding intermediate object program.The calculator 415 of Figure 22 _kThe decoding intermediate object program v that will carry out some other gained of variable node calculating offers for the memory 410 of storing decoding intermediate object program.

Therefore, the decoding device 400 of Figure 18 might be by the calculator 412 that hockets _kCalculating and calculator 415 _kCalculating carry out check node calculation and variable node and calculate, in order to decode.

Calculator 412 at Figure 22 _kIn, owing to the decoding intermediate object program u that from be stored in the decoding intermediate object program v for the memory 413 of storing decoding intermediate object program, deducts corresponding to the rib that will determine _j, wherein, as calculator 415 among the piece B _kBy using the decoding intermediate object program u corresponding to the rib that will determine _jAnd the result of the calculating of carrying out obtains described decoding intermediate object program v, therefore, does not need the FIFO memory 155 of Figure 20.

Next, provide passing through to use a plurality of equatioies by calculator 412 _kThe calculating of carrying out and by calculator 415 _kThe description of the calculating of carrying out.

More particularly, calculating unit 412 carries out first according to above-described formula (7) and the formula (8) that the following describes and calculates, and will be as the first result's who calculates decoding intermediate object program u _jOffer the memory 410 for storage decoding intermediate object program, store thus them.Calculating unit 415 carries out second according to above-mentioned formula (5) and calculates, and will offer as the decoding intermediate object program v of the second result of calculation the memory 410 for storage decoding intermediate object program, stores thus them.

v _i＝v-u _dv......(8)

The u of formula (8) _DvRepresentative wherein, will be determined to described rib the message of the i row of check matrix H from the intermediate object program (, referring to check node calculation result itself here) of the check node calculation of such rib.That is to say u _DvThe decoding intermediate object program corresponding to the rib that will determine.

In particular, the decoding intermediate object program v that obtains as the second result who calculates according to above-mentioned formula (5) is such: with the value u that receives _0iDecoding intermediate object program u with check node calculation _jTake together, wherein, described decoding intermediate object program u _jFrom all ribs of 1 corresponding to every delegation of check matrix H i row.The value v that is used for above-mentioned formula (7) _iBecome such: from the decoding intermediate object program v that obtains as the second result of calculation according to formula (5), deduct the decoding intermediate object program u of check node calculation _jIn the decoding intermediate object program u of check node calculation _Dv, wherein, decoding intermediate object program u _jFrom 1 rib corresponding to every delegation of the i of check matrix H row, and decoding intermediate object program u _DvFrom the rib that will determine its message.That is to say, be used for the value v of calculating of the formula that is identified for (7) _iThe calculating of formula (1) be the calculating that combines above-mentioned formula (5) and formula (8).

Therefore, in decoding device 400, hocket by calculating and by calculating according to second of formula (5) that calculating unit 415 carries out according to first of formula (7) and formula (8) that calculating unit 412 carries out, and, calculating unit 415 is exported the second last result who calculates as decoded result, so that might carry out the repeat decoding of LDPC code.

Here, the intermediate object program u that will be described as decoding according to the first result of calculation of formula (7) and formula (8) _j, and, these decoding intermediate object program u _jThe check node calculation that equals formula (7) is u as a result _j

Owing to obtain like this from the v of the formula (5) of the second calculative determination: from the check node calculation of the rib that will determine its message u as a result _jBe added to the variable node result of calculation v of formula (1) _iOn, therefore, for row (variable node) of check matrix H, only determine a v.

In decoding device 400, calculating unit 412 is by using the decoding intermediate object program v (the second decoding intermediate object program) corresponding to the row of check matrix H to carry out the first calculating, wherein, described decoding intermediate object program v is the second result who calculates who is undertaken by calculating unit 415, and, the decoding intermediate object program u of the check node calculation that obtains as result of calculation _j(the first decoding intermediate object program) is stored in the memory 413 for storage decoding intermediate object program, wherein, and described decoding intermediate object program u _jFrom the rib corresponding to the message (being outputed to the message of each rib by each check-node) of 1 rib of every delegation of the i of check matrix H row.Therefore, the capacity that is used for the memory 413 of storage decoding intermediate object program becomes such value, and it is similar to takes 1 number (total number of rib) and the number of quantization of check matrix together.On the other hand, calculating unit 415 is by using 1 decoding intermediate object program u corresponding to every delegation of the i row of check matrix H _j, and the reception value u of institute _0iCarry out second and calculate, and will be stored in for the memory 410 of storing decoding intermediate object program as the decoding intermediate object program v corresponding to the i row that result of calculation obtains, wherein, described decoding intermediate object program u _jThe first result who calculates who is undertaken by calculating unit 412.Therefore, the memory 410 necessary capacity that are used for storage decoding intermediate object program become such value, this value is that the number of the quantization of the number of the number of verification matrix column and quantization is taken together, wherein, the number of check matrix column is less than 1 number of check matrix, the i.e. code length of LDPC code.

Therefore, in for the decoding device 400 that 1 of check matrix is carried out sparse LDPC code decoding, when comparing with the rib data storage 311 of Figure 16 A and 16B, the memory capacity that is used for the memory 410 of storage decoding intermediate object program can be reduced.Therefore, can reduce the circuit scale of decoding device 400.

In addition, in decoding device 400, because calculating unit 415 carries out calculating according to second of formula (5), therefore decoding device 400 does not need to have the piece (not shown) of the calculating that is used for carrying out formula (5) in the decoding device 300 of Figure 16 A to 16C, wherein, formula (5) is used for calculating final decoded result.Thereby when comparing with the decoding device 300 of Figure 16 A to 16C, the circuit scale of the decoding device of Figure 18 can be reduced.

Now, with the description that at length provides each operation of components of the decoding device 400 of Figure 18.

To offer memory 410 for storage decoding intermediate object program from calculating unit 415 corresponding to 5 decoding intermediate object program D415 of 5 row of check matrix, wherein, these 5 decoding intermediate object programs are second results that calculate that undertaken by calculating unit 415.These 5 decoding intermediate object program D415 that provide from calculating unit 415 are provided since the first address the memory 410 that is used for storage decoding intermediate object program in order.

More particularly, at the place, the first address of the memory 410 that is used for storage decoding intermediate object program, storage is corresponding to the decoding intermediate object program v from the 1st row to the 5th row in the decoding intermediate object program of the row of check matrix.Similarly, at place, the second address, the decoding intermediate object program v of storage from the 6th row to the 10th row, and at place, the 3rd address, the decoding intermediate object program of storage from the 11st row to the 15th row.Subsequently, similarly, the decoding intermediate object program from the 16th row to the 90th row is stored in 18 addresses, the 4th address to the with 5 results' unit, and, 90 decoding intermediate object program v altogether are stored in for the decode memory 410 of intermediate object program of storage.Therefore, the number of word that is used for the memory 410 of storage decoding intermediate object program becomes 18, that is, and and the number of the row of the check matrix H of Figure 15 (code length of LDPC code) 90 numbers 5 divided by the decoding intermediate object program that is read simultaneously and write.

The memory 410 that is used for storage decoding intermediate object program reads the decoding intermediate object program u that determines by the calculating unit 412 of rear class simultaneously from stored decoding intermediate object program D415 _j5 decoding intermediate object program v, and they are offered cyclic shift circuits 411 as decoding intermediate object program D410, wherein, " 1 " in the corresponding row that described 5 decoding intermediate object program v are check matrix H.

The memory 410 that is used for storage decoding intermediate object program is made of the single port RAM that for example can read simultaneously and write 5 decoding intermediate object programs.Because at the decoding intermediate object program v of memory 410 storages that are used for storage decoding intermediate object program corresponding to such row, wherein, the calculating of these row is carried out in the second calculating by calculating unit 415, therefore, be stored in the data volume for the memory 410 of storage decoding intermediate object program, namely, the memory 410 necessary memory capacity that are used for storage decoding intermediate object program are the values that multiply each other of the column number (code length of LDPC code) of the quantization number of decoding intermediate object program and check matrix H.

5 decoding intermediate object program D410 are offered cyclic shift circuits 411 from the memory 410 that is used for storage decoding intermediate object program.In addition, to offer cyclic shift circuits 411 from control assembly 417 corresponding to the control signal D619 of decoding intermediate object program D410, wherein, control signal D619 indication is about the information (matrix data) of such fact, and this fact is: the result as the unit matrix cyclic shift how many times that for example will form the check matrix basis arranges 1 of check matrix.Cyclic shift circuits 611 is about to described 5 cyclic shifts that decoded result D410 rearranges control signal D619 basic enterprising, and the result is offered calculating unit 412 as decoding intermediate object program D411.

Calculating unit 412 comprises 5 calculators 412 ₁To 412 ₅5 decoding intermediate object program D411 (the second decoding intermediate object program) v that will obtain as the second result of calculation of calculating unit 415 offers calculating unit 412 from cyclic shift circuits 411.In addition, will be before as calculator 412 ₁To 412 ₅The first result who calculates who carries out and 5 decoding intermediate object program D413 (the first decoding intermediate object program) u of obtaining _j Offer calculating unit 412 from the memory 413 that is used for storage decoding intermediate object program.Described 5 decoding intermediate object program D411 and 5 decoding intermediate object program D413 are offered calculator 412 ₁To 412 ₅Each.In addition, control signal D419 is offered calculating unit 412 from control assembly 417, and control signal D419 is offered calculator 412 ₁To 412 ₅Control signal D419 is 5 calculators 412 ₁To 412 ₅Total signal.

Calculator 412 ₁To 412 ₅By carrying out calculating according to first of formula (7) and formula (8) with decoding intermediate object program D411 and decoding intermediate object program D413, and the intermediate object program D412 (v that determines to decode _i).Calculating unit 412 will offer corresponding to 5 decoding intermediate object program D412 of 51 of check matrix the memory 413 for storage decoding intermediate object program, wherein, and as calculator 412 ₁To 412 ₅The result of calculation of carrying out and obtain described 5 decoding intermediate object program D412.

The memory 413 that is used for storage decoding intermediate object program is made of two single port RAM that for example can read simultaneously and write 5 decoding intermediate object programs.5 decoding intermediate object program D412 are offered for the memory 413 of storing decoding intermediate object program from calculating unit 412, in addition, will offer memory 413 from control assembly 417 for the control signal D420 that reads and write of control decoding intermediate object program 413.

Based on control signal D420,5 decoding intermediate object program D412 that provide from calculating unit 412 collectively are provided the memory 413 that is used for storage decoding intermediate object program, and read simultaneously stored 5 decoding intermediate object program D412, and, they are offered calculating unit 412 and cyclic shift circuits 414 as decoding intermediate object program D413.That is to say that the memory 413 that is used for storage decoding intermediate object program carries out simultaneously and will be provided for the writing of the decoding intermediate object program D412 that reads and provide from calculating unit 412 of the decoding intermediate object program D413 of calculating unit 412 and cyclic shift circuits 414.

At the memory 413 that is used for storage decoding intermediate object program, storage is by the decoding intermediate object program u of the first check node calculation of calculating of calculating unit 412 _j, wherein, this decoding intermediate object program u _jFrom 1 rib corresponding to every delegation of the i of check matrix H row.Therefore, be stored in the data volume for the memory 413 of storage decoding intermediate object program, that is, be used for the memory 413 necessary memory capacity of storage decoding intermediate object program, become the value that multiplies each other of 1 number of the quantization number of decoding intermediate object program and check matrix.

With 5 decoding intermediate object program D413 (decoding intermediate object program u _j) offer cyclic shift circuits 414 from the memory 413 that is used for storage decoding intermediate object program.In addition, to offer cyclic shift circuits 414 from control assembly 417 corresponding to the control signal D421 of decoding intermediate object program D413, wherein, control signal D421 indication is about the information (matrix data) of such fact, and this fact is: the result as the unit matrix cyclic shift how many times that for example will form the check matrix basis arranges 1 of check matrix.Cyclic shift circuits 414 rearranges the cyclic shift of these 5 decoding intermediate object program D413 on the basis of control signal D421, and the result is offered calculating unit 415 as decoding intermediate object program D414.

Calculating unit 415 comprises 5 calculators 415 ₁To 415 ₅5 decoding intermediate object program D414 are offered calculating unit 415 from cyclic shift circuits 414, and the intermediate object program D414 that will decode offers each calculator 415 ₁To 415 ₅In addition, 5 received data D417 (LDPC code) are offered calculating unit 415 from the memory 417 that is used for receiving, and received data D417 is offered each calculator 415 ₁To 415 ₅In addition, control signal D422 is offered calculating unit 417 from control assembly 417, and control signal D422 is offered calculator 415 ₁To 415 ₅Control signal D422 is 5 calculators 417 ₁To 417 ₅Total signal.

Calculator 415 ₁To 415 ₅Each is by carrying out calculating according to second of formula (5) with decoding intermediate object program D414 and received data D417, and determines decoding intermediate object program D415.Calculating unit 415 will be as calculator 415 ₁To 415 ₅The second result who calculates who carries out and 5 decoding intermediate object program D415 (v) of obtaining offer the memory 410 for storage decoding intermediate object program.In addition, current ongoing calculating be last second calculate in, calculating unit 415 will be exported as final decoded results as 5 decoding intermediate object program D415 that result of calculation obtains.

The memory 416 that is used for receiving will be stored as received data D417 from the reception LLR (log-likelihood ratio) that the reception value (sign bit) that receives by communication channel is calculated, and this receives 0 similarity of LLR is-symbol position.

That is to say that at the place, the 1st address of the memory 416 that is used for receiving, storage is corresponding to being listed as to the received data D417 of the 5th row corresponding to check matrix the 1st among the received data D417 of the row of check matrix.Then, at place, the 2nd address, storage is corresponding to the received data D417 of check matrix the 6th row to the 10th row, and at place, the 3rd address, storage is corresponding to the received data D417 of check matrix the 11st row to the 16th row.Subsequently, similarly, at 18 addresses, the 4th address to the places, with the unit storage of 5 data corresponding to the received data D417 of the 17th row to the 90th row.

Then, the memory 616 that be used for to receive with the unit of 5 data, calculate necessary order according to variable node and read stored received data D417, and they are offered calculating unit 415.

The memory 416 that is used for receiving is made of the single port RAM that for example can read simultaneously and write 5 received data.Being stored in the data volume for the memory 416 that receives, that is, being used for the memory 315 necessary memory capacity that receive, is the value that multiplies each other of number of the quantization of the code length of LDPC code and received data.The number of the word of the memory 416 that be used for to receive is 18, and it is the code length of LDPC code, i.e. the number 90 of the row of check matrix is divided by the value of number 5 gained of the received data D417 that will be read simultaneously.

Control assembly 417 offers cyclic shift memory 411 with control signal D418, and control signal D419 is offered calculating unit 412, in order to control respectively them.Control assembly 417 offers control signal D420 for the memory 413 of storing decoding intermediate object program, control signal D421 is offered cyclic shift circuits 414, and control signal D421 is offered calculating unit 415, in order to control respectively them.

As according to the memory 410 that is used for storage decoding intermediate object program, cyclic shift circuits 411, calculating unit 412, be used for the result of data of sequential loop of memory 413, cyclic shift circuits 414 and the calculating unit 415 of storage decoding intermediate object program, decoding device 400 can once be decoded.In decoding device 400, after decoding was repeated pre-determined number, the result's that will calculate as second of calculating unit 415 decoding intermediate object program D415 was as final decoded result output.

Figure 21 is the calculator 412 that the calculating unit 412 of Figure 18 is shown ₁The block diagram of topology example.

In Figure 21, provide calculator 412 ₁Description, and, calculator 412 ₂To calculator 412 ₅Also disposed in an identical manner.

In Figure 21, by the decoding intermediate object program (u that supposes that previous the first result of calculation of carrying out as calculating unit 412 obtains _Dv) each and sign bit be quantified as together altogether 6 and the second result who calculates of carrying out as calculator 415 and each of the decoding intermediate object program (v) that obtains is quantified as 9, calculator 412 is shown ₁In addition, clock ck is offered the calculator 412 of Figure 21 ₁, and this clock ck offered necessary piece.Then, each piece and clock ck synchronously process.

Based on the control signal D419 that provides from control assembly 417, the calculator 412 of Figure 21 ₁By using the decoding intermediate object program D413 (u that reads successively from the memory 413 that is used for storage decoding intermediate object program _Dv) and the decoding intermediate object program D411 (v) that reads successively from cyclic shift circuits 411, carry out calculating according to first of formula (7) and formula (8), wherein, before obtained described decoding intermediate object program D413 (u as the first result who calculates of calculating unit 412 _Dv).

More particularly, 1 decoding intermediate object program D411 from 59 the decoding intermediate object program D411 (v) that cyclic shift circuits 411 provides is offered calculator 412 ₁56 the decoding intermediate object program D413 (u that will provide from the memory 413 that is used for storage decoding intermediate object program in addition, _j) in 1 decoding intermediate object program D413 from offering calculator 412 ₁, wherein, described 56 decoding intermediate object program D413 (u _j) be the result of calculation of before being undertaken by calculating unit 412, described 1 decoding intermediate object program D413 is the result of the calculating before undertaken by calculating unit 412.With 9 decoding intermediate object program D411 (v) and 6 decoding intermediate object program D413 (u _Dv) offer subtracter D431.In addition, control signal D419 is offered calculator 412 from control assembly 417 ₁, and control signal D419 offered selector 435 and selector 442.

Subtracter 431 deducts 6 decoding intermediate object program D413 (u from 9 decoding intermediate object program D411 (v) _j), and export 6 subtraction value D431.That is to say, the calculating that subtracter 431 carries out according to formula (8), and output is as the subtraction value D431 (v of result of calculation _i).

With the sign bit D432 (sign (v from 6 subtraction value D431 of subtracter 431 outputs _i)) offer EXOR circuit 440, wherein, this sign bit D432 indicates the plus or minus symbol of high-order position, and, with the absolute value D433 of 5 lower-order positions (| v _i|) offer LUT 432.

LUT 432 read to absolute value D433 (| v _i|) carry out in the formula (7)

5 result of calculations of calculating gained

And it is offered adder 433 and FIFO memory 438.

Adder 433 is passed through result of calculation Be stored in that 9 place value D435 in the register 434 are added together to come as a result D434 of cumulative calculation, and 9 aggregate-values that will as a result of obtain are stored in the register 434 again.When added up the absolute value D433 that all decoding intermediate object program D411 of 1 determine on corresponding to check matrix delegation (| v _i|) result of calculation the time, register 433 is reset.

When the decoding intermediate object program D411 on reading successively check matrix delegation and accumulative total were stored in the register 434 for the aggregate-value of the result of calculation D434 gained of delegation, the control signal D419 that provides from control assembly 417 changed into 1 from 0.For example, when row weight when being " 9 ", control signal D419 is " 0 " at the 1st to the 8th clock, and is " 1 " at the 9th clock.

When control signal D419 is " 1 ", the value of selector 435 Selective storages in register 434, that is, accumulative total is definite from decoding intermediate object program D411 (decoding intermediate object program v)

9 place value D435 of gained ( From i=1 to i=d _c), and should value output to register 436 as value D436, store thus it, wherein, described decoding intermediate object program D411 corresponding in the check matrix delegation all 1.Register 436 offers selector 435 and adder 437 with the value D436 that stores as 9 place value D437.When control signal D419 was " 0 ", the value D437 that provides from register 436 was provided for selector 435, and this value is outputed to register 436, came thus again to store it.That is to say that register 436 will before add up

Offer selector 435 and adder 437, until added up from definite corresponding to all decoding intermediate object program D411 of 1 in the check matrix delegation (decoding intermediate object program v) Till.

On the other hand, FIFO memory 438 is with the result of calculation of LUT 432 outputs

Postpone, until from register 436 exported new value D437 (

From i=1 to i=d _c) till, and it is offered subtracter 437 as 5 place value D438.Subtracter 437 deducts the value D438 that provides from FIFO memory 438 from the value D437 that register 436 provides, and subtraction result is offered LUT 439 as 5 subtraction value D439.That is to say that subtracter 437 is from according to corresponding to the definite aggregate-value of all decoding intermediate object program D411 of 1 in the check matrix delegation (decoding intermediate object program v) In, deduct the decoding intermediate object program corresponding to the rib that will determine, that is, definite according to 1 decoding intermediate object program D411 (decoding intermediate object program v) corresponding to predetermined check matrix

And with subtraction value ( From i=1 to i=d _c-1) offers LUT 439 as subtraction value D439.

LUT 439 output to subtraction value D439 (

From i=1 to i=d _c-1) carries out in the formula (7)

Calculate 5 result of calculations of gained

When processing on carry out, EXOR circuit 440 is stored in 1 place value D442 in the register 441 and the XOR of sign bit D432 by calculating, carries out sign bit and multiplies each other, and 1 multiplication result D441 is stored in the register 441 again.The sign bit D432 that determines as all decoding intermediate object program D411 of 1 on corresponding to check matrix delegation is all taken advantage of fashionable, and register 441 is reset.

As the multiply each other multiplication result D441 (∏ sign (v of gained of the sign bit D432 that all decoding intermediate object program D411 of 1 on corresponding to check matrix delegation are determined _i), from i=1 to i=d _c) when being stored in the register 441, the control signal D419 that provides from control assembly 417 changes into " 1 " from " 0 ".

When control signal D419 is " 1 ", the value of selector 442 Selective storages in register 441, that is, and the value D442 (∏ sign (v of the gained that multiplies each other from the sign bit D432 that determines corresponding to all decoding intermediate object program D411 of 1 in the check matrix delegation _i), from i=1 to i=d _c), and should value output to register 443 as 1 place value D443.Register 443 offers selector 442 and EXOR circuit 445 with the value D443 that stores as 1 place value D444.When control signal D419 was " 0 ", the value D444 that provides from register 443 was provided for selector 442, and this value is outputed to register 443, came thus again to store it.That is to say, register 443 offers selector 442 and EXOR circuit 445 with previously stored value, until from all taken advantage of corresponding to the definite sign bit D432 of all decoding intermediate object program D411 of 1 in the check matrix delegation (decoding intermediate object program v) into.

On the other hand, FIFO memory 444 postpones sign bit D432, until newly be worth D444 (∏ sign (v _i), from i=1 to i=d _c) offered EXOR circuit 445 from register 443 till, and it is offered EXOR circuit 445 as 1 place value D445.EXOR circuit 445 is by the XOR of the value D445 that the value D444 that provides from register 443 is provided and provides from FIFO memory 444, and will be worth D444 divided by value D445, and 1 value of being divided by is exported as the value D446 that is divided by.That is to say that EXOR circuit 445 will be from the sign bit D432 (sign (v that determines corresponding to all decoding intermediate object program D411 of 1 in the check matrix delegation _i)) the value that multiplies each other divided by the sign bit D432 (sign (v that determines from 1 decoding intermediate object program D411 corresponding to predetermined check matrix _i)), and the value of will being divided by (∏ sign (v _i), from i=1 to i=d _c-1) as the value D446 output of being divided by.

At calculator 412 ₁In, incite somebody to action altogether 6 conduct decoding intermediate object program D412 (decoding intermediate object program u _j) output, wherein, be 5 lower-order positions from 5 result of calculation D440 of LUT 439 output, and be high-order positions from 1 value D446 that is divided by of EXOR circuit 445 outputs.

As mentioned above, at calculator 412 ₁In, carry out the calculating of formula (7) and formula (8), and determine decoding intermediate object program u _j

Because the capable weight maximum of the check matrix of Figure 15 is 9, that is to say, owing to offer calculator 412 ₁Decoding intermediate object program D411 (v) and decoding intermediate object program D413 (u _Dv) maximum number be 9, therefore, calculator 412 ₁Have: FIFO memory 438 is used for postponing from 99 definite result of calculations of decoding intermediate object program D411

With FIFO memory 444, be used for postponing 9 sign bit D432.When wanting Determining Weights less than the message of 9 row, the retardation in FIFO memory 438 and the FIFO memory 444 is reduced to the weighted value of this row.

Figure 22 is the calculator 415 that calculating unit 415 is shown ₁The block diagram of topology example.

In Figure 22, provide calculator 415 ₁Description, and, calculator 415 ₂To calculator 415 ₅Also disposed in an identical manner.

In Figure 22, each decoding intermediate object program (u that first result of calculation of carrying out as calculator 412 by hypothesis obtains _j) and sign bit be quantified as together altogether 6 calculator 415 be shown ₁In addition, clock ck is offered the calculator 4151 of Figure 22, and, this clock ck is offered necessary piece.Each piece and clock ck synchronously process.

Based on the control signal D422 that provides from control assembly 417, the calculator 415 of Figure 22 ₁By using received data D417 (the reception value u of institute that reads successively from the memory 416 that is used for receiving _0i) and the decoding intermediate object program D414 (u that reads successively from cyclic shift circuits 414 _j), carry out calculating according to second of formula (5).

More particularly, at calculator 415 ₁In, read successively 16 decoding intermediate object program D414 (decoding intermediate object program u corresponding to the every delegation of check matrix from cyclic shift circuits 414 _j), and the intermediate object program D414 that will decode offers adder 417.In addition, at calculator 415 ₁In, read successively 6 received data D417 from the memory 416 that is used for receiving, and provide it to adder 475.In addition, control signal D422 is offered calculator 415 from control assembly 417 ₁, and control signal D422 offered selector 473.

Adder 471 is by the intermediate object program D414 that will decode (decoding intermediate object program u _j) and 9 aggregate-value D471 that are stored in the register 472 added together, come the accumulative total intermediate object program D414 that decodes, and 9 aggregate-values be stored in the register 472 again.During all decoding intermediate object program D414 of 1, register 472 is reset on having added up corresponding to check matrix delegation.

When the value of decoding intermediate object program D414 gained of the decoding intermediate object program D414 that reads successively check matrix delegation and accumulative total delegation was stored in the register 472, the control signal D422 that provides from control assembly 417 changed into " 1 " from " 0 ".For example, when the weight of row when being " 5 ", control signal D422 is " 0 " at the 1st clock to the 4 clocks, and is " 1 " at the 5th clock.

When control signal D422 is " 1 ", the value of selector 473 Selective storages in register 472, that is, accumulative total is from decoding intermediate object program D414 (the decoding intermediate object program u of all ribs in the check matrix delegation _j) 9 place value 471 (∑ u of gained _j, from j=1 to i=d _v), and this value outputed to register 474, store thus it.Register 474 offers selector 471 and adder 475 with the value D471 that stores as 9 place value D472.When control signal D422 was " 0 ", the value D472 that provides from register 474 was provided for selector 473, and this value is outputed to register 474, came thus again to store it.That is to say that the value that register 474 will before add up offers selector 473 and adder 475, until added up decoding intermediate object program D414 (the decoding intermediate object program u from all ribs in the check matrix delegation _j) till.

6 received data D417 that adder 475 provides with 9 place value D472 with from the memory 416 that be used for to receive are added together, and thus obtained 6 place values are exported as decoding intermediate object program D415 (decoding intermediate object program v).

As mentioned above, at calculator 415 ₁In, carry out the calculating of formula (5), and determine decoding intermediate object program v.

Because the maximum of the row weight of the check matrix of Fig. 8 is 5, that is to say, owing to offer calculator 415 ₁Decoding intermediate object program u _jMaximum number be 5, so calculator 415 ₁With 56 decoding intermediate object program u _jMaximum added together.So, calculator 415 ₁Output be 9 place values.

Figure 23 is the block diagram of topology example that the memory 413 that is used for storage decoding intermediate object program of Figure 18 is shown.

The memory 413 that is used for storage decoding intermediate object program comprises switch 501 and 504 and two RAM 502 and 503 that are used for storage decoding intermediate object program, and wherein, described RAM is single port RAM.

Before each parts of describing the memory 413 that is used for storage decoding intermediate object program in detail, will describe that at first data are stored in for the RAM 502 of storage decoding intermediate object program and 503 method.

Be used for the RAM 502 of storage decoding intermediate object program and the decoding intermediate object program D412 that 503 storages provide by switch 501, wherein, obtain described decoding intermediate object program D412 as the first result who calculates.

More particularly, place, 9 addresses, the 1st address to the at the RAM 502 that is used for storage decoding intermediate object program, according to for every delegation, in the horizontal direction (on column direction) check matrix H of Figure 15 is got more closely such mode (according to the mode of ignoring 0) from the 1st 1 filling of walking to the 5th row, storage is corresponding to their decoding intermediate object program D412 (D501).

More particularly, when the capable i tabulation of j is shown (j, i) time, place, the 1st address at the RAM 502 that is used for storage decoding intermediate object program, storage is corresponding to 1 data of 5 * 5 unit matrixs of from (1,1) to (5,5), wherein, described 5 * 5 unit matrixs submatrix that is check matrixes of Figure 15.At the 2nd address place, storage is corresponding to 1 data of the shift matrix from (1,21) to (5,25) (5 * 5 unit matrixs by to the right the shift matrix of loopy moving 3), and wherein, described shift matrix is the submatrix of the check matrix of Figure 15.Similarly, at the 3rd to the 8th address place, store equally by this way data, so as corresponding to the check matrix of Figure 15 matrix.Then, locate in the 9th address, storage corresponding to from the shift matrix of (1,86) to (5,90) of check matrix (with 0 replaced 5 * 5 unit matrixs the first row 1, and with this unit matrix shift matrix of loopy moving 1 left) 1 data.Here, in the shift matrix of check matrix from (1,86) to (5,90) of Figure 15, owing in the 1st row, do not have 1, therefore do not store data at place, the 9th address.

At the place, 18 addresses, the 10th address to the of the RAM 502 that is used for storage decoding intermediate object program, storage corresponding to the check matrix of Figure 15 from the 11st 1 the data that walk to the 15th row.That is to say that at the 10th address place, storage is corresponding to 1 data of such matrix, in this matrix, with 5 * 5 unit matrixs of check matrix from (11,6) to (15,10) loopy moving 3 to the right.Locate in the 11st address, storage is corresponding to forming check matrix from (11,11) to (15,15) and matrix (should and matrix be 5 * 5 unit matrixs with 5 * 5 unit matrixs by the shift matrix of loopy moving 3 to the right with) 1 data of shift matrix.At the 12nd address place, storage forms 1 the data of check matrix from (11,6) to (15,10) and unit matrix matrix.Subsequently, same, at place, 18 addresses, the 13rd address to the, store by this way data, so that corresponding to check matrix.

More particularly, be 2 or larger submatrix for weight, when with the two or more of following matrix and form when representing submatrix, be the data (corresponding to the decoding intermediate object program of the message of the rib that belongs to unit matrix, accurate unit matrix or shift matrix) of 1 position of 1 unit matrix, accurate unit matrix or shift matrix corresponding to weight in identical address place storage, wherein, described matrix is: weight is the 1 (unit matrix of P * P); Accurate unit matrix has wherein replaced as one or more 1 of the element of unit matrix with 0; And shift matrix, wherein unit matrix or accurate unit matrix are recycled displacement.

Similarly, at the place, 27 addresses, the 19th address to the of the RAM 502 that is used for storage decoding intermediate object program, store by this way corresponding to from the 21st 1 the data that walk to the 25th row, so that corresponding to the check matrix of Figure 15.That is to say that the number of word that is used for the RAM502 of storage decoding intermediate object program is 27.

Place, 9 addresses, the 1st address to the at the RAM 503 that is used for storage decoding intermediate object program, according to for every delegation, in the horizontal direction (on column direction) check matrix H of Figure 15 is got more closely such mode (wherein ignoring 0 mode) from the 6th 1 filling of walking to the 10th row, storage is corresponding to their decoding intermediate object program D412 (D502).

In particular, place, the 1st address at the RAM 503 that is used for storage decoding intermediate object program, storage is corresponding to forming from (6,1) to (10,5) and matrix (should and matrix be the first shift matrix and the second shift matrix and, in the first shift matrix, 5 * 5 unit matrixs are by loopy moving 1 to the right, and in the second shift matrix, described unit matrix is by loopy moving 2 to the right) 1 data of the first shift matrix, wherein, described the first shift matrix submatrix that is check matrix.At the 2nd address place, storage is corresponding to 1 the data that form from (6,1) to (10,5) and the second shift matrix matrix, and wherein, described the second shift matrix is the submatrix of check matrix.Subsequently, same, at place, 9 addresses, the 3rd address to the, store by this way data, so that corresponding to the submatrix of check matrix.

Similarly, at the place, the 10th to the 18th address of the RAM 503 that is used for storage decoding intermediate object program, store by this way corresponding to the check matrix of Figure 15 from the 16th 1 the data that walk to the 20th row, so that corresponding to the check matrix of Figure 15.At 27 addresses, the 19th address to the places, store by this way corresponding to the check matrix of Figure 15 from the 26th 1 the data that walk to the 30th row, so that corresponding to the check matrix of Figure 15.That is to say that the number of word that is used for the RAM 503 of storage decoding intermediate object program is 27.

In the manner described above, being used for the RAM 502 of storage decoding intermediate object program and the number of 503 word is 27.That is to say, the number of word becomes such value: the capable weight 9 of check matrix be multiply by capable number 30, with the number 5 of multiplied result (check matrix 1 number) divided by the decoding intermediate object program D501 that is read simultaneously, and further with the number 2 of result divided by the RAM 502 that is used for storage decoding intermediate object program, wherein, the memory 413 for storage decoding intermediate object program has described decoding intermediate object program.

Now, with the description that provides in detail the operation of each parts of the memory 413 that is used for storage decoding intermediate object program of Figure 23.

When calculating unit 412 carries out the first calculating, will be as the decoding intermediate object program D412 (u of the first result of calculation acquisition _j) offer for the memory 413 of storing decoding intermediate object program from calculating unit 412, and, write decoding intermediate object program D412 for the RAM 502 of storage decoding intermediate object program and be used for the presumptive address place of one of RAM 503 of storage decoding intermediate object program.Simultaneously, read the decoding intermediate object program D412 (u that obtains as the first result who calculates who had before been undertaken by calculating unit 412 from other RAM _j), and it is outputed to calculating unit 412.On the other hand, when calculating unit 415 carries out the second calculating, do not carry out to being used for storing the decode RAM 502 of intermediate object program or writing for the RAM 503 that stores decoding intermediate object program for the memory 413 of storing the intermediate object program of decoding, its presumptive address from one of described RAM reads decoding intermediate object program, and they are offered cyclic shift circuits 414.

5 decoding intermediate object program D412 are offered switch 501 from calculating unit 412, in addition, with control signal D420 ₁Offer switch 501 from control assembly 417, wherein, control signal D420 ₁Indication is selected to be used for the RAM 502 of storage decoding intermediate object program and is used for one of RAM 503 of storage decoding intermediate object program, as the memory that is used for storage decoding intermediate object program D412.Based on control signal D420 ₁, switch 501 is selected to be used for the RAM 502 of storage decoding intermediate object program and is used for one of RAM 503 of storage decoding intermediate object program, and 5 decoding intermediate object program D412 are offered selected RAM.

5 decoding intermediate object program D412 are offered for the RAM 502 that stores decoding intermediate object program from switch 501 as decoding intermediate object program D501, in addition, will indicate the control signal D420 of address ₂Offer RAM 502 from control assembly 417.The RAM 502 that is used for storage decoding intermediate object program reads and is stored in by control signal D402 ₂5 decoding intermediate object program D501 at the address place of indication, and they are offered switch 504 as decoding intermediate object program D503 wherein, obtain described 5 decoding intermediate object program D501 as the first result who calculates who had before been undertaken by calculating unit 412.In addition, be used for 5 decoding intermediate object program D501 storages (writing) that the RAM 502 of storage decoding intermediate object program will provide from switch 501 to by control signal D402 ₂The place, address of indication.

5 decoding intermediate object program D412 are offered for the RAM 503 that stores decoding intermediate object program from switch 501 as decoding intermediate object program D502, in addition, will indicate the control signal D420 of address ₃Offer RAM 503 from control assembly 417.The RAM 503 that is used for storage decoding intermediate object program reads and is stored in by control signal D420 ₃5 decoding intermediate object program D502 at the address place of indication, and they are offered switch 504 as decoding intermediate object program D504 wherein, obtain described 5 decoding intermediate object program D502 as the first result who calculates who had before been undertaken by calculating unit 412.In addition, be used for 5 decoding intermediate object program D502 storages (writing) that the RAM 502 of storage decoding intermediate object program will provide from switch 501 to by control signal D420 ₃The place, address of indication.

Decoding intermediate object program D503 is offered switch 504 from the RAM 502 that is used for storage decoding intermediate object program, and the intermediate object program D504 that perhaps will decode offers switch 504 from the RAM 503 that is used for storage decoding intermediate object program.In addition, with control signal D420 ₄Offer switch 504 from control assembly 417, wherein, control signal D420 ₄Indication is selected to be used for the RAM 502 of storage decoding intermediate object program and is used for one of RAM 503 of storage decoding intermediate object program.Based on control signal D420 ₁Switch 504 is selected to be used for the RAM 502 of storage decoding intermediate object program and is used for one of RAM 503 of storage decoding intermediate object program, and will offer calculating unit 412 and cyclic shift circuits 414 as 5 decoding intermediate object program D413 from 5 decoding intermediate object programs that selected RAM provides.

Figure 24 is the sequential chart with write operation of reading of the RAM 502 that is used for storage decoding intermediate object program of the diagram memory 413 that is used for storage decoding intermediate object program and the RAM 503 that is used for storage decoding intermediate object program.

In Figure 24, trunnion axis represents the time (t).

At the memory 413 that is used for storage decoding intermediate object program, when calculating unit 412 will carry out the first calculating, based on control signal D420 ₂Be used for the RAM 502 of storage decoding intermediate object program with 5 results' unit, from the decoding intermediate object program D501 that has stored, will be stored in identical address, read 9 times from the 1st 1 the decoding intermediate object program D501 that walks to the 5th row corresponding to check matrix, and by switch 504 they are offered calculating unit 412, wherein, obtain described decoding intermediate object program D501 as the first result who calculates who had before been undertaken by calculating unit 412.That is to say, because the capable weight of the check matrix of Figure 15 is 9, therefore there are 9 corresponding to 1 decoding intermediate object program of every delegation of check matrix H, and, be used for the RAM 502 of storage decoding intermediate object program with 5 results' unit, will be corresponding to reading 9 times from the 1st 15 the decoding intermediate object program D501 that walk to the 5th row.

Next, based on control signal D420 ₃Be used for the RAM 503 of storage decoding intermediate object program with 5 results' unit, from the decoding intermediate object program D502 that has stored will be stored in identical address, corresponding to reading continuously 9 times from the 6th 1 the decoding intermediate object program D502 that walks to the 10th row, and by switch 504 they are offered calculating unit 412, wherein, obtain described decoding intermediate object program D502 as the first result who calculates who had before been undertaken by calculating unit 412.Simultaneously, will be corresponding to the 1st of check matrix walks to 5 of the 5th row decoding intermediate object program D412 as decoding intermediate object program D501 offer RAM 502 for storage decoding intermediate object program by switch 501, wherein, obtain described 5 decoding intermediate object program D412 as current the first result who calculates who is just being undertaken by calculating unit 412.Based on control signal D420 ₂, the intermediate object program D501 that will decode of the place, address of the decoding intermediate object program D503 that the RAM 502 that is used for storage decoding intermediate object program has read in storage stores 9 times.

Subsequently, based on control signal D420 ₂Be used for the RAM 502 of storage decoding intermediate object program with 5 results' unit, from the decoding intermediate object program D501 that has stored, will be stored in identical address, reading 9 times from the 11st 1 the decoding intermediate object program D501 that walks to the 15th row corresponding to check matrix, and by switch 504 they are offered calculating unit 412, wherein, obtain described decoding intermediate object program D501 as the first result who calculates who had before been undertaken by calculating unit 412.Simultaneously, will be corresponding to check matrix offer RAM 503 for storage decoding intermediate object program as decoding intermediate object program D502 by switch 501 from the 6th 15 decoding intermediate object program D412 that walk to the 10th row, wherein, obtain described 5 decoding intermediate object program D412 as current the first result who calculates who is just being undertaken by calculating unit 412.Based on control signal D420 ₃, will decode intermediate object program D502 Coutinuous store 9 times of the place, address of the decoding intermediate object program D504 that the RAM 503 that is used for storage decoding intermediate object program has read in storage.

Subsequently, similarly, read or write take 9 times as unit hockets for the RAM 502 of storage decoding intermediate object program with for the RAM 503 that stores the intermediate object program of decoding, until will be stored in corresponding to all decoding intermediate object programs of 1 of check matrix for the RAM 502 of storage decoding intermediate object program or for the RAM 503 that stores decoding intermediate object program, wherein, the first result who calculates who carries out as calculating unit 412 and obtain described decoding intermediate object program.

At the memory 413 that is used for storage decoding intermediate object program, when calculating unit 415 carries out the second calculating, based on control signal D420 ₂, read the decoding intermediate object program D503 that has stored, obtain as the first result of calculation from the RAM 502 that is used for storage decoding intermediate object program, perhaps based on control signal D420 ₃, read the decoding intermediate object program D504 that has stored, obtain as the first result of calculation from the RAM 503 that is used for storage decoding intermediate object program, and the decoding intermediate object program that will read offers cyclic shift circuits 414 by switch 504.

Figure 25 is the flow chart of decode procedure of the decoding device 400 of diagram Figure 18.For example, when the data that will decode that receive are stored in for the memory 416 that receives, begin this process.

In step S50, cyclic shift circuits 414 413 that provide from the memory that is used for storage decoding intermediate object program, will be in 5 decoding intermediate object program D413 cyclic shifts of step S56 (will describe afterwards) storage, and they are offered calculating unit 415.

More particularly, 5 decoding intermediate object program D413 are offered cyclic shift circuits 414 from the memory 413 that is used for storage decoding intermediate object program, in addition, to offer cyclic shift circuits 414 from control assembly 417 corresponding to the control signal D421 of decoding intermediate object program D413, wherein, control signal D421 indication is about the information (matrix data) of such fact, and this fact is: the result as the unit matrix cyclic shift how many times that for example will form the check matrix basis arranges 1 of check matrix.Based on control signal D421, cyclic shift circuits 414 is these 5 decoding intermediate object program D413 cyclic shifts (rearranging), and the result is offered calculating unit 415 as decoding intermediate object program D414.

When not yet carrying out first and calculate and decoding intermediate object program D413 when not being stored in memory 413 for storage decoding intermediate object program offering received data D417 for the memory 416 that receives, the calculating unit 415 intermediate object program u that will decode _jBe set to initial value.

In step S51, calculating unit 415 carries out second and calculates, and will offer as the decoding intermediate object program D415 of result of calculation the memory 410 for storage decoding intermediate object program.

More particularly, in step S50,5 decoding intermediate object program D414 are offered calculating unit 415 from cyclic shift circuits 414, in addition, 5 received data D417 are offered calculating unit 415 from the memory 416 that is used for received data.Decode intermediate object program D415 and received data D417 are offered separately the calculator 415 of calculating unit 415 ₁To 415 ₅Each.In addition, control signal D422 is offered calculating unit 415 from control assembly 417, and control signal D422 is offered calculator 415 ₁To 415 ₅

Based on control signal D422, calculator 415 ₁To 415 ₅Each is by carrying out the calculating according to formula (5) with decoding intermediate object program D414 and received data D417, and will obtain as result of calculation, offer for the decode memory 410 of intermediate object program of storage corresponding to the decoding intermediate object program D415 (v) of the row of check matrix.

After the processing of step S51, this process proceeds to step S52, and at this step place, the memory 410 that is used for storage decoding intermediate object program will be stored in identical address from the decoding intermediate object program D415 that calculating unit 415 provides at step S51, then, this process proceeds to step S53.

At step S53, control assembly 417 determines whether calculating unit 415 has calculated all the decoding intermediate object program D415 corresponding to the row of check matrix.When determining not calculate all decoding intermediate object program D415, this process is returned step S50, and again carries out above-mentioned processing.

On the other hand, when determining that at step S53 control assembly 417 calculating units 415 have calculated all decoding intermediate object program D415 corresponding to the row of check matrix, this process proceeds to step S54, at this step place, decoding intermediate object program D410 (v) cyclic shift that cyclic shift circuits 411 will provide from the memory 410 that is used for storage decoding intermediate object program.

More particularly, 5 decoding intermediate object program D410 are offered cyclic shift circuits 411 from the memory 410 that is used for storage decoding intermediate object program.In addition, to offer cyclic shift circuits 411 from control assembly 417 corresponding to the control signal D418 of decoding intermediate object program D410, wherein, control signal D418 indication is about the information (matrix data) of such fact, and this fact is: the result as the unit matrix cyclic shift how many times that for example will form the check matrix basis arranges 1 of check matrix.Based on control signal D418, cyclic shift circuits 411 is 5 decoding intermediate object program D410 cyclic shifts (rearranging), and they are offered calculating unit 412 as decoding intermediate object program D411.

After the processing of step S54, this process proceeds to step S55, and at this step place, calculating unit 412 carries out first and calculates, and will offer cyclic shift circuits 414 as the decoding intermediate object program D412 of result of calculation.

More particularly, at step S54,5 decoding intermediate object program D411 (v) are offered calculating unit 412 from cyclic shift circuits 411.5 decoding intermediate object program D412 (D413) (u that will store at step S56 (will describe afterwards) in addition, _j) offer calculating unit 412, wherein, obtain these 5 decoding intermediate object program D412 (D413) (u as the first result who calculates who had before been undertaken by calculating unit 412 _j).Decoding intermediate object program D411 and decoding intermediate object program D413 are offered separately the calculator 412 of calculating unit 412 ₁To 412 ₅Each.In addition, control signal D419 is offered calculating unit 412 from control assembly 417, and control signal D419 is offered calculator 412 ₁To 412 ₅

Based on control signal D419, calculator 412 ₁To 412 ₅Each is by carrying out the calculating according to formula (7) and formula (8) with decoding intermediate object program D411 and decoding intermediate object program D413, and the decoding intermediate object program D412 (u that will obtain as result of calculation _j) offer for the memory 413 of storing decoding intermediate object program.

After the processing of step S55, this process proceeds to step S56, and at this step place, the memory 413 that is used for storage decoding intermediate object program will be stored in identical address from 5 decoding intermediate object program D412 that calculating unit 412 provides at step S55, then, this process proceeds to step S57.

At step S57, control assembly 417 determines whether calculating unit 412 has calculated all 1 the decoding intermediate object program D412 corresponding to check matrix.When determine not have the calculation check matrix all 1 the time, this process is returned step S54, and again carries out above-mentioned processing.

On the other hand, when when step S57 control assembly 417 determines that calculating unit 412 has calculated corresponding to all decoding intermediate object program D412 of 1, this process is finished.

Decoding device 400 repeats described decoding number with the decode procedure of Figure 25, and the message D415 that will obtain as the second last result who calculates is as final decoded result output.

In the superincumbent description, consisted of by two single port RAM although be used for the memory 413 of storage decoding intermediate object program,, if reading and write of a RAM do not occured simultaneously, then memory 413 can be made of three or more RAM.When the physical bit width of RAM is inadequate, by providing identical control signal with a plurality of RAM, these RAM logically can be assumed to be a RAM.

For the part that lacks rib data (corresponding to the message of rib), during in memory, storing (when data being stored in for the memory 410 of storing decoding intermediate object program and 413), storing message not, and in the computing interval (in first computing interval at calculating unit 412 places with in second computing interval at calculating unit 415 places), do not calculate.

Figure 26 be illustrate use of the present invention, being used for will be by the block diagram of the topology example of another embodiment of the decoding device of the LDPC code decoding of the check matrix representative of Figure 15.

In the decoding device 600 of Figure 26, the rib data storage 316 of Figure 16 A to 16C is formed the memory 613 for storage decoding intermediate object program, and it has the capacity less than the capacity of rib data storage 316.

Decoding device 600 comprises: be used for the memory 610, cyclic shift circuits 611 of storage decoding intermediate object program, by 5 calculators 612 ₁To 612 ₅The calculating unit 612 that forms, the memory 613 that is used for storage decoding intermediate object program, cyclic shift circuits 614, by 5 calculators 615 ₁To 615 ₅The calculating unit 615 that forms, be used for the memory 616 and the control assembly 617 that receive.

With reference to Figure 27 to Figure 30, provide the calculator 612 to the calculating unit 612 of Figure 26 ₁To calculator 612 ₅, Figure 30 the calculator 615 of calculating unit 615 ₁To calculator 615 ₅, the check node calculation device 101 of Figure 10 and Figure 11 the description of variable node calculator 103 Relations Amongs.

Figure 27 is identical with above-mentioned Figure 11 that variable node calculator 103 is shown with above-mentioned Figure 10 that check node calculation device 101 is shown respectively with Figure 28.Figure 29 shows calculator 612 _k(k=1,2 ..., 5) topology example.Figure 30 shows calculator 615 _k(k=1,2 ..., 5) topology example.

In the decoding device 600 of Figure 26, calculator 612 _kCarry out some of check node calculation and calculator 615 _kCarry out some that some other and variable node of check node calculation calculate, rather than calculator 612 _kCarry out check node calculation and calculating unit 615 _kCarrying out variable node calculates.

More particularly, the calculator 612 of Figure 29 _kConsisted of by piece D ' and piece E '.Piece D ' is disposed according to the mode identical with piece D, and wherein, piece D is used for accumulative total to the message v corresponding with all ribs of each row of check matrix _iAbsolute value carry out Calculate the value of gained, piece D is the part of the check node calculation device 101 of Figure 27.Piece E ' is disposed according to the mode identical with piece E, and wherein, piece E is used for will be corresponding to the message v of all ribs of each row of check matrix _iSign bit multiply each other.

On the other hand, the calculator 615 of Figure 30 _kConsisted of by piece F ', G ' and H '.Piece F ' is disposed according to the mode identical with piece F, and wherein, piece F is used for: will each be listed as the message v of all ribs corresponding to check matrix _iThe value that multiplies each other of sign bit divided by the message v corresponding to the rib that will determine _iSign bit; And, by to each is listed as the corresponding message v of all ribs with check matrix _iAbsolute value calculate

In the aggregate-value of the value of gained, deduct the message v corresponding with the rib that will determine _iAbsolute value carry out

Calculate the value of gained, the value that obtains is carried out Calculate, piece F ' is another part of the check node calculation device 101 of Figure 19.Piece G ' by according to be used for message v _iAbsolute value carry out

The identical mode of piece G of calculating disposes.Piece H ' is disposed by the identical mode of the piece H that calculates according to the variable node with the variable node calculator 103 that is used for carrying out Figure 20.

The calculator 612 of Figure 29 _kWith the result of calculation of piece A and piece B, that is, the decoding intermediate object program w that carries out some gained of check node calculation offers for the memory 613 of storing decoding intermediate object program.The calculator 615 of Figure 30 _kSome other and the variable node that will carry out check node calculation calculate the decoding intermediate object program v of gained _i' offer for the memory 610 of storing decoding intermediate object program.

Therefore, the decoding device 600 of Figure 26 might be by the calculator 612 that hockets _kCalculating and calculator 615 _kCalculating carry out check node calculation and variable node and calculate, in order to decode.

Calculator 615 at Figure 30 _kIn, by use be stored in for the memory 610 of storage decoding intermediate object program, corresponding to the decoding intermediate object program v of the rib that will determine _i', piece C is from as calculator 612 _kThe absolute value of the decoding intermediate object program w that obtains of result of calculation in, deduct the decoding intermediate object program v corresponding to the rib that will determine _i', and the sign bit of the intermediate object program w that will decode multiply by the decoding intermediate object program v corresponding to the rib that will determine _i' sign bit.Therefore, the memory 127 and the FIFO memory 133 that do not need Figure 27.

Next, by using equation, provide the calculator 612 to calculating unit 612 ₁To calculator 612 ₅The calculator 615 of the calculating of carrying out and calculating unit 615 ₁To calculator 615 ₅The description of the calculating of carrying out.

Calculating unit 612 carries out calculating according to first of formula (9), and will offer as the first result's who calculates decoding intermediate object program w the memory 613 for storage decoding intermediate object program, stores thus them.Calculating unit 615 carries out above-mentioned formula (1) and calculates according to second of formula (9) and formula (11), and will be as the second result's who calculates decoding intermediate object program v _i' offer the memory 610 for storage decoding intermediate object program, store thus them.

$w=\underset{i=1}{\overset{d_c}{\mathrm{\Σ}}}\left|{v_i}^{\′}\right|\×\underset{i=1}{\overset{d_c}{\mathrm{\Π}}}\mathrm{sign}\left({v_i}^{\′}\right)---\left(9\right)$

u _j＝Ф ^-1(|w|-|v _i|)×sign(v _i′)×sign(w) (10)

v _i′＝Ф(|v _i|)×sign(v _i) (11)

More particularly, the decoding intermediate object program w that obtains as the first result of calculation according to formula (9) is such: with the decoding intermediate object program v of check node calculation _i' absolute value | v _i' | summation and sign bit (v _i') take together, wherein, obtain described decoding intermediate object program v as the second result of calculation according to formula (1), formula (10) and formula (11) _i', and it is corresponding to capable all of the j of check matrix H 1.Therefore, shown in (10), the u that can obtain by the check node calculation that represents through type (7) with such value _j: from the absolute value of conduct according to the decoding intermediate object program w of the first result of calculation acquisition of formula (9) | the w|, deduct (a plurality of) decoding intermediate object program v corresponding to " 1 " (rib) of each capable row of the j of check matrix H _i' in, corresponding to the decoding intermediate object program v of the rib that will determine _i' absolute value | v _i' |.

In decoding device 600, hocket and calculate and calculate according to second of formula (1), formula (10) and formula (11) according to first of formula (9) by what calculating unit 612 carried out, and, calculating unit 615 is by using the first last result of calculation to carry out calculating according to first of formula (5), and result of calculation exported as decoded result, carry out thus the iterative decoding of LDPC code.

More particularly, in decoding device 600, calculating unit 612 is by using corresponding to capable all 1 the decoding intermediate object program v of check matrix H j _i' carry out first and calculate, and will obtain as result of calculation, be stored in for the decode memory 613 of intermediate object program of storage corresponding to the decoding intermediate object program w of the every delegation of check matrix, wherein, described decoding intermediate object program v _i' be the second result who calculates that calculating unit 615 carries out.Therefore, the capacity that is used for the memory 613 of storage decoding intermediate object program becomes takes the together value of gained with the line number order of check matrix and the quantization number of decoding intermediate object program w, wherein, the line number order of described check matrix is less than the number of " 1 " of check matrix.Calculating unit 615 is by using the first result's who calculates who carries out as calculating unit 612 decoding intermediate object program w and the reception value u of institute _0i, carry out second and calculate, and the decoding intermediate object program v of the check node calculation that will obtain as result of calculation _i' be stored in the memory 610 for storage decoding intermediate object program, wherein, described decoding intermediate object program w is corresponding to every delegation of the i row of check matrix H, the intermediate object program of decoding v _i' corresponding to 1 (rib) of check matrix i row.Therefore, the memory 610 necessary capacity that are used for storage decoding intermediate object program become the value that obtains like this: be similar to the rib data storage 311 that is used for storage variable node result of calculation of Figure 16 A and 16B, with 1 number and decoding intermediate object program v of check matrix _i' the quantization number take together.

Therefore, in coding/decoding method 600, when comparing with the rib data storage 311 of Figure 16 A and 16B, the memory capacity that is used for the memory 610 of storage decoding intermediate object program can be reduced.This is so that might reduce the circuit scale of decoding device 600.

The below will describe the operation of each parts of the decoding device 600 of Figure 26 in detail.

Based on control signal D618,5 decoding intermediate object program D615 that provide from calculating unit 615 collectively are provided the memory 610 that is used for storage decoding intermediate object program, simultaneously, read 5 stored decoding intermediate object program D615, and they are offered cyclic shift circuits 611 and calculating unit 615 as decoding intermediate object program D610.That is to say that the writing of the decoding intermediate object program D615 that reads and provide from calculating unit 615 of the decoding intermediate object program D610 of cyclic shift circuits 611 is provided the memory 610 that is used for storage decoding intermediate object program simultaneously.

At the memory 610 that is used for storage decoding intermediate object program, store by calculating unit 615 by the second decoding intermediate object program v that calculates _i' (the second decoding intermediate object program), it is corresponding to 1 (rib) of check matrix.Therefore, be stored in the data volume for the memory 610 of storage decoding intermediate object program, that is, be used for the required memory capacity of memory 610 of storage decoding intermediate object program, become the value that multiplies each other of quantization number and 1 the number (sum of rib) of decoding intermediate object program.

For example, the memory 610 for storage decoding intermediate object program comprises two single port RAM that can read simultaneously and write 5 decoding intermediate object programs.5 decoding intermediate object program D615 are offered for the memory 610 of storing decoding intermediate object program from calculating unit 615, in addition, will offer memory 610 from control assembly 617 for the control signal D618 that reads and write of control decoding intermediate object program D615.

5 decoding intermediate object program D610 are offered cyclic shift circuits 611 from the memory 610 that is used for storage decoding intermediate object program.In addition, to offer cyclic shift circuits 611 from control assembly 617 corresponding to the control signal D619 of decoding intermediate object program D610, wherein, control signal D619 indicates the information (matrix data) about such fact: the result as the unit matrix cyclic shift how many times that for example will form the check matrix basis arranges 1 of check matrix.Based on control signal D619, cyclic shift circuits 611 rearranges the cyclic shift of 5 decoded result D610, and the result is offered calculating unit 612 as decoding intermediate object program D611.

Calculating unit 612 comprises 5 calculators 612 ₁With 612 ₅With 5 decoding intermediate object program D611 (the second decoding intermediate object program) (v _i') offer calculating unit 612 from cyclic shift circuits 611, and 5 decoding intermediate object programs 611 (first decoding intermediate object program) (w) are offered respectively calculator 612 ₁To 612 ₅Control signal D620 is offered calculating unit 612 from control assembly 617, and control signal D620 is offered calculator 612 ₁To 612 ₅Control signal D620 is 5 calculators 612 ₁To 612 ₅Total signal.

Calculator 612 ₁To 612 ₅Each carries out the first calculating by using decoding intermediate object program D611 according to formula (9), in order to determine decoding intermediate object program D612 (w).Calculating unit 612 will be as calculator 612 ₁To 612 ₅The result of calculation of carrying out and obtain 5 decoding intermediate object program D612 offer the memory 613 for storage decoding intermediate object program.

To offer memory 613 for storage decoding intermediate object program from calculating unit 612 corresponding to 5 decoding intermediate object program D612 of the row of check matrix, wherein, described 5 decoding intermediate object program D612 are first results that calculate that calculating unit 612 carries out.These 5 decoding intermediate object program D612 that provide from calculating unit 612 are provided since the first address the memory 613 that is used for storage decoding intermediate object program in order.

More particularly, at the place, the 1st address of the memory 613 that is used for storage decoding intermediate object program, storage corresponding in the decoding intermediate object program of the row of check matrix from the 1st decoding intermediate object program w that walks to the 5th row.Similarly, at the 2nd address place, storage is from the 6th decoding intermediate object program that walks to the 10th row, and at place, the 3rd address, and storage is from the 11st decoding intermediate object program w that walks to the 15th row.Subsequently, similarly, with 5 results' unit in the storage of place, 6 addresses, the 4th address to the from the 16th decoding intermediate object program w that walks to the 30th row, and, 60 decoding intermediate object program w altogether are stored in memory 613 for storage decoding intermediate object program.Therefore, the number of word that is used for the memory 610 of storage decoding intermediate object program becomes 6, and this number is for the line number order 30 of the check matrix H of Figure 15 number 5 divided by the decoding intermediate object program that is read simultaneously and write.

The memory 613 that is used for storage decoding intermediate object program reads 5 decoding intermediate object program w simultaneously from 5 stored decoding intermediate object program D613, and they are offered cyclic shift circuits 614 as decoding intermediate object program D613, wherein, described 5 decoding intermediate object program w are the decoding intermediate object program v that determine by calculating unit 615 _i' " 1 " in the row of corresponding check matrix H.

For example, the memory 613 for storage decoding intermediate object program comprises the single port RAM that can read simultaneously and write 5 decoding intermediate object programs.Since by calculating unit 612 first that calculate, be stored in for the decode memory 613 of intermediate object program of storage corresponding to the decoding intermediate object program w of row, therefore, be stored in the data volume for the memory 613 of storage decoding intermediate object program, namely, the required memory capacity of memory 613 that is used for storage decoding intermediate object program, the line number purpose that becomes the quantization number of decoding intermediate object program and the check matrix H value that multiplies each other.

5 decoding intermediate object program D613 (decoding intermediate object program w) are offered cyclic shift circuits 614 from the memory 613 that is used for storage decoding intermediate object program.In addition, to offer cyclic shift circuits 614 from control assembly 617 corresponding to the control signal D621 of decoding intermediate object program D613, wherein, control signal D621 indicates the information (matrix data) about such fact: the result as the unit matrix cyclic shift how many times that for example will form the check matrix basis arranges 1 of check matrix.Based on control signal D621, cyclic shift circuits 614 rearranges the cyclic shift of 5 decoding intermediate object program D613, and the result is offered calculating unit 615 as decoding intermediate object program D614.

Calculating unit 615 comprises 5 calculators 615 ₁To 615 ₅5 decoding intermediate object program D614 (w) are offered variable node calculating unit 615 from cyclic shift circuits 614, in addition, with 5 decoding intermediate object program D610 (v _i') offer variable node calculating unit 615 from the memory 610 that is used for storage decoding intermediate object program.The intermediate object program of will decoding D614 and decoding intermediate object program D610 offer calculator 615 ₁To 615 ₅Each.5 received data D617 are offered calculating unit 615 from the memory 617 that is used for receiving, and received data D617 is offered separately calculator 615 ₁To 615 ₅Each.In addition, control signal D622 is offered calculating unit 617 from control assembly 617, and control signal D622 is offered calculator 615 ₁To 615 ₅Control signal D622 is 5 calculators 617 ₁To 617 ₅Total signal.

Calculator 615 ₁To 615 ₅Each is by using decoding intermediate object program D614 and D611 and received data D617 (LDPC code) and carry out second according to formula (1), formula (10) and formula (11) and calculate, in order to determine 5 intermediate object program (v that decode of 1 corresponding to each row of check matrix _i').Calculating unit 615 will be as calculator 615 ₁To 615 ₅5 decoding intermediate object program D615 that carry out the second result who calculates and obtain offer the memory 610 for storage decoding intermediate object program.

The memory 616 that is used for receiving will be stored as received data D617 from the reception LLR (log-likelihood ratio) that the institute's reception value (sign bit) that receives by communication channel is calculated, and wherein, receives 0 similarity of LLR is-symbol position.

More particularly, at the place, the first address of the memory 616 that be used for to receive, storage corresponding among the received data D617 of the row of check matrix, corresponding to the 1st row of the check matrix received data D617 to the 5th row.At place, the 2nd address, store corresponding to the 6th of check matrix and be listed as the received data D617 that is listed as to the 10th, and at place, the 3rd address, storage is listed as the received data D617 that is listed as to the 16th corresponding to the 11st of check matrix.Subsequently, similarly, at 18 addresses, the 4th address to the places, with the unit storage of 5 data corresponding to the received data D617 of the 17th row to the 90th row.

Then, the memory 616 that be used for to receive with the unit of 5 data, carry out second according to calculating unit 615 and calculate necessary order and read simultaneously stored received data D617, and they are offered calculating unit 615.

For example, comprise single port RAM for the memory 616 that receives.Being stored in the data volume for the memory 616 that receives, that is, being used for the memory 616 necessary memory capacity that receive, is the quantization digit purpose of the code length of LDPC code and the received data value that multiplies each other.In addition, the number of the word of the memory 616 that be used for to receive is 18, and this number is the code length with the LDPC code, and namely the column number 90 of check matrix is divided by the number of the received data D617 that is read simultaneously.

Control assembly 617 offers control signal D618 for the memory 610 of storing decoding intermediate object program, and control signal D619 is offered cyclic shift circuits 611, in order to control respectively them.In addition, control assembly 617 offers calculating unit 612 with control signal D620, and control signal D621 is offered cyclic shift circuits 614, in order to control respectively them.

As according to the memory 610 that is used for storage decoding intermediate object program, cyclic shift circuits 611, calculating unit 612, be used for the result of data of sequential loop of memory 613, cyclic shift circuits 614 and the calculating unit 615 of storage decoding intermediate object program, decoding device 600 can once be decoded.In decoding device 600, after decoding is repeated pre-determined number, the calculating that calculating unit 615 carries out according to formula (5), and, this result of calculation is exported as final decoded result.

Figure 29 is the calculator 612 that the calculating unit 612 of Figure 26 is shown ₁The block diagram of topology example.

Calculator 612 has been described in Figure 29 ₁, and, calculator 612 ₂To calculator 612 ₅Also disposed in the same way.

In addition, in Figure 29, each decoding intermediate object program (v that the second result who calculates who carries out as calculator 615 by hypothesis obtains _i') be quantified as 6 calculator 612 is shown ₁Clock ck is offered the calculator 612 of Figure 29 ₁, and clock ck offered necessary piece.Each piece and clock ck synchronously process.

Based on the control signal D620 that provides from control assembly 617, the calculator 612 of Figure 29 ₁By using the decoding intermediate object program D611 (v that reads successively from cyclic shift circuits 611 _i') carry out calculating according to first of formula (9).

56 the decoding intermediate object program D611 (v that more particularly, will provide from cyclic shift circuits 611 _i') in a decoding intermediate object program D611 offer calculator 612 ₁, will offer EXOR circuit 635 as the sign bit D631 of high-order position, and will be as 6 decoding intermediate object program D611 (v _i') 5 lower-order positions absolute value D632 (| v _i' |) offer adder 631.In addition, control signal D620 is offered calculator 612 from control assembly 617 ₁, and control signal D620 offered selector 633 and selector 637.

Adder 631 by with absolute value D632 (| v _i' |) and be stored in 9 place value D633 in the register 632 accumulative total absolute value D632 of coming added together (| v _i' |), and 9 aggregate-values that will as a result of obtain are stored in the register 632 again.When added up the absolute value D632 that all decoding intermediate object program D611 of 1 determine on corresponding to check matrix delegation (| v _i' |) time, register 632 is reset.

When the aggregate-value of the absolute value D632 gained of the decoding intermediate object program D611 on reading successively check matrix delegation and accumulative total delegation was stored in the register 632, the control signal D620 that provides from control assembly 617 changed into 1 from 0.For example, when row weight when being " 9 ", control signal D620 is " 0 " at the 1st to the 8th clock, and is " 1 " at the 9th clock.

When control signal D620 is " 1 ", the value of register 632 Selective storages in selector 633, that is, accumulative total is corresponding to (the decoding intermediate object program v of all decoding intermediate object program D611 of 1 in the check matrix delegation _i') absolute value D632 (| v _i' |) 9 place value D633 of gained (∑ | v _i' |, from i=1 to i=d _c), and should value output to register 634 as value D634, store thus it.Register 634 offers selector 633 with the value D634 that stores as 9 place value D635, and with its output.When control signal D620 was " 0 ", the value D635 that provides from register 634 was provided for selector 633, and this value is outputed to register 634, came thus again to store it.That is to say that register 634 will before add up | v _i' | offer selector 633, and with its output, until added up (the decoding intermediate object program v corresponding to all decoding intermediate object program D611 of 1 in the check matrix delegation _i') absolute value D632 (| v _i' |) till.

When carrying out above-mentioned processing, EXOR circuit 635 is stored in 1 place value D637 in the register 636 and the XOR of sign bit D631 by calculating, carries out multiplying each other of sign bit, and 1 multiplied result D636 is stored in the register 636 again.The sign bit D631 of all decoding intermediate object program D611 of 1 is all taken advantage of fashionablely on corresponding to check matrix delegation, and register 636 is reset.

As multiplied result D636 (∏ sign (v _i'), from i=1 to d _c) when being stored in the register 636, the control signal D620 that provides from control assembly 617 changes into " 1 " from " 0 ", wherein, will be from multiplying each other corresponding to all determined sign bit D631 of decoding intermediate object program D611 of 1 in the check matrix delegation and obtaining described multiplied result D636 (∏ sign (v _i'), from i=1 to d _c).

When control signal D620 is " 1 ", the value of selector 637 Selective storages in register 636, that is, and the value D637 (∏ sign (v of the gained that will multiply each other corresponding to the sign bit D631 of all decoding intermediate object program D611 of 1 in the check matrix delegation _i'), from i=1 to i=d _c), and should value output to register 638 as 1 place value D638, store thus it.Register 638 offers selector 637 with the value D638 that stores as 1 place value D639, and exports it.When control signal D620 was " 0 ", the value D639 that provides from register 638 was provided for selector 637, and this value is outputed to register 638, came thus again to store it.That is to say that register 638 offers selector 637 with previously stored value, and exports it, until corresponding to (the decoding intermediate object program v of all decoding intermediate object program D611 of 1 in the check matrix delegation _i') sign bit D631 all taken advantage of till.

In calculator 6121, will be altogether 10 as decoding intermediate object program D612 (decoding intermediate object program w) output, wherein, make 9 place value D635 from register 634 outputs (∑ | v _i' |, from i=1 to i=d _c) become 9 lower-order positions, and make from 1 place value D639 (sign (v of register 638 outputs _i')) become high-order position.

As mentioned above, at calculator 612 ₁In, carry out the calculating of formula (9), and determine decoding intermediate object program w.

Figure 30 is the calculator 615 that the calculating unit 615 of Figure 26 is shown ₁The block diagram of topology example.

Calculator 615 has been described in Figure 30 ₁, and calculator 615 ₂To 615 ₅Also disposed in an identical manner.

In addition, in Figure 30, each decoding intermediate object program (w) that the first result who calculates who carries out as calculator 612 by hypothesis obtains and sign bit are quantified as altogether 10 and previous each decoding intermediate object program (u that had obtained as the second result of calculation together _j) and sign bit be quantified as together 6 altogether, calculator 6151 is shown, wherein, provide described decoding intermediate object program (u from the memory 610 that is used for storage decoding intermediate object program _j).In addition, clock ck is offered the calculator 615 of Figure 30 ₁, and clock ck offered necessary piece.Each piece and clock ck synchronously process.

Based on the control signal D622 that provides from control assembly 617, the calculator 615 of Figure 30 ₁By carry out the second calculating according to formula (1), formula (10) and formula (11) with the following: from received data D617 (the reception value u of institute that reads successively for the memory 616 that receives _0i); The decoding intermediate object program D614 (w) that reads successively from cyclic shift circuits 614; From the decoding intermediate object program D610 (v that reads successively for the memory 610 of storing decoding intermediate object program _i'), wherein, before obtained this decoding intermediate object program as the second result who calculates who is undertaken by calculating unit 615.

More particularly, at calculator 615 ₁In, read successively 10 decoding intermediate object program D614 (decoding intermediate object program w) corresponding to the row of check matrix from cyclic shift circuits 614.Read successively before the second result who calculates who carries out as calculating unit 615 and 6 decoding intermediate object program D610 (decoding intermediate object program v that obtain from the memory 610 that is used for storage decoding intermediate object program _i').Sign bit D653 (sign (u with the high-order position of the sign bit D651 (sign (w)) of the high-order position of decoding intermediate object program D614 and decoding intermediate object program D610 _j)) offer EXOR circuit 653.With the absolute value D652 of 9 lower-order positions of decoding intermediate object program D614 (| w|) and the sign bit D653 of 9 lower-order positions of decoding intermediate object program D610 (| v _i' |) offer subtracter 651.In addition, at calculator 615 ₁In, read successively 6 received data D617 from the memory 616 that is used for receiving, and provide it to adder 658.In addition, at calculator 615 ₁In, provide control signal D622 from control assembly 617, and control signal D622 is offered selector 656.

Subtracter 651 deducts absolute value D654 from absolute value D652, and 5 subtraction value D655 are offered LUT 652.LUT 652 outputs are carried out subtraction value D655

Calculate 5 result of calculations of gained

On the other hand, EXOR circuit 653 is by compute sign position D651 (sign (w)) and sign bit D653 (sign (v _i')) XOR sign bit D651 and sign bit D653 are taken together, and with 1 multiplied result as multiplying each other value D657 output.Then, 6 place value D658 are offered adder 654, and provide it to FIFO memory 659, wherein, in described 6 place value D658, make 5 result of calculation D656 that provide from LUT652 become 5 lower-order positions

And make the 1 place value D657 (sign (w) * sign (v that provides from EXOR circuit 653 _i')) become high-order position.

In the above described manner, carry out the calculating according to formula (10), and will be as 6 place value D658 (u of result of calculation _j) offer adder 654, and provide it to FIFO memory 659.

Adder 659 is passed through 6 place value D658 (u _j) and be stored in the 9 place value D659 aggregate-value D658 of coming added together in the register 655, and 9 aggregate-values that will as a result of obtain are stored in the register 655 again.When having added up to list all value D658 of 1 corresponding to check matrix one, register 655 is reset.

As the value D658 that reads successively check matrix one and list, and the value of the value D658 gained of accumulative total one row is when being stored in the register 655, and the control signal D622 that provides from control assembly 617 changes into " 1 " from " 0 ".For example, when the row weight was " 5 ", control signal D622 was " 0 " at the 1st to the 4th clock, and was " 1 " at the 5th clock.

When control signal D622 is " 1 ", the value of selector 656 Selective storages in register 655, that is, and 1 the value D658 (u that accumulative total lists corresponding to check matrix one _j) 9 place value D659 (∑ u of gained _j, from j=1 to j=d _v), and this value outputed to register 657, store thus it.Register 657 offers selector 471 and adder 658 with the value D659 that stores as 9 place value D660.When control signal D622 was " 0 ", the value D660 that provides from register 657 was provided for selector 656, and this value is outputed to register 657, came thus again to store it.That is to say that the value that register 657 will before add up offers selector 656 and adder 658, until added up 1 the value D658 that lists corresponding to check matrix one.

6 received data D617 that adder 658 provides with 9 place value D660 with from the memory 616 that be used for to receive are added together, and are provided as the 9 place value D661 that the result obtains.

In calculator 615, in the time will carrying out last calculating, adder 658 is exported 9 place value D661 as final decoded result.That is to say the calculating that calculating unit 615 carries out according to formula (5).

On the other hand, FIFO memory 659 postpones 6 place value D658 (u _j), until from the new value of register 665 outputs D660 (∑ u _j, from j=1 to j=d _v) till, and should value offer subtracter 660 as 6 place value D662.Subtracter 660 deducts 6 place value D662 from 9 place value D660, and output subtraction value D663.That is to say that subtracter 660 deducts the value corresponding to the rib that will determine from the aggregate-value of 1 the value D658 that lists corresponding to check matrix one, that is, and corresponding to 1 value D658 (u of predetermined check matrix _j), and with subtraction value (∑ u _j, from i=1 to i=d _v-1) as 6 subtraction value D663 output.

In the above described manner, carry out the calculating according to formula (1), and output is as 6 subtraction value D663 (v of result of calculation _i).Then, will from the absolute value of 5 lower-order positions of 6 subtraction value D663 of subtracter 660 output (| v _i|) offer LUT 661, and sign bit (sign (v that will high-order position _i)) as value D665 output.

LUT 661 output to absolute value (| v _i|) carry out

5 result of calculation D666 of calculating gained

Then, LUT 661 incites somebody to action altogether 6 conduct decoding intermediate object program (v _i') offer the memory 610 for storage decoding intermediate object program, wherein, make from 5 result of calculations of LUT 661 outputs Become 5 lower-order positions, and the value of making D665 (sign (v _i)) become high-order position.

As mentioned above, at calculator 615 ₁In, carry out the calculating of formula (1), formula (10) and formula (11), and determine decoding intermediate object program v _i'.

The maximum of the row weight of the check matrix of Figure 15 is 5, that is to say, offers calculator 615 ₁Decoding intermediate object program D614 (w) and decoding intermediate object program D610 (v _i') maximum number be 5.Therefore, calculator 615 ₁ Have FIFO memory 659, be used for 5 result of calculation D658 (u that postpone 5 decoding intermediate object program D614 and determine from decoding intermediate object program D610 _j).When wanting the calculated column weight less than 5 message, the retardation in the FIFO memory 659 is reduced to the value of row weight.

Figure 31 is the block diagram of topology example that the memory 610 that is used for storage decoding intermediate object program of Figure 26 is shown.

The memory 610 that is used for storage decoding intermediate object program comprises switch 701 and 704 and the RAM 702 and 703 that is used for storage decoding intermediate object program, and wherein, RAM 702 and 703 is two single port RAM.

Before each parts of describing the memory 610 that is used for storage decoding intermediate object program in detail, at first description is used for data are stored in for the RAM 702 of storage decoding intermediate object program and 703 method.

Be used for the RAM 702 of storage decoding intermediate object program and the decoding intermediate object program D615 that 703 storages provide by switch 701, wherein, the first result who calculates who carries out as calculating unit 612 and obtain described decoding intermediate object program D615.

More particularly, place, 5 addresses, the 1st address to the at the RAM 702 that is used for storage decoding intermediate object program, according to for every delegation, in the horizontal direction (at column direction) the 1st row of the check matrix H of Figure 15 to 1 filling of the 5th row is got more closely mode (according to the mode of ignoring 0), store the decoding intermediate object program D615 (D701) corresponding to them.

More particularly, when the capable i tabulation of j is shown (j, i), place, the 1st address at the RAM 702 that is used for storage decoding intermediate object program, storage is corresponding to 1 data of 5 * 5 unit matrixs of the check matrix from (1,1) to (5,5) of Figure 15.Locate in the 2nd address, storage corresponding to the check matrix that forms Figure 15 from (6,1) to (10,5) and matrix (should and matrix be the first shift matrix and the second shift matrix and, wherein, in the first shift matrix, 5 * 5 unit matrixs are by loopy moving 1 to the right, and in the second shift matrix, 5 * 5 unit matrixs are by loopy moving 2 to the right) the data of 1 position of the first shift matrix.In addition, at the 3rd address place, storage is corresponding to the data that form check matrix 1 positions with the second shift matrix matrix from (6,1) to (10,5).Subsequently, same, at the 4th address and place, the 5th address, store by this way data, so that corresponding to the check matrix of Figure 15.

At the place, 10 addresses, the 6th address to the of the RAM 702 that is used for storage decoding intermediate object program, storage is corresponding to the check matrix of Figure 15 1 data from the 11st row to the 15th row.That is to say, locate in the 6th address, storage is corresponding to forming check matrix from (11,11) to (15,15) and matrix (should and matrix be 5 * 5 unit matrixs and the first shift matrix and, wherein, in the first shift matrix, 5 * 5 unit matrixs are by loopy moving 3 to the right) the data of 1 position of the first shift matrix, and locate in the 7th address, storage is corresponding to (11,11) that form check matrix 1 data to (15,15) and unit matrix matrix.Subsequently, same, at place, 10 addresses, the 8th address to the, store by this way data, so that corresponding to check matrix.

Similarly, place, 28 addresses, the 10th address to the at the RAM 702 that is used for storage decoding intermediate object program, according to corresponding to the such mode of the check matrix of Figure 15, storage is corresponding to 1 data from the 21st row to the 25th row, from the 31st row to the 35th row, from the 41st row to the 45th row, from the 51st row to the 55th row, from the 61st row to the 65th row, from the 71st row to the 75th row, from the 81st row to the 85th row.That is to say that the number of word that is used for the RAM 702 of storage decoding intermediate object program is 28.

Place, 5 addresses, the 1st address to the at the RAM 703 that is used for storage decoding intermediate object program, according to for every delegation, in the horizontal direction (on column direction) the 6th row of the check matrix H of Figure 15 to 1 filling of the 10th row is got more closely mode (according to the mode of ignoring 0), store the decoding intermediate object program D615 (D702) corresponding to them.

More particularly, place, the 1st address at the RAM 703 that is used for storage decoding intermediate object program, storage is corresponding to forming check matrix from (6,1) to (10,5) and matrix (should and matrix be the first shift matrix and the first shift matrix and, wherein, in the first shift matrix, 5 * 5 unit matrixs are by loopy moving 1 to the right, and in the second shift matrix, unit matrix is by loopy moving 2 to the right) 1 data of the first shift matrix, wherein, the first shift matrix be check matrix matrix.At the 2nd address place, storage is corresponding to 1 the data that form from (6,1) to (10,5) and the second shift matrix matrix, and wherein, the second shift matrix is the submatrix of check matrix.Subsequently, same at 5 addresses, the 3rd address to the places similarly, store by this way data, so that corresponding to the submatrix of check matrix.

Similarly, at the place, 26 addresses, the 6th address to the of the RAM 703 that is used for storage decoding intermediate object program, storage is corresponding to the check matrix of Figure 15 1 data from the 16th row to the 20th row, from the 26th row to the 30th row, from the 36th row to the 40th row, from the 46th row to the 50th row, from the 56th row to the 60th row, from the 66th row to the 70th row, from the 76th row to the 80th row and from the 86th row to the 90th row.That is to say that the number of word that is used for the RAM 703 of storage decoding intermediate object program is 26.

As mentioned above, the number of word that is used for the RAM 702 of storage decoding intermediate object program is 28, and the number of word that is used for the RAM 703 of storage decoding intermediate object program is 26.

Figure 32 is the sequential chart with write operation of reading of the RAM 702 that is used for storage decoding intermediate object program of the diagram memory 610 that is used for storage decoding intermediate object program and the RAM 703 that is used for storage decoding intermediate object program.

In Figure 32, trunnion axis represents the time (t).

At the memory 610 that is used for storage decoding intermediate object program, when calculating unit 612 will carry out the first calculating, based on the control signal D720 that provides from control assembly 617 ₂, read the stored decoding intermediate object program D703 that obtains as the second result of calculation from the RAM 702 that is used for storage decoding intermediate object program, perhaps based on the control signal D720 that provides from control assembly 617 ₃, read the stored decoding intermediate object program D704 that obtains as the second result of calculation from the RAM 703 that is used for storage decoding intermediate object program.The decoding intermediate object program that reads is offered cyclic shift circuits 614 by switch 704.

When calculating unit 615 will carry out the second calculating, the decoding intermediate object program D615 (v that will obtain as the second result of calculation _i') offer for the memory 610 of storing decoding intermediate object program from calculating unit 615.Be written to for the RAM 702 of storage decoding intermediate object program and when being used for the presumptive address place of one of RAM 703 of storage decoding intermediate object program at the intermediate object program D615 that will decode, read before the second result who calculates who carries out as calculating unit 615 and the decoding intermediate object program D610 (v that obtains from other RAM _i'), and by cyclic shift circuits 614 it is outputed to calculating unit 615.

5 decoding intermediate object program D615 are offered switch 701 from calculating unit 615, in addition, with control signal D720 ₁Offer switch 701, wherein, control signal D720 ₁Indication is selected to be used for the RAM 702 of storage decoding intermediate object program and is used for one of RAM 703 of storage decoding intermediate object program, as the memory that is used for storage decoding intermediate object program D615.Based on control signal D720 ₁, switch 701 is selected to be used for the RAM 702 of storage decoding intermediate object program and is used for one of RAM 703 of storage decoding intermediate object program, and 5 decoding intermediate object program D612 are offered selected in them one.

5 decoding intermediate object program D612 are offered for the RAM 702 that stores decoding intermediate object program from switch 701 as decoding intermediate object program D701, in addition, will indicate the control signal D702 of address ₂Offer RAM 702 from control assembly 617.The RAM 702 that is used for storage decoding intermediate object program reads and is stored in by control signal D720 ₂5 decoding intermediate object program D701 at the address place of indication, and they are offered switch 704 as decoding intermediate object program D703, wherein, the second result who calculates who had before carried out as calculating unit 615 and obtain described 5 decoding intermediate object program D701.In addition, be used for 5 decoding intermediate object program D702 storages (writing) that the RAM 702 of storage decoding intermediate object program will provide from switch 701 to by control signal D720 ₂The place, address of indication.

5 decoding intermediate object program D615 are offered for the RAM 703 that stores decoding intermediate object program from switch 701 as decoding intermediate object program D702, in addition, will indicate the control signal D720 of address ₃Offer RAM 703 from control assembly 617.The RAM 703 that is used for storage decoding intermediate object program reads and is stored in by control signal D720 ₃5 decoding intermediate object program D702 at the address place of indication, and they are offered switch 704 as decoding intermediate object program D704, wherein, the second result who calculates who had before carried out as calculating unit 615 and obtain described 5 decoding intermediate object program D702.In addition, be used for 5 decoding intermediate object program D702 storages (writing) that the RAM 702 of storage decoding intermediate object program will provide from switch 701 to by control signal D720 ₃The place, address of indication.

Decoding intermediate object program D703 is offered switch 704 from the RAM 702 that is used for storage decoding intermediate object program, and the intermediate object program D704 that perhaps will decode offers switch 704 from the RAM 703 that is used for storage decoding intermediate object program.In addition, with control signal D720 ₄Offer switch 704 from control assembly 617, this control signal D720 ₄Indication is selected to be used for the RAM 702 of storage decoding intermediate object program and is used for one of RAM 703 of storage decoding intermediate object program.Based on control signal D720 ₄, switch 704 is selected to be used for the RAM 702 of storage decoding intermediate object program and is used for one of RAM 703 of storage decoding intermediate object program, and will offer calculating unit 615 as 5 decoding intermediate object program D610 from 5 decoding intermediate object programs that selected RAM provides.

At the memory 610 that is used for storage decoding intermediate object program, when calculating unit 615 will carry out the second calculating, based on control signal D720 ₂Be used for the RAM 702 of storage decoding intermediate object program with 5 results' unit, before previous crops is among the stored decoding intermediate object program D701 that obtains of the second result who calculates that calculating unit 615 carries out, with be stored in the identical address place, read 5 times corresponding to 1 the decoding intermediate object program D701 of check matrix from the 1st row to the 5th row, and by switch 704 they are offered calculating unit 615.That is to say, because the row weight of the check matrix H of Figure 15 is 5, therefore, there are 5 corresponding to 1 decoding intermediate object program of each row of check matrix H, and, the RAM 702 that is used for storage decoding intermediate object program take 5 results as unit, will read 5 times corresponding to 1 decoding intermediate object program D701 from the 1st row to the 5th row.

Next, based on control signal D720 ₃The RAM 703 before previous crops that are used for storage decoding intermediate object program are that the second result who calculates that calculating unit 615 carries out obtains, stored decoding intermediate object program D702, with be stored in the identical address place, read continuously 5 times corresponding to 15 decoding intermediate object program D702 of check matrix from the 6th row to the 10th row, and they are offered calculating unit 615 by switch 704 and cyclic shift circuits 614.Simultaneously, to offer RAM 702 for storage decoding intermediate object program as decoding intermediate object program D701 by switch 701 corresponding to 15 the decoding intermediate object program D615s of check matrix from the 1st row to the 5th row, wherein, obtain described decoding intermediate object program D615 as current the second result who calculates who is just being undertaken by calculating unit 615.Based on control signal D720 ₂, the RAM 702 that is used for storage decoding intermediate object program locates Coutinuous store 5 times at will the decode address of the decoding intermediate object program D703 that intermediate object program D701 read in storage.

Subsequently, based on control signal D720 ₂Be used for the RAM 702 of storage decoding intermediate object program take 5 results as unit, before previous crops is that the second result who calculates that calculating unit 615 carries out obtains, among the stored decoding intermediate object program D701, with be stored in the identical address place, read continuously 5 times corresponding to 1 the decoding intermediate object program D701 of check matrix from the 11st row to the 15th row, and they are offered calculating unit 615 by switch 704.Simultaneously, to offer RAM 703 for storage decoding intermediate object program as decoding intermediate object program D702 by switch 701 corresponding to 15 the decoding intermediate object program D612s of check matrix from the 6th row to the 10th row, wherein, obtain described decoding intermediate object program D612 as current the second result who calculates who is just being undertaken by calculating unit 615.Based on control signal D720 ₃, the decoding intermediate object program D702 that will read for the RAM 703 that stores decoding intermediate object program locates Coutinuous store 5 times in the address of storage decoding intermediate object program D704.

Subsequently, similarly, the RAM 703 that is used for the RAM 702 of storage decoding intermediate object program and is used for storage decoding intermediate object program hockets and reads and write for 5 times, until the second result who calculates who carries out as calculating unit 615 obtains, be stored in for the RAM 702 of storage decoding intermediate object program or be used for the RAM 703 of storage decoding intermediate object program corresponding to all decoding intermediate object programs of 1.

Figure 33 is the flow chart of decode procedure of the decoding device 600 of diagram Figure 26.For example, when the received data that will decode is stored in for the memory 616 that receives, begin this process.

At step S70, the cyclic shift of 5 decoding intermediate object program D613 that cyclic shift circuits 614 rearranges in step S76 (will describe afterwards) storage, and they are offered calculating unit 615, wherein, provide described 5 decoding intermediate object program D613 from the memory 613 that is used for storage decoding intermediate object program.

More particularly, 5 decoding intermediate object program D613 are offered cyclic shift circuits 614 from the memory 613 that is used for storage decoding intermediate object program.In addition, to offer cyclic shift circuits 614 from control assembly 617 corresponding to the control signal D621 of decoding intermediate object program D613, wherein, this control signal D621 indicates the information (matrix data) about such fact: the result as the unit matrix cyclic shift how many times that for example will form the check matrix basis arranges 1 of check matrix.Based on control signal D621, cyclic shift circuits 614 is 5 decoding intermediate object program D613 cyclic shifts (rearranging), and they are offered calculating unit 615 as decoding intermediate object program D614.

Calculate and decoding intermediate object program D612 when also not being stored in memory 613 for storage decoding intermediate object program when also not the received data D617 that provides from the memory 616 that is used for receiving not being carried out first, calculating unit 615 results are set to initial value.

At step S71, calculating unit 615 carries out second and calculates, and will offer as the decoding intermediate object program D615 of result of calculation the memory 610 for storage decoding intermediate object program.

More particularly, at step S70,5 decoding intermediate object program D614 are offered calculating unit 615 from cyclic shift circuits 614, and, step S72 (will describe afterwards), previous decoding intermediate object program D610 is offered calculating unit 615 from the memory 610 that is used for storage decoding intermediate object program.Provide 5 received data D617 from the memory 616 that is used for received data, and 5 decode intermediate object program D615 and D610 and received data D617 are offered separately the calculator 615 of calculating unit 615 ₁To 615 ₅Each.In addition, control signal D622 is offered calculating unit 615 from control assembly 617, and control signal D622 is offered calculator 615 ₁To 615 ₅

Based on control signal D622, calculator 615 ₁To 615 ₅Each is by carrying out the calculating according to formula (1), formula (10) and formula (11) with decoding intermediate object program D614 and D610 and received data D617, and will obtain as result of calculation, corresponding to 1 decoding intermediate object program D615 (v of each row of check matrix _i') offer for the memory 610 of storing decoding intermediate object program.

After the processing of step S71, this process proceeds to step S72, at this step place, the memory 610 that is used for storage decoding intermediate object program will be stored in identical address from the decoding intermediate object program D615 that calculating unit 615 provides at step S71, read the decoding intermediate object program D615 (D610) that has stored, and they are offered cyclic shift circuits 611 and calculating unit 615.

After the processing of step S72, this process proceeds to step S73, and at this step place, control assembly 617 determines whether calculating units 615 have calculated all decoding intermediate object program D615 of 1 corresponding to each row of check matrix.When control assembly 617 determined not calculate all decoding intermediate object program D615, this process was returned step S70, and again carries out above-mentioned processing.

On the other hand, when control assembly in step S73 617 determines that calculating unit 615 has calculated all decoding intermediate object program D615, this process proceeds to step S74, at this step place, the decoding intermediate object program D610 (v that cyclic shift circuits 611 will provide from the memory 610 that is used for storage decoding intermediate object program _i') cyclic shift.

More particularly, 5 decoding intermediate object program D610 are offered cyclic shift circuits 611 from the memory 610 that is used for storage decoding intermediate object program.In addition, to offer cyclic shift circuits 611 from control assembly 617 corresponding to the control signal D619 of decoding intermediate object program D610, wherein, control signal D619 indicates the information (matrix data) about such fact: the result as the unit matrix cyclic shift how many times that for example will form the check matrix basis arranges 1 of check matrix.Based on control signal D619, cyclic shift circuits 611 is 5 decoding intermediate object program D610 cyclic shifts (rearranging), and they are offered calculating unit 612 as decoding intermediate object program D611.

After the processing of step S74, this process proceeds to step S75, and at this step place, calculating unit 612 carries out first and calculates, and will offer cyclic shift circuits 614 as the decoding intermediate object program D612 of result of calculation.

More particularly, at step S74, with 5 decoding intermediate object program D611 (v _i') offer calculating unit 612 from cyclic shift circuits 611, and the intermediate object program D611 that will decode offers separately the calculator 612 of calculating unit 612 ₁To 612 ₅Each.In addition, control signal D621 is offered calculating unit 612 from control assembly 617, and control signal D621 is offered calculator 612 ₁To 612 ₅

Based on control signal D619, calculator 612 ₁To 612 ₅Each is by carrying out the calculating according to formula (9) with decoding intermediate object program D611, and will obtain as result of calculation, offer for the decode memory 613 of intermediate object program of storage corresponding to the decoding intermediate object program D612 (w) of the row of check matrix.

After the processing of step S75, this process proceeds to step S76, and at this step place, the memory 613 that is used for storage decoding intermediate object program will be stored in identical address from the decoding intermediate object program D612 that calculating unit 612 provides at step S75, then, this process proceeds to step S77.

At step S77, control assembly 617 determines whether calculating unit 612 has calculated the decoding intermediate object program D612 corresponding to all row of check matrix.When control assembly 617 determined not calculate all decoding intermediate object programs, this process was returned step S74, and again carries out above-mentioned processing.

On the other hand, when control assembly in step S77 617 determined that calculating units 612 have calculated decoding intermediate object program D612 corresponding to all row, this process was finished.

Decoding device 600 repeats described decoding number with the decode procedure of Figure 33, and just as the value D661 that obtains according to the result of calculation of above-mentioned formula (5) and by calculating unit 621 as final decoded result output.

In the superincumbent description, consisted of by two single port RAM although be used for the memory 610 of storage decoding intermediate object program,, if reading and write of a RAM occured simultaneously, then it can be made of 3 or more RAM.When the physical bit width of RAM is inadequate, provide identical control signal by using a plurality of RAM, these RAM logically can be assumed to be a RAM.

For the part that lacks rib data (corresponding to the message of rib), be stored in (when data are stored in for the memory 610 of storing decoding intermediate object program and 613) during the memory, storing message not, and in the computing interval (in first computing interval at calculating unit 612 places with in second computing interval at calculating unit 615 places), do not calculate.

If bucket formula (barrel) shift unit is used for the cyclic shift circuits 411 and 414 and the cyclic shift circuits 611 and 614 of Figure 26 of cyclic shift circuits 314 and 320, Figure 18 of Figure 16 A and 16B, then can when reducing circuit scale, realizes desirable operation.

In above-mentioned situation, for describing simple reason, be 5 with P, namely form the line number order of submatrix of check matrix and calculating number and be 5 situation as example.The line number order of submatrix and column number differ and are decided to be 5, and can get different values according to check matrix.For example, P can be 360 or 392.

In addition, in the present embodiment, used code length be 90 and encoding rate be 2/3 LDPC code.Yet code length and encoding rate can be arbitrary values.For example, when the line number order of submatrix and column number P are 5, if the total number of rib is less than or equal to 5, then can be by only changing control signal, the decoding device 600 of the decoding device 300 of usefulness Figure 16 A to 16C, the decoding device 400 of Figure 18 and Figure 26 is incited somebody to action or even the LDPC code of any code length and encoding rate is decoded.

In addition, decoding device for certain LDPC code that satisfies certain condition can satisfy desirable any encoding rate of this condition and the arbitrarily LDPC code decoding of code length, wherein, described condition is that line number order and the column number P of submatrix is predetermined value, and the total number of rib is less than or equal to particular value.

When check matrix is not the multiple of row and column number P of submatrix, can be by will entirely being that 0 element is assigned to outside the part (fraction) of check matrix and the Hypothesis matrix is the multiple of P, use the present invention.

Next, can utilize hardware to carry out the said process sequence, and, also can utilize software to carry out this process sequence.When utilizing software to carry out this process sequence, with the installation that forms this software in all-purpose computer etc.

Correspondingly, Figure 34 illustrates the topology example of the embodiment of the computer that the program that is used for execution said process sequence has been installed.

Program can be recorded in advance in the hard disk that serves as recording medium 905 and RAM 903 that is incorporated in the computer.

Replacedly, can be with program interim or permanent storage (record) in the removable recording medium 911 such as floppy disk, CD-ROM (compact disk read-only memory), MO (magneto-optic) dish, DVD (digital multi-purpose disk), disk or semiconductor memory.Can be used as so-called software packaging so removable recording medium 911 is provided.

Except from being installed to the computer such as removable recording medium 911 recited above, can wirelessly program be delivered to computer from the download website by the artificial satellite that is used for digital satellite broadcasting, perhaps program can be delivered to computer by the network such as LAN (local area network (LAN)) or internet wiredly.In computer, can receive at communication component 908 places the program of transmitting by this way, and attach it in the hard disk 905 that wherein comprises.

Computer has merged CPU (CPU) 902.Input/output interface 910 is connected to CPU 902 by bus 901.When the user comprises the input block 907 of keyboard, mouse, microphone etc. by operation and during via input/output interface 910 input instruction, CPU902 carries out the program that is stored among the ROM (read-only memory) 903 according to this instruction.Replacedly, CPU 902 is loaded into following program among the RAM (random access memory) 904, and CPU 902 these programs of execution, and wherein, described program is: be stored in the program in the hard disk 905; From satellite or network delivery, receive and be installed to program the hard disk 905 by communication component 908; Perhaps the removable recording medium 911 from be loaded in driver 909 reads and is installed to the program in the hard disk 905.Therefore, CPU 902 carries out according to the processing of above-mentioned flow chart or according to the processing of above-mentioned block diagram.Then, for example, CPU 902 transmits results from the output block 906 that comprises LCD (liquid crystal display), loud speaker etc., by input/output interface 910 output results from communication component 908, and according to required and further it is recorded in the hard disk 905.

In this manual, do not need to write be used to making computer can carry out the treatment step of the program of various processing with the time sequencing execution according to the order of writing out as flow chart.In addition, can simultaneously or carry out individually their (for example, parallel processing or object-based processing).

Described program can be utilized a Computer Processing, perhaps can be processed by many distributed computers.In addition, program can be delivered to remote computer and can process there.

Can adopt the framework that is used for carrying out simultaneously P check node calculation and P variable node calculating by the LDPC code decoding of the check matrix of the combination of following matrix representative for having, wherein, described matrix is: (the unit matrix of P * P); Accurate unit matrix has wherein replaced as one or more 1 of unit matrix element with 0; Shift matrix, wherein unit matrix or accurate unit matrix are recycled displacement; And matrix, its be the two or more of unit matrix, accurate unit matrix and shift matrix and; And (0 matrix of P * P).Therefore, calculate by carrying out simultaneously P node, frequency of operation can be limited in the feasible scope.Like this, although can carry out a large amount of iterative decodings,, might prevent during reading and writing to memory (FIFO and RAM) from memory (FIFO and RAM) different addresses in access occur.

When the LDPC code that will be represented by the check matrix of Figure 15 by the decoding device 300 of reusing Figure 16 A to 16C is decoded, might be so that the mode of each check-node and per 5 ribs of each variable node be calculated 269 ribs.Therefore, for once decoding, decoding device need to carry out 108 clock operations of 269/5 * 2 ≈.Therefore, in order to carry out 50 decodings, when receiving 90 code information, decoding device need to carry out 108 * 50=5400 time clock operation, thereby can use and be approximately 60 times of high frequency of operation of receive frequency.Therefore, according to the decoding device of Figure 16 A to 16C, when comparing with the decoding device for carrying out successively node calculating of Fig. 9, only need 1/5 frequency of operation.When seeing from the aspect of circuit scale, because memory size is identical, therefore, even logical circuit becomes greatly a little, also be little on the impact of integral body.

The decoding device 400 of Figure 18 and the decoding device 600 of Figure 26 have the memory capacity less than the memory capacity of the decoding device 300 of Figure 16 A to 16C.

For example, when the check matrix of LDPC code is that the quantization number of the check matrix of Figure 15 and LDPC code is when being 6, in the decoding device 300 of Figure 16 A to 16C, the rib data storage needs two RAM with capacity of 269 (total number of rib) * 6=1614 positions, namely, for two RAM, need the capacity of 1614 * 2=3228 position.As a comparison, for example, when the quantization number of decoding intermediate object program v is 9, in the decoding device 400 of Figure 18, need to provide the RAM of 1614 bit capacities of the total number with rib to the memory 413 that is used for storage decoding intermediate object program, and needing provides such RAM to the memory 410 that is used for storage decoding intermediate object program, its quantization digit purpose with the code length (column number of check matrix) of LDPC code and decoding intermediate object program v the multiply each other capacity of value, the i.e. capacity of 90 * 9=810 position.Like this, can reduce the circuit scale of decoding device.In addition, in the decoding device 400 of Figure 18, there is no need to have the FIFO memory owing to be used for carrying out the second calculating unit 415 that calculates, therefore, can reduce the circuit scale of logic.

In addition, for example, when the check matrix of LDPC code is that the quantization number of the check matrix of Figure 15 and decoding intermediate object program v is when being 10, in the decoding device 600 of Figure 26, need to provide the RAM of 1614 bit capacities of the total number with rib to the memory 610 that is used for storage decoding intermediate object program, and needing provides such RAM to the memory 613 that is used for storage decoding intermediate object program, it has the capacity of the value that multiplies each other of the line number order of check matrix and the intermediate object program v that decodes, the i.e. capacity of 30 * 10=300 position.Like this, can reduce the circuit scale of decoding device.In addition, in the decoding device 600 of Figure 26, there is no need to have the FIFO memory owing to be used for carrying out the first calculating unit 612 that calculates, therefore, can reduce the circuit scale of logic.

Generally speaking, because the code length of LDPC code greatly to thousands of to tens thousand of, therefore uses P value size to be hundreds of LDPC codes.In this case, use the advantage according to decoding device of the present invention to increase.

In addition, owing to realize faithfully sum-product algorithm according to decoding device of the present invention, therefore the decoding loss except message quantizes can not appear.

Industrial usability

According to above-mentioned viewpoint, by using according to decoding device of the present invention, the high-performance decoding becomes possible.

Claims (22)

1. decoding device that is used for the decoding of low-density checksum LDPC code, described LDPC code represents by the check matrix that is comprised of a plurality of submatrixs, described submatrix comprises P * P unit matrix, accurate unit matrix, shift matrix, 0 matrix with matrix and P * P, wherein accurate unit matrix is to have with 0 to have replaced one or more 1 unit matrix, shift matrix is unit matrix or the accurate unit matrix that is recycled displacement, with matrix be described unit matrix, two or more in described accurate unit matrix and the described shift matrix and, described decoding device comprises:

The first calculating unit is for carrying out simultaneously for P check node calculation with described LDPC code decoding;

The second calculating unit, P the variable node that is used for carrying out simultaneously for described LDPC code decoding calculates; With

The message stores parts, for the message data that reads and write corresponding to P bar rib, described message data obtains as the result of a described P check node calculation or described P variable node calculating;

Wherein, be 2 or larger submatrix for its weight, described message stores parts will be stored in the identical address place corresponding to the message data of P bar rib, and described P bar rib belongs to adds up mutually that to form its weight be 2 or each unit matrix, accurate unit matrix and/or the shift matrix of larger described submatrix.

2. according to claim 1 decoding device, wherein, described the first calculating unit has be used to the P that carries out check node calculation check node calculation device, and

Described the second calculating unit has P the variable node calculator that calculates be used to carrying out variable node.

3. according to claim 1 decoding device, wherein, described message stores component stores gets the message data corresponding to P bar rib that more tight such mode reads to go up in the row direction 1 filling with check matrix during check node calculation.

4. according to claim 1 decoding device, wherein, the message data corresponding to P bar rib that described message stores component stores read 1 filling of check matrix got more tight such mode on column direction in the variable node computing interval.

5. according to claim 1 decoding device, wherein said message stores parts comprise line number/P fifo fifo and columns/P FIFO, and

Described line number/P and described columns/P correspond respectively to the quantity of the word of the capable weight of described check matrix and row weight.

6. according to claim 1 decoding device, wherein, described message stores parts comprise random access memory, and

Described random access memory according to described message data filling is got more closely such mode, reading the described message data of sequential storage, and read described message data with the memory location order.

7. according to claim 1 decoding device also comprises:

Receive information storage part spare, be used for storing the information of the LDPC code that receives, and read simultaneously P described received information.

8. according to claim 7 decoding device, wherein, described reception information storage part spare is stored described reception information in such a manner, and this mode is: can calculate necessary order according to described variable node and read received information.

9. according to claim 1 decoding device also comprises:

Rearrange parts, be used for rearranging the message that obtains as the result of a described P check node calculation or described P variable node calculating.

10. according to claim 9 decoding device, wherein, the described parts that rearrange comprise barrel shifter.

11. decoding device according to claim 1, wherein, described the first calculating unit and described the second calculating unit are determined the message corresponding to P bar rib.

12. decoding device that is used for the decoding of low-density checksum LDPC code, described LDPC code represents by the check matrix that is comprised of a plurality of submatrixs, described submatrix comprises P * P unit matrix, accurate unit matrix, shift matrix, 0 matrix with matrix and P * P, wherein accurate unit matrix is to have with 0 to have replaced one or more 1 unit matrix, shift matrix is unit matrix or the accurate unit matrix that is recycled displacement, with matrix be described unit matrix, two or more in described accurate unit matrix and the described shift matrix and, described decoding device comprises:

The first calculating unit is for carrying out simultaneously for P check node calculation with described LDPC code decoding;

The second calculating unit, P the variable node that is used for carrying out simultaneously for described LDPC code decoding calculates; With

The message stores parts, for the message data that reads and write corresponding to P bar rib, described message data obtains as the result of a described P check node calculation or described P variable node calculating;

Wherein, for the submatrix that is formed by accurate unit matrix, described message stores parts will be stored in the identical address place corresponding to the message data of P bar rib, and described P bar rib belongs to add up mutually and forms each unit matrix, accurate unit matrix and/or the shift matrix of the described submatrix that is comprised of accurate unit matrix.

13. decoding device according to claim 12, wherein, described the first calculating unit has be used to the P that carries out check node calculation check node calculation device, and

Described the second calculating unit has P the variable node calculator that calculates be used to carrying out variable node.

14. decoding device according to claim 12, wherein, described message stores component stores gets the message data corresponding to P bar rib that more tight such mode reads with 1 filling of going up in the row direction check matrix during check node calculation.

15. decoding device according to claim 12, wherein, the message data corresponding to P bar rib that described message stores component stores read 1 filling of check matrix got more tight such mode on column direction in the variable node computing interval.

16. decoding device according to claim 12, wherein said message stores parts comprise line number/P fifo fifo and columns/P FIFO, and

Described line number/P and described columns/P correspond respectively to the quantity of the word of the capable weight of described check matrix and row weight.

17. decoding device according to claim 12, wherein, described message stores parts comprise random access memory, and

Described random access memory according to described message data filling is got more closely such mode, reading the described message data of sequential storage, and read described message data with the memory location order.

18. decoding device according to claim 12 also comprises:

Receive information storage part spare, be used for storing the information of the LDPC code that receives, and read simultaneously P described received information.

19. decoding device according to claim 18, wherein, described reception information storage part spare is stored described reception information in such a manner, and this mode is: can calculate necessary order according to described variable node and read received information.

20. decoding device according to claim 12 also comprises:

Rearrange parts, be used for rearranging the message that obtains as the result of a described P check node calculation or described P variable node calculating.

21. decoding device according to claim 20, wherein, the described parts that rearrange comprise barrel shifter.

22. decoding device according to claim 12, wherein, described the first calculating unit and described the second calculating unit are determined the message corresponding to P bar rib.

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