CN101567361B - Wafer alignment mark - Google Patents
Wafer alignment mark Download PDFInfo
- Publication number
- CN101567361B CN101567361B CN2008100365876A CN200810036587A CN101567361B CN 101567361 B CN101567361 B CN 101567361B CN 2008100365876 A CN2008100365876 A CN 2008100365876A CN 200810036587 A CN200810036587 A CN 200810036587A CN 101567361 B CN101567361 B CN 101567361B
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- wafer
- alignment mark
- wafer alignment
- mark
- symmetric form
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Abstract
The invention provides a wafer alignment mark. In the prior art, the wafer edge is provided with a notch as a wafer alignment mark. The notch is easy to generate stress or defect on the wafer, therebyaffecting the quality of the peripheral devices. In the invention, the wafer alignment mark is arranged at the wafer back and is an axis symmetry-type laser mark. The invention can effectively improv e the finished product ratio of semiconductor devices on the wafer under the premise of ensuring the wafer alignment precision.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of wafer alignment mark.
Background technology
In field of semiconductor manufacture, now make a breach (notch) in manufacture process, to aim at the edge of wafer usually, this kind alignment mark exists advantage simply and easily, but this breach is easily introduced defective or stress at crystal round fringes, thereby influences quality of semiconductor devices and rate of finished products near the breach.
Therefore, how to provide a kind of wafer alignment mark, become the technical problem that industry needs to be resolved hurrily with in the rate of finished products of guaranteeing to improve under the prerequisite of alignment precision wafer semiconductor-on-insulator device.
Summary of the invention
The object of the present invention is to provide a kind of wafer alignment mark, can improve the rate of finished products of wafer semiconductor-on-insulator device by described mark.
The object of the present invention is achieved like this: a kind of wafer alignment mark be arranged on wafer rear, and it is an axis symmetric form laser mark.
In above-mentioned wafer alignment mark, this wafer alignment mark is arranged on the edge of wafer rear.
In above-mentioned wafer alignment mark, this axis symmetric form laser is labeled as a circle.
In above-mentioned wafer alignment mark, this axis symmetric form laser is labeled as a cross.
In above-mentioned wafer alignment mark, this axis symmetric form laser is labeled as one group of palisade striped.
With the alignment mark on the wafer in the prior art is low the comparing of rate of finished products that breach easily causes wafer semiconductor-on-insulator device, wafer alignment mark of the present invention is produced on wafer rear, and be axis symmetric form laser mark, so can avoid on wafer, causing stress or defective, and then can under the prerequisite of guaranteeing the wafer alignment precision, effectively improve the rate of finished products of wafer semiconductor-on-insulator device.
Description of drawings
Wafer alignment mark of the present invention is provided by following embodiment and accompanying drawing.
Fig. 1 is the schematic diagram of wafer alignment mark first embodiment of the present invention;
Fig. 2 is the schematic diagram of wafer alignment mark second embodiment of the present invention;
Fig. 3 is the schematic diagram of wafer alignment mark the 3rd embodiment of the present invention.
Embodiment
Below will be described in further detail wafer alignment mark of the present invention.
Wafer alignment mark of the present invention is arranged on the edge at the back side 10 of wafer 1, and described wafer alignment mark is an axis symmetric form laser mark.
It should be noted that the one side opposite with the back side 10 of wafer 1 is that the front of wafer 1 is used to make semiconductor device.
Referring to Fig. 1, in first embodiment of the invention, described wafer alignment mark 2 is arranged on the back side 10 of wafer 1, and it is a circle for laser mark and its, and described diameter of a circle is 10 microns.
Referring to Fig. 2, in second embodiment of the invention, described wafer alignment mark 3 is arranged on the back side 10 of wafer 1, and it is a cross for laser mark and its.
Referring to Fig. 3, in third embodiment of the invention, described wafer alignment mark 4 is arranged on the back side 10 of wafer 1, and it is one group of palisade striped for laser mark and its, and described palisade striped is made up of 4 stripe.
In semiconductor fabrication, use the wafer alignment mark 2,3 and 4 described in Fig. 1 to Fig. 3 can guarantee that wafer semiconductor-on-insulator device is manufactured on its predeterminated position, and can avoid in the prior art offering breach as stress and defect problem that alignment mark caused at crystal round fringes.
In sum, wafer alignment mark of the present invention is produced on wafer rear, and be axis symmetric form laser mark, so can avoid on wafer, causing stress or defective, and then can under the prerequisite of guaranteeing the wafer alignment precision, effectively improve the rate of finished products of wafer semiconductor-on-insulator device.
Claims (5)
1. a wafer alignment mark is characterized in that, described wafer is not provided with breach, and this wafer alignment mark is arranged on wafer rear, and it is an axis symmetric form laser mark.
2. wafer alignment mark as claimed in claim 1 is characterized in that this wafer alignment mark is arranged on the edge of wafer rear.
3. wafer alignment mark as claimed in claim 1 is characterized in that, this axis symmetric form laser is labeled as a circle.
4. wafer alignment mark as claimed in claim 1 is characterized in that, this axis symmetric form laser is labeled as a cross.
5. wafer alignment mark as claimed in claim 1 is characterized in that, this axis symmetric form laser is labeled as one group of palisade striped.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100365876A CN101567361B (en) | 2008-04-24 | 2008-04-24 | Wafer alignment mark |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100365876A CN101567361B (en) | 2008-04-24 | 2008-04-24 | Wafer alignment mark |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101567361A CN101567361A (en) | 2009-10-28 |
| CN101567361B true CN101567361B (en) | 2011-02-02 |
Family
ID=41283451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100365876A Expired - Fee Related CN101567361B (en) | 2008-04-24 | 2008-04-24 | Wafer alignment mark |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101567361B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102221792A (en) * | 2010-04-13 | 2011-10-19 | 中芯国际集成电路制造(上海)有限公司 | Alignment method performed in semiconductor lithography process |
| CN103077904B (en) * | 2013-01-14 | 2015-09-09 | 武汉新芯集成电路制造有限公司 | A kind of method that bonding machine platform device is aimed at bonding |
| CN104249992B (en) * | 2013-06-28 | 2016-08-10 | 上海华虹宏力半导体制造有限公司 | Alignment methods between wafer and wafer |
| CN103531510A (en) * | 2013-10-24 | 2014-01-22 | 华东光电集成器件研究所 | Transfer and alignment photoetching method of P+ epitaxy pattern of semiconductor circuit |
| CN104655006B (en) * | 2013-11-19 | 2017-09-22 | 中芯国际集成电路制造(上海)有限公司 | The detection method that the component graphics of wafer frontside are aligned with the dorsal pore at the back side |
| CN105819395B (en) * | 2015-01-09 | 2017-09-05 | 中国科学院微电子研究所 | Method, semi-conductor device manufacturing method |
| CN108828902B (en) * | 2018-06-25 | 2020-10-27 | 中国电子科技集团公司第四十一研究所 | Dielectric substrate photoetching alignment mark, alignment method and photoetching method |
| CN110808238B (en) * | 2019-11-06 | 2021-06-29 | 全球能源互联网研究院有限公司 | Preparation method of transparent semiconductor material double-sided alignment mark |
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2008
- 2008-04-24 CN CN2008100365876A patent/CN101567361B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101567361A (en) | 2009-10-28 |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110202 Termination date: 20190424 |
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| CF01 | Termination of patent right due to non-payment of annual fee |