CN101562131A - Method for manufacturing gate structure - Google Patents
Method for manufacturing gate structure Download PDFInfo
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- CN101562131A CN101562131A CNA2008100927869A CN200810092786A CN101562131A CN 101562131 A CN101562131 A CN 101562131A CN A2008100927869 A CNA2008100927869 A CN A2008100927869A CN 200810092786 A CN200810092786 A CN 200810092786A CN 101562131 A CN101562131 A CN 101562131A
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- metal silicide
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Abstract
The invention discloses a method for manufacturing a gate structure, which comprises the steps: firstly, a substrate is supplied, a gate dielectric layer is formed on the substrate, and at least one dielectric post is formed on the gate dielectric layer; secondly, a polycrystalline silicon layer is formed above the substrate in adaptability to cover the dielectric post and the gate dielectric layer; thirdly, an etching technology is carried out, the partial polycrystalline silicon layer is removed, and two polycrystalline silicon clearance walls are formed on the side wall of the dielectric post; fourthly, an etching stop layer is formed on the substrate, and a dielectric layer is formed to cover the etching stop layer, the two polycrystalline silicon clearance walls and the dielectric post; fifthly, the dielectric post and the dielectric layer are partially removed, the surfaces of the dielectric post and the dielectric layer are lower than the surface of a polycrystalline silicon post; and sixthly, a metal silicide self-aligning technology is carried out to convert the polycrystalline silicon post into a metal silicide post.
Description
Technical field
The invention relates to a kind of semiconductor technology, and particularly relevant for a kind of manufacture method of grid structure.
Background technology
Photoetching process (Photolithography) is one of step the most very important in the whole semiconductor technology.The pattern of every relevant for example each layer film with semiconductor component structure all is to decide its critical size by photoetching process (Critical Dimension, size CD) also are decided by the development of photoetching process technology.
For metal oxide semiconductor transistor (MOS Transistor), one of most important member is grid (Gate), and it is in order to control raceway groove (Channel) ON/OFF, and it is positioned on the element region of substrate.In the electronic product of many types, each grid in the element region is parallel to each other, and its live width (Linewidth) critical size in the semiconductor technology for this reason.
And along with the raising day by day of the integrated level of integrated circuit, the component size of whole integrated circuit also must be dwindled thereupon.Particularly, for critical size is 35nm or following grid, can access littler live width in order to make element, and further obtain littler component size, need use more the light source of small wavelength for example be KrF (KrF, 248nm), argon fluoride (ArF, 193nm), fluorine (F
2, 157nm), argon (Ar
2, 126nm) etc., to promote the resolution of step of exposure.But such exposure tool is still very expensive, or still in research and development.
In addition, for downsizing, when carrying out photoetching process, also can utilize the photoresist material layer of thinner thickness and high sensitive (Sensitivity) in response to component size, yet this kind technology will impact follow-up etching technics, and can't dwindle component size.On the other hand, improve the integrated circuit integrated level and constantly dwindle component size when reaching deep-submicron (Deep Submicron) technology for asking, the economic serviceability of photomask cost also becomes a big problem.
Therefore, interval (the Pitch)/width (Size) that how effectively to dwindle and to control grid is the consistent target of industry.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of manufacture method of grid structure is being provided, and need not use high-resolution (high resolution) photoetching process can make the component size downsizing.
Another object of the present invention provides a kind of manufacture method of grid structure, can produce the method for the grid of predetermined small size and relatively large size simultaneously.
The present invention proposes a kind of manufacture method of grid structure.At first, provide a substrate, formed gate dielectric on the substrate, and be formed with at least one dielectric post on the gate dielectric.Then, compliance forms polysilicon layer above substrate, covers dielectric post and gate dielectric.Afterwards, carry out an etching technics, remove the polysilicon layer of part, form two polysilicon gap walls with sidewall in dielectric post.Then, on substrate, form etch stop layer.Then, form dielectric layer to cover etch stop layer, two polysilicon gap walls and dielectric post.Then, carry out a flatening process, remove dielectric post, dielectric layer and the polysilicon gap wall of part, make polysilicon gap wall form polysilicon pillar.Afterwards, carry out etching technics one time, remove the dielectric post and the dielectric layer of part, make the surface of dielectric post and dielectric layer be lower than the surface of polysilicon pillar.Subsequently, carry out one and aim at metal silicide technology voluntarily, make polysilicon pillar be transformed into the metal silicide post.Wherein, the thickness of polysilicon layer equals the critical size of metal silicide post.
Manufacture method according to the described grid structure of embodiments of the invention also comprises: on the metal silicide post, form a metal level, and the dielectric post and the dielectric layer that remove part, to form clearance wall in metal silicide post both sides.Wherein, the material of metal level for example is titanium nitride, tantalum or tungsten.
According to the manufacture method of the described grid structure of embodiments of the invention, above-mentioned gate dielectric is the dielectric materials layer of high-k.
According to the manufacture method of the described grid structure of embodiments of the invention, the material of above-mentioned etch stop layer for example is a silicon oxynitride.
According to the manufacture method of the described grid structure of embodiments of the invention, above-mentioned flatening process is a chemical mechanical milling tech.
According to the manufacture method of the described grid structure of embodiments of the invention, above-mentioned etching technics is the anisotropic etching technics.
The present invention proposes a kind of manufacture method of grid structure in addition.At first, provide a substrate, substrate has first grid polar region and second grid district, has formed gate dielectric on the substrate, and is formed with at least one dielectric post on the gate dielectric in second grid district.Then, compliance forms polysilicon layer above substrate, covers dielectric post and gate dielectric.Afterwards, carry out one first etching technics, remove the part polysilicon layer in second grid district, form two polysilicon gap walls with sidewall in dielectric post.Then, on substrate, form an etching stop layer.Then, carry out one second etching technics, remove the polysilicon layer of first grid polar region, to form at least one first polysilicon pillar.Subsequently, form a dielectric layer, to cover etch stop layer, two polysilicon gap walls, dielectric post and first polysilicon pillars.Afterwards, carry out a flatening process, remove dielectric post, dielectric layer and two polysilicon gap walls of part, make two polysilicon gap walls form two second polysilicon pillars.Then, carry out etching technics one time, remove the dielectric post and the dielectric layer of part, make the surface of dielectric post and dielectric layer be lower than the surface of first polysilicon pillar and second polysilicon pillar.Then, carry out one and aim at metal silicide technology voluntarily, make first polysilicon pillar and second polysilicon pillar be transformed into the first metal silicide post and the second metal silicide post respectively.Wherein, the thickness of polysilicon layer equals the critical size of the second metal silicide post.
Manufacture method according to the described grid structure of embodiments of the invention also comprises: form a metal level on the first metal silicide post and the second metal silicide post.Then, remove the dielectric post and the dielectric layer of part, to form a clearance wall in the first metal silicide post both sides and the second metal silicide post both sides.Wherein, the material of metal level for example is titanium nitride, tantalum or tungsten.
According to the manufacture method of the described grid structure of embodiments of the invention, above-mentioned gate dielectric is the dielectric materials layer of high-k.
According to the manufacture method of the described grid structure of embodiments of the invention, the material of above-mentioned etch stop layer for example is a silicon oxynitride.
According to the manufacture method of the described grid structure of embodiments of the invention, above-mentioned flatening process is a chemical mechanical milling tech.
According to the manufacture method of the described grid structure of embodiments of the invention, the first above-mentioned etching technics is the anisotropic etching technics.
Method of the present invention is the thickness that utilizes the width of dielectric post and be formed at its surperficial polysilicon layer, with the control grid interval/width, therefore need not use high resolution lithography technology, can reach the purpose of reduction of gate size.In addition, method of the present invention can be produced the grid of predetermined small size and relatively large size simultaneously.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Fig. 1 to Fig. 8 is the flow process generalized section of manufacture method of the grid structure of the embodiment of the invention.
The main element symbol description:
100: substrate
101: first grid polar region
103: the second grid district
104: gate dielectric
106: dielectric post
108: polysilicon layer
110,116: the patterning photoresist layer
112: polysilicon gap wall
114: etch stop layer
118: the first polysilicon pillars
119: the first metal silicide posts
120: dielectric layer
122: the second polysilicon pillars
123: the second metal silicide posts
124: metal level
126: clearance wall
Embodiment
Below will be that example further specifies the present invention with the semiconductor technology, but this example be not in order to limit scope of the present invention.Fig. 1 to Fig. 8 is the flow process generalized section of manufacture method of the grid structure of the embodiment of the invention, this grid structure technology includes of the present invention producing and has the method for being scheduled to undersized grid, and the method for producing the grid of predetermined small size and relatively large size simultaneously.
At first, please refer to Fig. 1, a substrate 100 is provided, for example is silicon substrate or other suitable Semiconductor substrate.This substrate 100 has a first grid polar region 101 and a second grid district 103, wherein second grid district 103 is used for making having predetermined undersized grid, for example be critical size (CriticalDimension, CD) be 35nm or following grid, first grid polar region 101 then is the grid that is used for making relatively large size.Then, on substrate 100, form gate dielectric 104.Gate dielectric 104 for example is the dielectric materials layer of high-k, it for example is hafnium oxide (HfO) layer, zirconia (ZrO) layer, aluminium oxide (AlO) layer, titanium oxide (TiO) layer, lanthana (LaO) layer, yittrium oxide (YO) layer, tantalum oxide (TaO) layer or its combination, and its formation method for example is a chemical vapour deposition technique.
Afterwards, please continue, on the gate dielectric 104 in second grid district 103, form dielectric post 106 with reference to Fig. 1.The material of dielectric post 106 for example is a silica, and its formation method for example is first silicon oxide layer deposited, utilizes photoetching, etching technics to form it then.Subsequently, compliance forms a polysilicon layer 108 above substrate 100, to cover dielectric post 106 and gate dielectric 104.The formation method of polysilicon layer 108 for example is a chemical vapour deposition technique.The thickness t that is noted that polysilicon layer 108 especially equals the critical size (that is, live width (Line Width)) of predetermined undersized grid, forms the grid of 32nm live width for instance in advance, then forms thickness and is
Polysilicon layer 108.In addition, the width t ' of dielectric post 106 also can be in order to the interval (Pitch) that determines adjacent two grids.
Then, please refer to Fig. 2, form a patterning photoresist layer 110, cover the polysilicon layer 108 of first grid polar region 101, and expose the polysilicon layer 108 in second grid district 103.Afterwards, serve as the cover curtain with patterning photoresist layer 110, carry out first etching technics, remove the part polysilicon layer 108 in second grid district 103, form polysilicon gap wall 112 with sidewall in dielectric post 106.The first above-mentioned etching technics for example is non-etching technics such as the tropism of grade.
In addition, the present technique field has knows also visual its demand of the knowledgeable usually, and changes execution mode according to the teaching of spirit of the present invention and aforementioned each embodiment.For example, as shown in Figure 2, can be according to the actual process demand, patterning photoresist layer 110 is covered part polysilicon layer 108 in the second grid district 103, then, serves as the cover curtain with patterning photoresist layer 110, carry out etching technics, form polysilicon gap wall 112 with sidewall in dielectric post 106.Above-mentioned patterning photoresist layer 110 covers the zone in second grid district 103 and can change according to its demand, is not limited to shown in Figure 2.
Then, please refer to Fig. 3, remove patterning photoresist layer 110, then on substrate 100, form etch stop layer 114.The material of etch stop layer 114 for example is silicon oxynitride or other suitable materials, and its formation method for example is to utilize nitriding process to form it.Afterwards, remove the polysilicon layer 108 in second grid district 103, it removes method for example is to form photoresist layer (not illustrating), with the polysilicon layer 108 that exposes second grid district 103, be the cover curtain then with the photoresist layer, wait tropism's etching technics, remove the polysilicon layer 108 that is exposed, remove this photoresist layer afterwards.
Subsequently, please refer to Fig. 4, form a patterning photoresist layer 116 above substrate 100, this patterning photoresist layer 116 exposes the part polysilicon layer 108 of first grid polar region 101.Afterwards, serve as the cover curtain with patterning photoresist layer 116, carry out second etching technics, remove the polysilicon layer 108 that comes out, with 101 formation, first polysilicon pillar 118 in first grid polar region.
Subsequently, please refer to Fig. 5, form a dielectric layer 120, cover etch stop layer 114, polysilicon gap wall 112, dielectric post 106 and first polysilicon pillar 118.The material of dielectric layer 120 for example is silica or other suitable dielectric materials, and its formation method for example is to utilize deposition process.Then, carry out a flatening process, remove dielectric post 106, the dielectric layer 120 and polysilicon gap wall 112 of part, make polysilicon gap wall 112 form second polysilicon pillar 122.Above-mentioned flatening process for example is a chemical mechanical milling tech.
Subsequently, please refer to Fig. 6, carry out etching technics one time, remove the dielectric post 106 and dielectric layer 120 of part, make the dielectric post 106 and the surface of dielectric layer 120 be lower than the surface of first polysilicon pillar 118 and second polysilicon pillar 122, to expose the surface of first polysilicon pillar 118 and second polysilicon pillar 122.
Then, please refer to Fig. 7, carrying out one aims at metal silicide voluntarily (Self-Aligned Silicide, Salicide) technology makes first polysilicon pillar 118 and second polysilicon pillar 122 be transformed into the first metal silicide post 119 and the second metal silicide post 123 respectively.The material of the first metal silicide post 119 and the second metal silicide post 123 can be the heating resisting metal silicide, and heating resisting metal wherein is to be selected from the group that titanium, tungsten, platinum, cobalt and nickel are formed.Is example and aim at metal silicide technology voluntarily to form titanium silicide, it generally is elder generation's sputter layer of metal titanium on entire substrate 100, carry out rapid hot technics (Rapid ThermalProcess again, RTP), allow Titanium and be positioned at the silicon atom formation titanium silicide layer that reacts of its below, utilize selectivity wet etching method that the unreacted metal titanium layer is removed again.Wherein, the first metal silicide post 119 and the second metal silicide post 123 for example are whole metal silicide (Fully Silicide), or are made up of polysilicon and metal silicide.
It should be noted that the critical size of the first metal silicide post 119 and the second metal silicide post 123 equals the thickness t of polysilicon layer 108.
Afterwards, please refer to Fig. 8,, also can on the first metal silicide post 119 and the second metal silicide post 123, form metal level 124 in order further to reduce the resistance value of grid.The material of metal level 124 for example is titanium nitride (TiN), tantalum (Ta), tungsten (W), and its formation method for example is a chemical deposition.Next, remove the dielectric post 106 and dielectric layer 120 of part, to form clearance wall 126 in the first metal silicide post, 119 both sides and the second metal silicide post, 123 both sides.
In sum, method of the present invention is the thickness that utilizes the width of dielectric post and be formed at its surperficial polysilicon layer, with the control grid interval (Pitch)/width (Size), and need not use high resolution lithography technology, and can save the technology cost.In addition, method of the present invention can be produced the grid of predetermined small size and relatively large size simultaneously.
Though the present invention discloses as above with embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (14)
1. the manufacture method of a grid structure comprises:
One substrate is provided, has formed a gate dielectric on this substrate, and be formed with at least one dielectric post on this gate dielectric;
Compliance forms a polysilicon layer above this substrate, covers this dielectric post and this gate dielectric;
Carry out an etching technics, remove this polysilicon layer of part, form two polysilicon gap walls with sidewall in this dielectric post;
On this substrate, form an etching stop layer;
Form a dielectric layer, to cover this etch stop layer, this two polysilicon gap walls and this dielectric post;
Carry out a flatening process, remove this dielectric post, this dielectric layer and this two polysilicon gap walls of part, make these two polysilicon gap walls form two polysilicon pillars;
Carry out etching technics one time, remove this dielectric post and this dielectric layer of part, make the surface of this dielectric post and this dielectric layer be lower than the surface of this polysilicon pillar; And
Carry out one and aim at metal silicide technology voluntarily, make this polysilicon pillar be transformed into a metal silicide post,
Wherein the thickness of this polysilicon layer equals the critical size of this metal silicide post.
2. the manufacture method of grid structure as claimed in claim 1 is characterized in that, also comprises:
On this metal silicide post, form a metal level; And
Remove this dielectric post and this dielectric layer of part, to form a clearance wall in these metal silicide post both sides.
3. the manufacture method of grid structure as claimed in claim 2 is characterized in that, the material of this metal level comprises titanium nitride, tantalum or tungsten.
4. the manufacture method of grid structure as claimed in claim 1 is characterized in that, this gate dielectric is the dielectric materials layer of high-k.
5. the manufacture method of grid structure as claimed in claim 1 is characterized in that, the material of this etch stop layer comprises silicon oxynitride.
6. the manufacture method of grid structure as claimed in claim 1 is characterized in that, this flatening process is a chemical mechanical milling tech.
7. the manufacture method of grid structure as claimed in claim 1 is characterized in that, this etching technics is the anisotropic etching technics.
8. the manufacture method of a grid structure comprises:
One substrate is provided, and this substrate has a first grid polar region and a second grid district, has formed a gate dielectric on this substrate, and is formed with at least one dielectric post on this gate dielectric in this second grid district;
Compliance forms a polysilicon layer above this substrate, covers this dielectric post and this gate dielectric;
Carry out one first etching technics, remove this polysilicon layer of part in this second grid district, form two polysilicon gap walls with sidewall in this dielectric post;
On this substrate, form an etching stop layer;
Carry out one second etching technics, remove this polysilicon layer of this first grid polar region, to form at least one first polysilicon pillar;
Form a dielectric layer, to cover this etch stop layer, these two polysilicon gap walls, this dielectric post and this first polysilicon pillar;
Carry out a flatening process, remove this dielectric post, this dielectric layer and this two polysilicon gap walls of part, make these two polysilicon gap walls form two second polysilicon pillars;
Carry out etching technics one time, remove this dielectric post and this dielectric layer of part, make the surface of this dielectric post and this dielectric layer be lower than the surface of this first polysilicon pillar and this second polysilicon pillar; And
Carry out one and aim at metal silicide technology voluntarily, make this first polysilicon pillar and this second polysilicon pillar be transformed into one first metal silicide post and one second metal silicide post respectively,
Wherein the thickness of this polysilicon layer equals the critical size of this second metal silicide post.
9. the manufacture method of grid structure as claimed in claim 8 is characterized in that, also comprises:
On this first metal silicide post and this second metal silicide post, form a metal level; And
Remove this dielectric post and this dielectric layer of part, to form a clearance wall in these first metal silicide post both sides and this second metal silicide post both sides.
10. the manufacture method of grid structure as claimed in claim 9 is characterized in that, the material of this metal level comprises titanium nitride, tantalum or tungsten.
11. the manufacture method of grid structure as claimed in claim 8 is characterized in that, this gate dielectric is the dielectric materials layer of high-k.
12. the manufacture method of grid structure as claimed in claim 8 is characterized in that, the material of this etch stop layer comprises silicon oxynitride.
13. the manufacture method of grid structure as claimed in claim 8 is characterized in that, this flatening process is a chemical mechanical milling tech.
14. the manufacture method of grid structure as claimed in claim 8 is characterized in that, this first etching technics is the anisotropic etching technics.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100927869A CN101562131B (en) | 2008-04-15 | 2008-04-15 | Method for manufacturing gate structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100927869A CN101562131B (en) | 2008-04-15 | 2008-04-15 | Method for manufacturing gate structure |
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| CN101562131A true CN101562131A (en) | 2009-10-21 |
| CN101562131B CN101562131B (en) | 2012-04-18 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738058A (en) * | 2011-04-01 | 2012-10-17 | 无锡华润上华半导体有限公司 | Forming method for active area and forming method for STI trench |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6599831B1 (en) * | 2002-04-30 | 2003-07-29 | Advanced Micro Devices, Inc. | Metal gate electrode using silicidation and method of formation thereof |
| CN100483652C (en) * | 2006-08-18 | 2009-04-29 | 台湾茂矽电子股份有限公司 | Groove power semiconductor device and its making method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738058A (en) * | 2011-04-01 | 2012-10-17 | 无锡华润上华半导体有限公司 | Forming method for active area and forming method for STI trench |
| CN102738058B (en) * | 2011-04-01 | 2014-08-27 | 无锡华润上华半导体有限公司 | Forming method for active area and forming method for STI trench |
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| CN101562131B (en) | 2012-04-18 |
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Address after: 215123 333 Xinghua street, Suzhou Industrial Park, Jiangsu Patentee after: Warship chip manufacturing (Suzhou) Limited by Share Ltd Address before: 215025 Xinghua street, Suzhou Industrial Park, Suzhou, Jiangsu 333 Patentee before: Hejian Technology (Suzhou) Co., Ltd. |
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