CN101558396A - Direct memory access controller - Google Patents
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- CN101558396A CN101558396A CNA2007800460130A CN200780046013A CN101558396A CN 101558396 A CN101558396 A CN 101558396A CN A2007800460130 A CNA2007800460130 A CN A2007800460130A CN 200780046013 A CN200780046013 A CN 200780046013A CN 101558396 A CN101558396 A CN 101558396A
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Abstract
A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.
Description
The cross reference of related application
The application's case advocate the title of application on Dec 15th, 2006 be " DMA park mode (DMA SUSPENDMODE) " the 60/870th, the title of No. 295 U.S. Provisional Application cases and on Dec 15th, 2006 application be " DMA awakening mode (DMA WAKE UP MODE) " the 60/870th, the rights and interests of No. 267 U.S. Provisional Application cases, the mode that described U.S. Provisional Application case is quoted in full is incorporated herein.
Technical field
The technical field of the application's case relates to the direct memory access (DMA) controller.
Background technology
Direct memory access (DMA) controller (DMA) is generally used in microprocessor system, the integrated microcontroller etc.Dma controller is used to be independent of the CPU (central processing unit) of computer system and the data carried out from the storer to the peripheral unit and from the peripheral unit to the storer transmit.For this reason, dma controller can be considered as having second processing unit able to programme of limited ability.In general, the instruction dma controller is sent to destination locations with the data of specified quantitative from the source position.Described source can be in storer (for example storer of the data-carrier store of microcontroller, peripheral unit), or is to be produced or accessible data in peripheral unit by peripheral unit (for example, analog to digital converter, port, capture comparing unit etc.).Therefore the destination also can allow the interior high speed of storage arrangement of computer system or microcontroller to transmit in storer.Yet the destination also can be peripheral unit, for example digital to analog converter, port etc.For data are sent to the destination from the source, dma controller must receive corresponding source and destination way address.In addition, need to specify each to transmit length.For this reason, dma controller need receive the start and end address of length that data transmit or data to be transmitted.
In addition, dma controller is used for the CPU (central processing unit) (CPU) of back-up system, especially transmits at tediously long data.CPU thereby can freely carry out other function.Yet CPU and dma controller are shared same memory bus system.Therefore, in order to forbid between CPU and the DMA conflict (it may stop DMA by CPU) of any kind when the ACCESS bus, DMA has the right of priority that is better than CPU usually, when transmitting well afoot, and the CPU access memory bus that is under an embargo.Although CPU can carry out other function that does not relate to the access of shared storage bus, the dirigibility of this DMA right of priority possibility restriction system.Therefore need a kind of through improved system with dma controller.
Summary of the invention
According to an embodiment, a kind of system can have at least one bus, one with the CPU (central processing unit) (CPU) of described bus coupling, one with the storer of described bus coupling, one have a plurality of DMA passages and be independent of described CPU and operate and with direct memory access (DMA) (DMA) controller of described bus coupling, wherein be the described bus of access, described dma controller can be programmed under first pattern to have the right of priority that is better than described CPU, and can under second pattern, programme, under described second pattern, at least one DMA passage of described dma controller is suspended the described bus of access.
According to another embodiment, described system can further comprise control register, and itself and described dma controller are coupled, and are used for dma controller is programmed, and described control register comprises the position that is used to be provided with first or second pattern.According to another embodiment, can come first or second pattern is programmed by the control signal that is fed to dma controller.According to another embodiment, each in described a plurality of DMA passages can have the priority of being assigned.According to another embodiment, dma controller can comprise channel control register at each passage.According to another embodiment, each channel control register can comprise programmable bit, is used for controlling enabling or inactive described passage.According to another embodiment, can come first or second pattern is programmed by the control signal that comprises priority that is fed to dma controller.
According to another embodiment, a kind of be used for the bus of main device and direct memory access (DMA) (DMA) controller coupling on carry out data transmission method can may further comprise the steps: according to request, permit the described bus of dma controller access to the DMA data transmission; Dma controller is programmed to suspend the DMA data transmission; Permit the described bus of described main device access; Carry out at least one bus access by main device; Dma controller is programmed to recover the DMA data transmission.
According to another embodiment, the described step that dma controller is programmed can be carried out by configurable register.According to another embodiment, the described step that dma controller is programmed can be carried out by the position in the configurable register being set and institute's rheme being resetted.According to another embodiment, the described step that dma controller is programmed can be carried out by control signal is fed to dma controller.According to another embodiment, can produce control signal according to the abnormal signal that is fed to main device.According to another embodiment, if before initial time-out, the data of data transmission transmit initial by dma controller, and system can finish described data transmission so, and then suspend the access of dma controller.According to another embodiment, main device can be CPU (central processing unit) (CPU), and described programming step is carried out by described CPU.According to another embodiment, main device can be peripheral unit, and described programming step can be carried out by CPU (central processing unit).
According to another embodiment, a kind of microcontroller can comprise at least one bus, one with the CPU (central processing unit) (CPU) of described bus coupling, one with the storer of described bus coupling, a plurality of peripheral units with described bus coupling, and one be independent of described CPU and operate and with direct memory access (DMA) (DMA) controller of described bus coupling, wherein be the described bus of access, described dma controller can be programmed under first pattern to have the right of priority that is better than described CPU and described a plurality of peripheral units, and can under second pattern, programme, under described second pattern, described dma controller is suspended the described bus of access.
According to another embodiment, described microcontroller can further comprise control register, and itself and described dma controller are coupled, and are used for dma controller is programmed, and described control register comprises the position that is used to be provided with first or second pattern.According to another embodiment, can come first or second pattern is programmed by the control signal that is fed to dma controller.According to another embodiment, can produce control signal according to the abnormal signal that is fed to CPU (central processing unit).According to another embodiment, dma controller can comprise a plurality of DMA passages.According to another embodiment, dma controller can comprise channel control register at each passage.According to another embodiment, each channel control register can comprise programmable bit, is used for controlling enabling or inactive described passage.According to another embodiment, each channel control register can comprise that one is used for the programmable bit field of the right of priority of definite DMA passage.
According to another embodiment, a kind of being used for main device with have the method for carrying out data transmission on the bus of dma controller coupling of a plurality of direct memory access (DMA) (DMA) passage and can may further comprise the steps: assign a priority to each of described a plurality of DMA passages; According to the request of DMA data transmission, permit dma controller with the described bus of accesses in described a plurality of DMA passages; The pause command that will have priority is fed to dma controller; If the priority in the described pause command is higher than the priority of the DMA passage of the described ACCESS bus of having the right, make any DMA passage suspend the described bus of access so with right of priority lower than the priority in the pause command; And if do not have other DMA passage described bus of access of having the right, would permit main device ACCESS bus so; Carry out at least one bus access by main device; And will recover order and be fed to dma controller, to recover the DMA data transmission.
According to another embodiment, described dma controller can be operated to cycle through a plurality of DMA channel transactions of the DMA passage with equal priority.
The those skilled in the art from following graphic, content is described and claims will be understood other technological merit of the present invention easily.Various embodiment of the present invention can only obtain the subclass of the advantage of stating.Arbitrary advantage is not critical to described embodiment.
Description of drawings
By with reference to the following description of carrying out in conjunction with the accompanying drawings, can obtain the understanding more comprehensively of the present invention and advantage thereof, in the accompanying drawings, identical reference numerals indication same characteristic features, and wherein:
Fig. 1 is the block diagram of the intrasystem typical dma controller of demonstrating computer (for example, microcontroller);
Fig. 2 illustrates employed exemplary bus in the bus matrix;
Fig. 3 is the block diagram of details of showing first embodiment of dma controller;
Fig. 4 is the block diagram of details of showing second embodiment of dma controller;
Fig. 5 is the block diagram of details of showing second embodiment of dma controller;
Fig. 6 A and Fig. 6 B explanation are according to the exemplary register of some aspect that is used to control the system with dma controller of an embodiment;
Fig. 7 shows the process flow diagram according to system's control routine of an embodiment;
Fig. 8 shows the DMA initialization routine;
Fig. 9 shows the process flow diagram of the transmission routine of dma controller;
Figure 10 shows the sequential chart that hyperchannel transmits; And
Figure 11 explanation has the system that uses the functional dma controller that interrupts control system.
Embodiment
According to an embodiment, as indicated above, dma controller and CPU share same data and address bus, data be sent to storer and transmit data from storer.CPU and dma controller may command are to the access of bus.Therefore, CPU or dma controller can be main device.In addition, a plurality of peripheral units can be configurable with the described bus of access, and become main device or slave unit on the described bus.System can " first come, first served (first come) " right of priority or the use right of priority of assigning permit access to bus." first come, first served " priority scheme is permitted any access that at first is requested the bus of access.All other requestors must wait for, and will obtain access sequentially with the order of its request.Yet most systems is used assigned priority scheme, and wherein each may have the privilege of access of the being assigned power that can surmount than low priority by main device.In general, dma controller has highest priority in this system.Therefore, if CPU or peripheral master and dma controller are actively sought the allowance to bus, so dma controller have usually be better than all other may main device the right of priority of ACCESS bus.Therefore, any activation of the data transmission of process dma controller will make CPU or peripheral unit stop.According to an embodiment, dma controller is designed to and can following mode programmes: CPU can (for example) suspends the data of dma controller and transmits by position in the special-purpose control register is set.
Yet, can provide other controlling mechanism to suspend dma controller, for example by the special-purpose control line between CPU and the dma controller.For instance, when CPU receive interrupt or other when unusual, CPU must change context by data being pushed in the storehouse in the shared storage.If CPU provides exception level signal, DMA can use described signal to suspend its activity so, thereby allows CPU to preserve its context quickly, and obtains the access to service routine quickly.
Also can allow incidents such as dma controller should for example interrupt and wake up, and central cpu is retained in power down or the park mode with relevant logic in the digital device.In this way, but dma logic or dma controller services request, and CPU is in park mode with relevant logic.When reaching buffer count or otherwise determining end of transmission (EOT), for example come the wake up process device, and CPU withdraws from power-down mode or park mode by another look-at-me.
Conventional digital device is at present by wake up process device core or total system and carry out corresponding instruction by corresponding interrupt system and come response events.This is consuming time, and causes more multiple current to be consumed with to CPU and program storage power supply, so that carried out service routine before returning dormancy.According to an embodiment, only wake dma controller up and be retained in low power state with the permission of service asynchronous event CPU, program storage and unwanted other assembly of described service when serving described incident.Described incident stores in the local storage nothing more than the content that reads peripheral unit with value usually.This can be finished separately by dma controller.After the described incident of service, according to an embodiment, dma controller can turn back in the park mode.
Microcontroller on the chip or system can have following pattern, and described pattern can be implemented by interrupt system or other suitable control of correspondingly control.In operational mode: all clocks move according to the corresponding configuration value and arrive all peripheral units and CPU (central processing unit).In this pattern, CPU is movable, and consumed power.In first low-power mode (idle mode): processor clock stops, and only consumes standby power, and for example described clock can selectedly be open to the custom and be closed.Bus clock on the bus matrix continues operation.Flash program memory is in standby mode.Interrupt event only starts dma controller, or starts dma controller and the Clock enable processor clock to reduce at full speed.Under second low-power mode (park mode): processor and bus clock stop.The flash program memory outage.The asynchronous interrupt incident only starts clock at dma controller.In other embodiments, can provide more multi-mode, wherein only some installs receive clock, and therefore operates.
The routine techniques digital device does not have the ability that withdraws from low-power mode under the situation of not enabling CPU.According to embodiment in greater detail hereinafter, dma controller can be from the separate payment clock operation pseudo-synchronous with system clock.When external event (for example interrupt) through programming when waking DMA up, will enable this clock.During this process, need not to enable CPU, this saving power.According to an embodiment, when dma controller was finished transmission, the register of storage number n just increased by 1 at every turn.In case the predefine number n＞=l of the DMA incident that has write down warns CPU with regard to available interrupt event.According to an embodiment, interruptable controller can detect the incident at peripheral unit (for example USB or Ethernet), and described peripheral unit waken up to (for example) idle mode, therefore described peripheral unit can be with in its impact damper writing system data random access memory (RAM).Therefore, if the DMA incident occurs during park mode, so only corresponding peripheral unit switches to activity pattern from park mode dma controller and data-carrier store and (randomly).Therefore, only those system components to DMA affairs necessity are activated after request, and in case ask to have finished just with deactivation.
Turn to graphicly, will describe the one exemplary embodiment of the application's case now.Fig. 1 describes the exemplary embodiments of the dma controller (for example microcontroller 100) in the computer system.Microcontroller 100 generally includes CPU (central processing unit) (CPU) 110, and its (for example) is coupled to system component and peripheral unit via bus matrix 120.By bus matrix 120, CPU110 can be directly with a plurality of peripheral unit i to k 145 ... 150 communications, and/or by peripheral bridge 180 and peripheral unit n to m 165 ... 170 communications.Peripheral unit can be (but being not limited to) for example devices such as I/O port, storer, A/D and D/A converter, timer, pulse-width modulator.Interruptable controller 155 can be provided, and its control is used to provide the look-at-me of the asynchronous beginning of the interruption routine in the CPU110.Can use look-at-me to come the current execution of interrupt instruction stream, and force CPU 110 to be branched off into corresponding Interrupt Service Routine.Look-at-me also can be used for controlling the functional of dma controller 125, for example the activation of new tunnel transmission.Yet in addition, look-at-me also can be used for waking up CPU 110, dma controller 125 and other peripheral unit.Bus matrix 120 can provide dedicated interrupt bus to carry these signals.Interruptable controller 155 can be through programming to cover for example some interrupt level, to prevent some look-at-me interruption or to wake CPU110 up.
In addition, can in bus matrix 120, provide dedicated memory bus, to make CPU 110 and flash program memory 135 couplings via cache memory 130.Data random access memory (RAM) 140 also can be coupled to CPU 110 via bus matrix 120.Direct memory access (DMA) controller (DMA) is showed to number 125.This dma controller 125 also is coupled with bus matrix 120, transmits with the data between the device of permission and bus matrix 120 couplings.In bus matrix 120, the DMA unit can be by various buses and storer 140 and peripheral unit 145 ... 150 and 165 ... 170 couplings.In addition, dma controller 125 can receive a plurality of control signals from CPU 110 by bus matrix 120.System Timing Unit 115 directly or by the corresponding control signal in the bus matrix 120 provides various clock signals to CPU with to all unit that need clock.According to an embodiment, be to allow the independent operation of CPU and dma controller, for CPU and dma controller provide two or more independent clock signals.Also can provide different clocks to other system component by bus matrix 120.Perhaps, intrasystem each assembly can be operated to control its oneself power mode.For this reason, bus matrix 120 can comprise the special power control bus with power management block 175 couplings, power management block 175 comprises single or multiple clock signals, power mode signal and control signal, and which unit it indicates operate under which power mode.Yet power management block is alternately directly controlled all unit.
This system allows under the situation about directly relating to of no CPU 110, by dma controller 125 with any peripheral unit 145 of bus matrix 120 coupling ... 150 and 165 ... between 170 and those peripheral units 145 ... 150,165 ... 170 and storer 140 between or transmit data in the storer 140.Usually only need CPU 110 to come initialization dma controller 125, in case and data be transmitted with regard to processing said data.In case dma controller 125 is programmed, just carry out the suitable data transmission down no CPU 110 auxiliary.So CPU 110 can freely carry out other task.For this reason, the system that carries out parallel DMA transmission can not change the power management of the unit that is associated with system usually, because for example in some cases, CPU 110 can carry out standalone feature when dma controller 125 actual figures reportedly send.The flexible control that power management block 175 allows device.Therefore, decide on power save mode, but the different units of parting system.Power save mode changes on power consumption from high to low.CPU 110 is normally movable under most of power save mode, and the operation of timing rate that can be different.Usually only under the peak power save mode, CPU 110 just can disconnect fully.
According to an embodiment, system with CPU 110 and dma controller 125 allows an AD HOC, wherein can be independent of CPU 110 and activate dma controller 125, and wherein CPU 110 can enter power save mode from the clock speed that reduces to the different brackets of complete deactivation simultaneously.According to an embodiment, in case CPU 110 and dma controller 125 enter in the power save mode of higher level in (for example wherein the static schema that is stopped of CPU 110 and dma controller 125), just can activate dma controller 125 independently by the DMA request of transmitting.This request can (for example) produce by corresponding look-at-me.Transmit request in case receive this, dma controller 125 just will be operated.For this reason, if necessary, power management block can be waken dma controller 125 and one or more peripheral units of asking up.Yet in one embodiment, look-at-me itself can activate dma controller 125.Data random access memory 140 even also may be movable during power save mode, but words if not so also can be activated (if necessary) again.In case it all is movable that corresponding DMA transmits necessary all unit, dma controller 125 just begins suitable DMA and transmits.During at this moment, CPU and concerning affairs other unnecessary device be retained in its corresponding park mode.This can (for example) finish by covering interrupt level in the following manner: respective interrupt level only activates dma controller 125 and does not activate CPU 110.Dma controller 125 monitors and controls described transmission, and directly or by power management block 175 sends signal to CPU 110, and described signal will wake CPU 110 up.For instance, in one embodiment, dma controller 125 can produce has the high interruption that wakes the grade of CPU 110 up after DMA transmission is finished of must being enough to.Therefore, CPU can follow the data that further processing has been transmitted.In case CPU 110 has finished any necessary processing, CPU 110 just can enter corresponding power save mode once more.And after dma controller 125 had been served the DMA request, dma controller 125 can reenter dormancy or low-power mode.In one embodiment, initial wakeup process under the situation of the DMA transmission of finishing predetermined number only to CPU 110.For this reason, provide relevant register, it increases by 1 at every turn when DMA transmission has been finished.If the content of this register is greater than or equal to predefine number n＞=l, can only produce the look-at-me that is used to wake up CPU110 so.
In another embodiment, a kind of specified register can comprise the address or the data of the activation of initial CPU 110.If the transition of CPU 110 from the park mode to the activity pattern needs the plenty of time, this embodiment is useful so.Therefore, the intermediate address that is set to the start address that transmits and the predefine number memory location between the end address can trigger the activation again of CPU 110.Therefore, when the DMA transmission has been finished, CPU will be activity, and not have the further delay that any (for example) caused by the oscillator starting time.Replace in specified register, can use bit field in the control register to define skew from the end address, it is used in the DMA transmission and produces wake-up signal before having finished.
Fig. 2 shows some bus signals of employed bus 200 in the bus matrix 120.For instance, bus can comprise common address and data-signal, and a plurality of control signal.Can comprise in the described control signal: a plurality of control signals as shown in the figure; A plurality of look-at-mes are used to define the different look-at-mes with different right of priority/grades; Signal specific is used to indicate park mode; And the mode signal that is associated, indication will enter the park mode of which kind of type.Which unit can comprise other indicates to enter the signal of corresponding park mode.Fig. 2 also shows the dedicated cpu clock signal that can be used in the system and the example of DMA clock signal separately, and wherein discrete cell can't individually be assigned different power modes.Other control signal that bottom control line indication is implemented in microprocessor or microcontroller usually.
Fig. 3 shows the embodiment of dma controller.A plurality of DMA passages 350 are provided ... 360, and described a plurality of DMA passage 350 ... 360 are controlled by control bus 340 (for example interrupt request control bus).DMA passage 350 ... 360 with bus 310 coupling to receive data and address.In particular, address decoder 320 receiver addresses 320, and itself and control corresponding register 330 compared, with control DMA transmit functional.Multiplexer 370 can be used for controlling respective channel 350 ... 360 output.Controller 380 control multiplexers 370, and therefore control through the data stream of subsequently bus matrix interface 390.Embodiment shown in Fig. 3 can be by corresponding look-at-me control.For instance, can use look-at-me to come initial transmission through respective channel.For this reason, each passage can be assigned corresponding interrupt level.Can use the subclass of interrupt level, and dma controller 125 can be programmable, some interrupt level is assigned to corresponding transmission passage.In addition, dma controller can be programmable, with finish, arrive in transmission in the transmission certain a bit (for example transmission of half of channel buffer), arrive the predefine point in the channel buffer or be matched with predefined data pattern to be transmitted after a plurality of look-at-mes of generation.Can implement other interrupt control signal.
Fig. 4 shows the more details of the embodiment of the passage in the dma controller 125.According to an embodiment, dma controller 125 can have Static Design, therefore and can receive its oneself DMA clock signal 490, it can be used for the directly different power mode of control, for example, and under high-power mode, described device will receive maximum clock speed, under lowest power mode, do not have any clock signal, and the middle power pattern can comprise various middle clock speeds.Dma controller 125 can comprise programmable door, its receive clock signal, and can after entering park mode, block clock signal, and after receiving the interruption wake-up signal, open described door.Dma controller 125 further comprises at least one data register or latch 410a and address register that is associated or latch 440a, 440b, its both and bus matrix 120 in reception bus 470 and transfer bus 480 couplings.It can be same person that Fig. 4 indicates reception bus 470 and transfer bus 480 by a dotted line, for example the bus shown in Fig. 2 200.Yet in another embodiment, dma controller 125 also can be configured to communicate by letter between two different bus.In this embodiment, receive bus 470 and can be (for example) bus 310 as shown in Figure 3, and transfer bus 480 can be another bus of the bus matrix interface 390 that is connected to as shown in Figure 3.The register or latch 410a and the 440a that are used for address and data, 440b and the coupling of these buses.Perhaps, can utilize independent register at transmission and reception.As shown in Figure 4 independent address register 440a and 440b are useful, because source address is normally different with destination-address.Data register 410a and transmission and/or receiving register 440a, 440b can further be coupled with comparer 420,450, with the coupling of specified data or address.
During the DMA data transmitted, dma controller 125 can be sent to the destination with the data that will start from the source start address and end at the specified quantitative of end address, source through programming, and described destination also starts from the destination start address and ends at the end address, destination.For this reason, for example, register 440a loads active start address, and register 440b is loaded with the destination start address.Dma controller 125 further receives the length or the end address, source of data block to be transmitted.If use the end address, source, so this address is carried among the corresponding registers 440c that is coupled with comparator unit 450.Perhaps, but the length of end address, application target ground or data block as indicated above is determined the end that transmits.In case carried out this exemplary initialization, suitable data just transmits and takes place.Dma controller 125 further can comprise another register 440d, and it can be used for defining specific intermediate address and has arrived certain any signal to be used to produce transmission.For this reason, the predeterminable address that has indication to transmit the mid point or arbitrary other point in the impact damper of impact damper of this register 440d.Comparator unit 450 can comprise one group of comparer, maybe can be configured to produce after more different content of registers independent signal.Can use comparator output signal to produce specific look-at-me.
The transmission of single bus is used in explaination hereinafter.Dma controller 125 places first address (being stored in the source start address among the register 440a) on the bus.This address can with the storer or any device of described bus coupling in.Then the data that are associated are sent among the data register 410a.In a later step, with storer 440a from described bus decoupling, and with the coupling of register 440b and described bus.Perhaps, if only use an address register, so this address register is loaded with the destination start address.Therefore, now destination-address is placed on the bus, thus addressing corresponding target ground, for example with storer or any device of described bus coupling.Then, the data that are stored among the register 410a are sent to this destination-address.Source address register 440a and destination-address register 440b are increased progressively, and repeat described process, till source address register 440a contains active end address.Can (for example) come this ending of detected transmission, the content of described comparer 450 compare address register 440a and register 440c by comparer 450.Can use register 440d to produce M signal, its indication has reached a certain state/time of transmission.
In addition, dma controller 125 allows transmission with good conditionsi, and it just stops described transmission in case received specific pattern (for example predefined data byte).For this reason, dma controller 125 comprises further pattern register 410b.After initialization, this register 410b is loaded with for example pattern such as specified byte.In case comparer 420 detects the coupling between the institute's loaded data and pattern register 410b among the register 410a, just produces corresponding signal 430, it has arrived the ending of transmission to dma controller 125 indications.In order to prevent endless transmission, can use address comparator 450 to define maximum the transmission in addition.
Therefore, the dma controller 125 according to this embodiment allows two kinds of dissimilar affairs usually.First affairs are defined as the regular length transmission, and it allows dma controller to transmit the data block that defines.Second affairs have open length, and its length is defined by specific pattern.For instance, the ending of transmission can be defined by special symbol.In addition, in another embodiment, symbol sebolic addressing can define the ending of transmission.Therefore, the more flexible definition to the transmission ending is possible.For instance, replace to use the sequence of two bytes for example carriage return (carriage return, CR) line feed (LF) sequence in single byte.For this reason, can provide a plurality of registers, its programming has corresponding sequence.Available maximum transfer length strengthens second transaction types, circulates to avoid endless transmission, and therefore provides extra security.
Fig. 5 shows another one exemplary embodiment of dma controller 125.In this embodiment, provide source-register 510 and destination-address register 520.In addition, length/maximum length register 530 and comparer 580 couplings, described comparer 580 can produce the end address and detect EndAddr.Comparer 580 other and counter 570 couplings.Pattern register 540 and another comparer 550 couplings, described comparer 550 also is coupled with data register 560, and described data register 560 receives and transmission suitable data D
InAnd D
OutComparer 550 produces signal Match, and it then can produce end of transmission signal EofTrans.As indicated by the respective element that makes with dashed lines, the comparer that a plurality of pattern register 540 can be provided and be associated.Can provide the respective logic between register and the comparer, to allow dissimilar transmission.For instance, Fig. 5 shows first controllable driver 585, and it receives the signal EndAddr from comparer 580.The first input coupling of the output of driver 585 and OR-gate 590.The signal Match that the second may command phase inverter 555 receives from comparer 550.The second input coupling of the output of driver 555 and OR-gate 590.Therefore, the output of OR-gate 590 provides end of transmission signal EofTrans.Can use this signal to come control data to transmit.In addition, this signal can be fed to power management block 175.
Perhaps, provide comparator unit 565, so that the content of source address register 510 or destination-address register 520 and the content of end address register 595 are compared, with direct generation end of transmission signal EoTrans.In another embodiment, provide offset register 545, its content is used for deducting skew from end address register 595, to produce independently early stage wake-up signal, as hereinafter explaining in more detail.As another alternative, use wake up address register 475 to replace offset register 545.In this embodiment, produce end of transmission signal EoTrans by source address register 510 or destination-address register 520 and end address register 595 are compared, and produce wake-up signal WakeUp by source address register 510 or destination-address register 520 are compared with wake up address register 575.
According to another embodiment, can provide the control register 515 of storing predetermined adopted programmable number n and the register 535 that serves as counter and the number of the performed transmission of dma controller is counted in addition.The content of above-mentioned two registers is compared by comparer 525, and the result is fed to power management block 175.Register 515 storages are by the Integer n of user by CPU 110 programmings.After being set to system in the park mode, make register 535 reset to DMA#=0.If during park mode, receive the DMA request, activate dma controller and DMA so again and transmit necessary related device.If transmission is finished, make so register 535 and therefore DMA# increase progressively.Comparer 525 compares the content of register 515 and 535, and the result is sent to power management block 175.If DMA#＞=n, power management block 175 produces wake-up signal so.Otherwise dma controller 125 is put back park mode, till next DMA request arrives.
Can under different mode, carry out the DMA transmission.Under first pattern, Control Driver 555 so that comparer 550 from OR-gate 590 decouplings, thereby produce constant logic low signal in second input of OR-gate 590, and Control Driver 585 is so that comparer 580 and OR-gate 590 couplings.Register 510 and 520 is loaded with corresponding source start address and destination start address.Register 530 is loaded with the length of data to be transmitted piece, and counter 570 reset-to-zeros.Then, can begin data transmits.For this reason, the data load of 510 addressing of register in register 560, and is written to the address of being contained in the register 520.Then, make register 510 and 520 increase progressively transmit the size of data.For instance, if data register is a byte wide register, register 510 and 520 increases progressively 1 so.If data register is 16 bit registers, register 510 and 520 increases progressively 2 so, and the rest may be inferred.Counter 570 correspondingly increases progressively.Comparer 580 compares the Counter Value and the register 530 of counter 570.Repeating data transmits, till the content match of Counter Value and register 530.If reach this coupling, the EndAddr signal becomes logic high so, and the output of OR-gate 590 will become height, thus indication end of transmission (EOT) EofTrans.Therefore, dma controller is stopped.
Under second pattern, Control Driver 585 so that comparer 580 from OR-gate 590 decouplings, thereby produce constant logic low signal in first input of OR-gate 590, and Control Driver 555 is so that comparer 550 and OR-gate 590 couplings.Under this pattern, source-register 510 and destination register 520 are loaded with corresponding start address once more.In addition, pattern register 540 is loaded with the predefine pattern.Begin DMA once more and transmit, and first data load that will be associated with source-register is in data register 560, and itself and pattern register 540 are compared.If mate, comparer 550 produces high signal in its output place so, and it causes the high signal of output place of OR-gate 590, and the indication end of transmission (EOT).Otherwise register 510 and 520 increases progressively, and transmits and continue, till the data of being transmitted and the coupling between the pattern register 540 take place.Under three-mode, activate driver 555 and 585 both, thereby make comparer 550 and 580 both be coupled with OR-gates 590.Under this pattern, register 510 and 520 is loaded with corresponding start address once more.In addition, maximum length value is loaded in the register 530, and pattern is loaded in the register 540.As indicated above, data transmit and take place.Yet end of transmission (EOT) is produced by comparer 550 or 580.
In CPU 110 work or be suspended or be in park mode, when dma controller 125 and corresponding peripheral unit be activity simultaneously, can carry out all DMA transfer modes.Then use power management block 175 to control further process.For this reason, also can be with the EofTrans signal forwarding to power management block 175.Power management block 175 can comprise relevant register, and it can be through programming to produce the wake-up signal that is sent to CPU 110 according to the number of DMA transmission as indicated above or according to passage, peripheral unit etc.Therefore, under programming mode (wherein CPU 110 must handle the data that specific DMA transmits immediately), be at CPU 110 under the situation of dormancy or park mode, power management block 175 will be waken CPU 110 up after corresponding D MA transmission is finished.If in case CPU 110 has finished its data processing and has been requested, CPU 110 just can and enter dormancy or park mode once more according to its further programming.Similarly, in case all transmission co-pending are all finished, just dma controller 125 is put back corresponding park mode.
In addition, as CPU 110 and dma controller 125 boths when being movable, dma controller 125 has the right of priority to any bus access usually.Therefore, when on bus, transmitting data, the CPU 110 same bus of access that is under an embargo, and therefore be stopped.For the peripheral unit that can be changed into the main device on the bus, situation also is like this.Yet allowing the current bus of being used by dma controller 125 of CPU or another peripheral access is important sometimes.In order to allow this access, dma controller can be programmed via register to suspend current transmission.For this reason, CPU 110 can be provided with the dedicated bit in the dma controller, and it will suspend its current transmission to dma controller 125 indication dma controllers 125, till CPU 110 resets corresponding positions.Replace the dedicated bit in use control register as indicated above, can use special-purpose control line to make dma controller suspend the current data transmission.In addition, priority scheme can be used, wherein each DMA passage and/or the DMA unit that is associated a certain priority can be assigned to.Halt signal can comprise certain priority.Therefore, will only suspend the passage that those are lower than described certain priority according to the request of CPU.
Therefore, after detecting halt signal, dma controller 125 is finished current data and is transmitted, and promptly uses the individual data of data register 410a/560 to transmit, and it began before the detection that suspends position/signal is finished.In another embodiment, before not finishing the data transmission that has begun, the described data of abort transmit.Finish or this transmission that has begun of abort after, dma controller suspends any further transmission, but the current state that keeps it to store.In other words, when dma controller is in park mode, keep all content of registers.If data transmit by abort, dma controller is reset to transmit abort corresponding state before can repeat the affairs of abort.During park mode, dma controller is removed any blocking-up to the bus that is used to transmit data.Under the situation of priority scheme, have only those to have and just can be done, and then dma controller switches in the park mode than the DMA affairs of suspending the high right of priority of right of priority.Therefore, allow CPU 110 or peripheral unit to have complete access now, and can transmit data necessary respective bus.After finishing corresponding transmission, CPU 110 can be by resetting corresponding positions in the control register or by deactivation control signal corresponding or the pause command that has lowest priority by transmission, DMA being discharged from park mode.This mechanism allows the more flexible control to the bus in the access system.Therefore, notice that CPU can controllable way make dma controller suspend the current transmission of blocking-up CPU so, and CPU or peripheral unit can be carried out necessary access if a certain program need cause CPU or peripheral unit immediately.
Fig. 6 A and Fig. 6 B show some control register of the passage that is used for dma controller 125.For instance, according to Fig. 6 A, register 600 DMACON are used to control the general utility functions of dma controller.Position 15 is used to activate dma controller 125 or deactivation dma controller 125.By this position, can enable or inactive dma module.Position 14 is used for " freezing " DMA during debugging (Debug) pattern when being set up, or allows the DMA during the debugging mode to transmit when not being set up.Position 13 is used for freezing the transmission during the park mode when being set up, and allows the transmission during the park mode when not being set up.Position 12 is used for the time-out of dynamically controlling dma controller 125 as indicated above.For this reason, position 12 can be set to " 1 " and transmit, and allow not ACCESS bus interruptedly of CPU to suspend DMA.When making position 12 when being reset to " 0 ", dma controller 125 normal runnings, it will give the right of priority that dma controller surpasses bus, thereby stop or any access of interrupts of CPU.But those have the DMA passage of the right of priority lower than pause command the priority mechanism automatic pause.Also can implement priority scheme via interrupt mechanism.
Register 610 CHXCON control individual channels X.Because each data transmission can be made up of a plurality of affairs, so can use position 0 to 1 CHPR[1:0] define the right of priority that is assigned to each passage.In this embodiment, dma controller 125 can have some passages, for example 4 or 8 passages.2 potential energies enough define 4 different right of priority.If more multipriority is necessary, so according to an embodiment, can enlarge bit field CHPR, so that the position of respective amount to be provided.Use priority assignment to determine to carry out the order of a plurality of channel transactions.For instance,, will carry out all affairs so, till producing EofTrans signal and data transmission at this passage and having finished at passage 0 if passage 0 has highest priority and all other passages have than low priority.If a plurality of passages have equal priority, controller will be to cycle through all passages of described right of priority so.Therefore, if passage 2 and passage 3 have equal priority and do not have more high priority, so after affairs at passage 2, controller switches to passage 3, to carry out affairs at this passage, and then switch back passage 2, the rest may be inferred, till all having finished at all affairs of these two passages.Transmit if having the channel request of higher-priority, and another passage that has than low priority has affairs co-pending, so described affairs will be finished before moving to the passage with higher-priority.
Figure 10 shows the example that the hyperchannel in have 8 passages system of (wherein passage 0,1,2 and 4 is for movable) transmits.Passage 0 is at first by asserting that its control corresponding line asks to transmit.T at this moment
1The place, no affairs are co-pending.Therefore, transmit affairs and begin next circulation, as indicated in the line " active tunnel: ", the passage of described line identification current active.During the transmission at passage 0, passage 4 requests transmit.Because comparing with passage 0, passage 4 has higher-priority, so at next of t cycling time
2The place, beginning is at the transmission affairs of passage 4.During the transmission at passage 4, passage 2 requests transmit.Because comparing with passage 4, passage 2 has higher-priority, so at next of t cycling time
3The place, beginning is at the transmission affairs of passage 2.When the sequential transfer transactions of carrying out at passage 2, be suspended at the transmission of passage 0 and 4.At time t
4The place is done at all transmission of passage 2, and controller recovers the transmission at the passage 4 that has highest priority at this moment.At time t
5The place, passage 1 request transmits, and wherein passage 1 has identical right of priority with passage 4.Therefore, controller will cycle through the transmission of passage 1 and passage 4 from now on, till its transmission has been finished or received higher priority request.In example shown in Figure 10,, finish at the transmission of passage 1 and 4 at time t6 place.Therefore, controller recovers next the transmission affairs at remaining channel 0.At any time, the pause command with a certain priority can be received by dma controller.Then, only allow those passages to carry out its affairs with higher-priority.In this way, can implement very flexibly to suspend mechanism in dma controller, it allows optionally to suspend some or all DMA passages.
Return register CHXCON, use position 4 to 5 ETMD[1:0 referring to Fig. 6 A] define operator scheme.For instance, can assign 4 kinds of different modes.Therefore, these positions allow to define three kinds of patterns that (for example) describes with respect to Fig. 5.
Return register CHXCON, use (for example) position 8 (with 9) ETWU to define when transmitting whether produce wake-up signal when having finished referring to Fig. 6 A.If corresponding position is set up, power management block 175 can (for example) receive this signal (as illustrated in fig. 5) from OR-gate 590 so, and produces corresponding wake-up signal at CPU 110.Routine as an alternative, bit field ETWU[1:0 as shown in Figure 6] can use with two or more positions, to define the interrupt level of in a single day having finished the look-at-me that will produce at the transmission of respective channel.In the case, for example, will use the output signal of OR-gate 590 to produce look-at-me.CPU 110 can just wake up under programming with the situation that is only receiving the interruption with a certain priority.In other words, during park mode, will cover some and interrupt than low priority.The method will allow the simple designs of arouse machine processed.The DMA transmission that is not intended to wake up CPU 110 will be assigned the right of priority of lower grade, will be assigned higher-priority to wake CPU 110 up and need CPU to handle the DMA transmission that institute transmits data.
Return A, position 16 to 26 CHOFFSET[8:0 referring to Fig. 6] the indication skew, to produce wake-up signal early than finishing of DMA transmission.For instance, in dma memory transmitted, each affairs needed a known time t1.If being used for the activationary time of CPU 110 postpones bit field CHOFFSET to be programmed for 25 so for 25xt1.Corresponding comparer 565 and register 545 can be provided, and destination-address is deducted described skew for it and actual source address compares, as indicated among Fig. 5.The result of described comparison is independent of end of transmission signal, and is fed to power management block 175.
Another register 620 DCHXECON that Fig. 6 B explanation can be implemented at each passage, it controls the interrupt function of each passage.For this reason, bit field CHAIRQ is defined in position 16 to 23, and it can the interrupt level programming.Be higher than the described abort that will cause respective channel to transmit through the interruption of programming grade.Bit field CHSIRQ is defined in position 8 to 15, and is used to define and will causes transmitting at the DMA of described passage the interrupt level of beginning.Position 7 CFORCE can be used for forcing DMA to transmit beginning when being set to " 1 ".Position 6 CABORT can be used for the specific transmission of abort when being set to " 1 ".It is functional that position 5 PATCEN can be used for that pattern match is set.Therefore, as indicated above when this position when being set to " 1 ", transmission will be after pattern match abort.
Fig. 6 B shows another register 630 CHXINT be used for controlling some function of interrupting controlled DMA system.This register can be used for the generation of some look-at-me and functional the programming.Position 23 CHSDIE enable the interruption when the indication channel source buffer is finished.Position 22 CHSHIE enable the interruption when in midair the indication channel source buffer (arrives the center of described impact damper).Position 21 CHDDIE enable the interruption when indication passage destination impact damper is finished.Position 20 CHDHIE enable the interruption when in midair indication passage destination impact damper (arrives the center of described impact damper).Position 19 CHBCIF are used to enable indicator dog and transmit the interruption of finishing.Position 18 CHCCIE are used to enable indicating member and transmit the interruption of finishing.Position 17 CHTAIE are used to enable the interruption at transmitting abort.Position 16 CHERIE are used to enable the interruption at the channel address mistake.Position 7 CHSDIF are interrupt flag bit that indication channel source buffer pointer has arrived the ending of described source impact damper.Position 6 CHSHIF are interrupt flag bit that indication channel source buffer pointer has arrived the mid point of described source impact damper.Position 5 CHDDIF are interrupt flag bit that indication passage destination buffer pointer has arrived the ending of described destination impact damper.Position 4 CHDHIF are interrupt flag bit that indication passage destination buffer pointer has arrived the mid point of described destination impact damper.Position 3 CHBCIF are the completed interrupt flag bit of indication block transfer.Position 2CHCCIF is that the indication unit transmits completed interrupt flag bit.Position 1 CHTAIF indicates to detect interrupt match CHAIRQ and DMA transmits the interrupt flag bit of abort.Position 0 CHERIF indicates the interrupt flag bit that detects the channel address mistake.In embodiment mentioned above, the unit transmits the byte number that is transmitted when describing transmission initial before the DMA passage has another incident of wait.Therefore, the unit transmits and comprises that a programmable number individual character transmits, and wherein each individual character transmits and can be made up of nearly 4 bytes in 32 systems.Block is transmitted the byte number be defined as when passage is activated to be transmitted.Described byte number can be the source size that can independently programme or the greater in the size of destination.Therefore, block transfer comprises that one or more unit transmit.
Figure 11 shows the embodiment of the system with CPU 110, dma controller 125, interruptable controller 155 and dedicated control signal (for example interrupt bus 1110, individual outage line 1120,1130 and 1140).In one embodiment, interrupt bus 1110 can be used for producing different look-at-mes, and is as indicated above.Interruptable controller 155 is used to control these interruptions.Yet in other embodiments, can for example using between dma controller 125 and CPU 110, interrupt line 1140 grades directly be connected.In addition, further individual interrupt signals 1120 and 1130 can be used and produced by interruptable controller 155.Yet, can implement interrupt bus 1110, for example use the single look-at-me that is fed to all unit and a plurality of control lines to indicate corresponding interrupt level.Such as (for example) above description, use a plurality of registers to allow control very neatly to comprise the system of CPU 110 and dma controller 125.According to an embodiment, the DMA passage will be sent to destination register with data from source-register under the situation that no CPU gets involved.Channel source buffer start address register defines the start address of source impact damper.Passage destination impact damper start address register defines the beginning of destination impact damper.Can use relevant register source of configuration impact damper and destination impact damper independently.The unit transmits can be by the software that corresponding position CFORCE is set or next initial by the interrupt event of coupling CHSIRQ interrupt level by programming.DMA is transmitted in when initial performance element is transmitted.According to an embodiment, passage keeps being activated, till the DMA passage has transmitted the greater in source impact damper or the destination impact damper.Each passage uses buffer pointer to follow the tracks of from the number of the word of source impact damper and the transmission of destination impact damper.When source or destination pointer are a half of buffer sizes, perhaps when source or destination counter arrive the ending of impact damper, can produce buffer interrupts.According to different embodiment, interruption can be controlled by interruptable controller 155, and can individually or by the dedicated interrupt bus that allows a plurality of priority manage.
As indicated above, the user also can suspend dma module 125 immediately by writing a time-out position SUS (seeing Fig. 6 A).This will make DMA suspend any further bus transaction immediately.Can implement this function and have complete bus access to allow CPU.When CPU need be to the control fully of bus for atomic instructions (atomic instruction) sequence (for example unlock sequences of non-volatile memory module), will suspend DMA usually.Can use CHEN position (seeing Fig. 6 A, register 610) to suspend individual channels.If DMA transmits well afoot, and the CHEN position is eliminated, and will finish current affairs so, and will suspend the further affairs on this passage.A CHEN is enabled in removing will can not influence channel pointer or transaction counter.When passage was suspended, the user can select to continue to receive for example incident such as abort interrupts by CHAED position (seeing Fig. 6 A, register 610) is set.As indicated above, also can use priority scheme individually to suspend some DMA passage.
Fig. 7 shows the process flow diagram of embodiment of park mode that has the system of dma controller according to an embodiment.In first step 710, deactivation may enter all unit that comprise CPU 110 of park mode, so that power consumption is reduced to minimum.In step 720, whether the dma controller inspection has received DMA and has transmitted request.If be subjected to drives interrupts, the poll to this request is unnecessary so, and routine will be used as the Interrupt Service Routine execution.Perhaps, dma controller also can be in park mode, and DMA transmits request or interruption will wake dma controller up.If necessary, in step 730, will activate all required unit of DMA transmission by corresponding wake-up signal.In step 740, beginning DMA transmits, and carries out first affairs.In step 750, whether dma controller inspection transmission is finished.If do not finish, routine is returned step 740 so, to carry out another affairs.If transmission is finished, after step 750, routine can be operated by different way so.
According to first embodiment, routine continues step 760a, wherein checks whether will wake CPU 110 up.If (for example) corresponding positions in the respective channel control register is set up, will in step 770, activate CPU 110 so.Otherwise, routine skips step 770.As to the substituting of step 760 and 770, can after finishing, transmission produce the look-at-me of interrupt level with previous appointment.
According to second embodiment, routine continues step 755, wherein increases progressively register DMA#.Then, in step 760b, whether check DMA#＞=n, to determine whether to wake CPU 110 up.If (for example) number of the transmission of being finished is lower than predetermined number n, will not activate CPU 110 so, and routine skips step 770.That yes is possible in the combination of above-mentioned determining step, and can implement according to required system design.
According to the 3rd embodiment, routine continues step 770c, and wherein all devices reenter its respective sleep mode that had entered before affairs begin.
Fig. 8 shows the process flow diagram of the embodiment of the initialization routine that is used for dma controller.In first step 810, make the decision of whether using pattern mode.If do not use, routine is branched off into step 820 so, wherein stores the source and destination way address.In step 830 subsequently, determine the length of transmission by end address or block length.Then routine finishes.If the use pattern mode, routine forwards step 840 to so, and source and destination wherein are set.Then in step 850, the maximum length of transmission is set randomly, and in step 860, the storage data stop pattern value.In step 870, pattern mode is set, and initialization routine finishes.
Fig. 9 shows that in more detail DMA transmits the process flow diagram of the embodiment of routine (for example step 740 to 750 of Fig. 7).Routine begins in step 910, in step 910, reads the source data under the start address.In step 920, these data are written to destination-address.In step 930, check the pattern match pattern that whether has been provided with.If be not provided with, increase progressively source address and destination-address so, and in step 960, the data length value of successively decreasing.In step 970, check whether the data length value is 0.If, transmit so and finish, if not, routine is returned step 910 so.If pattern mode is set up, routine is branched off into step 950 from step 930 so, checks wherein whether data mate described pattern.If coupling takes place, transmit so and finish.Otherwise routine continues step 940, and is as indicated above.
In a word, because CPU does not wake up during the DMA affairs, so processor need not extract instruction and needn't understand fully why it wakes up by consumed energy.As indicated above, described extraction consumed power when the access flash storer.When dma controller was waken up, program storage can keep outage, because not have execution from program storage with to the transmission of program storage.Therefore, have only those assemblies just can be activated, and can after affairs are finished, return dormancy DMA affairs necessity.And if necessary, dma controller can be through programming to be suspended.Can use corresponding positions in the general control register or priority scheme or signal to suspend whole dma module.Yet, also can suspend individual channels by designated lane control register or priority scheme.Therefore, if necessary, can be open to the access of bus to CPU.
Therefore, the present invention is very suitable for carrying out described target and realizes mentioned purpose and advantage, and wherein intrinsic other purpose and advantage.Though describe, describe and defined the present invention with reference to certain preferred embodiment of the present invention, described reference does not hint limitation of the present invention, and should not infer any this type of restriction.To expect that as those possessing an ordinary skill in the pertinent arts the present invention can allow considerable modification, change and equivalent on form and function.The preferred embodiments of the present invention of describing and describing are exemplary, and at large do not illustrate scope of the present invention.Therefore, only the invention is intended to limit, assert fully thereby all give equivalent in all respects by the spirit and scope of appended claims.
Claims (25)
1. system, it comprises:
At least one bus;
CPU (central processing unit) (CPU), itself and described bus are coupled;
Storer, itself and described bus are coupled;
Direct memory access (DMA) (DMA) controller, it has a plurality of DMA passages, and be independent of described CPU and operate and with the coupling of described bus, wherein be the described bus of access, described dma controller can be programmed under first pattern to have the right of priority that is better than described CPU, and can programme under second pattern, at least one DMA passage of described dma controller is suspended the described bus of access under described second pattern.
2. system according to claim 1, it further comprises control register, described control register and described dma controller coupling, and be used for described dma controller is programmed, described control register comprise and are used to be provided with described first or the position of second pattern.
3. system according to claim 1, wherein said first or second pattern can be by being fed to the control signal programming of described dma controller.
4. system according to claim 1, each in wherein said a plurality of DMA passages has the priority of being assigned.
5. system according to claim 1, wherein said dma controller comprises a channel control register at each passage.
6. system according to claim 5, wherein each channel control register comprises that control is enabled or the programmable bit of the described passage of stopping using.
7. system according to claim 4, wherein said first or second pattern can be by being fed to the control signal programming that comprises priority of described dma controller.
One kind be used for the bus of main device and direct memory access (DMA) (DMA) controller coupling on carry out the method for data transmission, described method comprises:
According to request, permit the described bus of described dma controller access to the DMA data transmission;
Described dma controller is programmed to suspend described DMA data transmission;
Permit the described bus of described main device access;
Carry out at least one bus access by described main device;
Described dma controller is programmed to recover described DMA data transmission.
9. method according to claim 8 is wherein carried out the described step that described dma controller is programmed by configurable register.
10. method according to claim 9 is wherein carried out the described step that described dma controller is programmed by the position in the setting and the described configurable register that resets.
11. method according to claim 8 is wherein carried out the described step that described dma controller is programmed by control signal being fed to described dma controller.
12. method according to claim 11 wherein produces described control signal according to the abnormal signal that is fed to described main device.
13. method according to claim 8 if the wherein data of the initial described data transmission of described dma controller transmission before initial time-out finishes described data so and transmits, and is then suspended the access of described dma controller.
14. method according to claim 8, wherein said main device is CPU (central processing unit) (CPU), and described programming step is carried out by described CPU.
15. method according to claim 8, wherein said main device is a peripheral unit, and described programming step is carried out by CPU (central processing unit).
16. a microcontroller, it comprises:
At least one bus;
CPU (central processing unit) (CPU), itself and described bus are coupled;
Storer, itself and described bus are coupled;
A plurality of peripheral units, itself and described bus are coupled;
Direct memory access (DMA) (DMA) controller, its be independent of described CPU and operate and with the coupling of described bus, wherein be the described bus of access, described dma controller can be programmed under first pattern to have the right of priority that is better than described CPU and described a plurality of peripheral units, and can programme under second pattern, described dma controller is suspended the described bus of access under described second pattern.
17. microcontroller according to claim 16, it further comprises control register, described control register and described dma controller coupling, and be used for described dma controller is programmed, described control register comprise and are used to be provided with described first or the position of second pattern.
18. microcontroller according to claim 16, wherein said first or second pattern can be by being fed to the control signal programming of described dma controller.
19. microcontroller according to claim 18 wherein produces described control signal according to the abnormal signal that is fed to described CPU (central processing unit).
20. microcontroller according to claim 16, wherein said dma controller comprise a plurality of DMA passages.
21. microcontroller according to claim 20, wherein said dma controller comprises a channel control register at each passage.
22. microcontroller according to claim 21, wherein each channel control register comprises that control is enabled or the programmable bit of the described passage of stopping using.
23. microcontroller according to claim 21, wherein each channel control register comprises the programmable bit field of the right of priority that is used for definite DMA passage.
24. one kind is used for main device with have the method for carrying out data transmission on the bus of dma controller coupling of a plurality of direct memory access (DMA) (DMA) passage, described method comprises:
Each assigned priority in described a plurality of DMA passages;
According to request, permit described dma controller and come the described bus of access with one in described a plurality of DMA passages to the DMA data transmission;
The pause command that will have priority is fed to described dma controller;
If the described priority in the described pause command is higher than the priority of the described DMA passage of the described bus of access of having the right, so
Make any DMA passage suspend the described bus of access with right of priority lower than the described priority in the described pause command;
If do not have other DMA passage described bus of access of having the right, so
Permit the described bus of described main device access;
Carry out at least one bus access by described main device;
To recover order and be fed to described dma controller to recover described DMA data transmission.
25. method according to claim 8, wherein said dma controller can be operated to cycle through a plurality of DMA channel transactions of the DMA passage with equal priority.
Applications Claiming Priority (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US87026706P | 2006-12-15 | 2006-12-15 | |
| US87029506P | 2006-12-15 | 2006-12-15 | |
| US60/870,295 | 2006-12-15 | ||
| US60/870,267 | 2006-12-15 | ||
| US11/928,132 US9141572B2 (en) | 2006-12-15 | 2007-10-30 | Direct memory access controller |
| US11/928,132 | 2007-10-30 | ||
| PCT/US2007/087592 WO2008076892A2 (en) | 2006-12-15 | 2007-12-14 | Direct memory access controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101558396A true CN101558396A (en) | 2009-10-14 |
| CN101558396B CN101558396B (en) | 2011-12-14 |
Family
ID=41175628
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Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4989113A (en) * | 1987-03-13 | 1991-01-29 | Texas Instruments Incorporated | Data processing device having direct memory access with improved transfer control |
| US5461266A (en) * | 1990-11-27 | 1995-10-24 | Hitachi, Ltd. | Power consumption control system |
| US5379381A (en) * | 1991-08-12 | 1995-01-03 | Stratus Computer, Inc. | System using separate transfer circuits for performing different transfer operations respectively and scanning I/O devices status upon absence of both operations |
| US5367639A (en) * | 1991-12-30 | 1994-11-22 | Sun Microsystems, Inc. | Method and apparatus for dynamic chaining of DMA operations without incurring race conditions |
| JPH05250305A (en) * | 1992-03-06 | 1993-09-28 | Mitsubishi Electric Corp | Data transfer control system |
| JP2996183B2 (en) * | 1996-08-16 | 1999-12-27 | 日本電気株式会社 | Data processing device with DMA function |
| JP3602293B2 (en) * | 1997-04-22 | 2004-12-15 | 株式会社ソニー・コンピュータエンタテインメント | Data transfer method and device |
-
2007
- 2007-12-14 CN CN2007800460130A patent/CN101558396B/en active Active
- 2007-12-14 CN CN2007800460427A patent/CN101558366B/en active Active
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Also Published As
| Publication number | Publication date |
|---|---|
| CN101558366A (en) | 2009-10-14 |
| CN101558396B (en) | 2011-12-14 |
| CN101558366B (en) | 2012-11-21 |
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