CN101557211B

CN101557211B - Time sequence signal source circuit

Info

Publication number: CN101557211B
Application number: CN 200910050470
Authority: CN
Inventors: 刘立明; 胡昌友; 文兴; 刘芳; 胡芝丽; 陈建红
Original assignee: XINMAO SEMICONDUCTOR CO Ltd SHANGHAI
Current assignee: XINMAO SEMICONDUCTOR CO Ltd SHANGHAI
Priority date: 2009-04-30
Filing date: 2009-04-30
Publication date: 2011-05-18
Anticipated expiration: 2029-04-30
Also published as: CN101557211A

Abstract

The invention discloses a time sequence signal source circuit. The circuit comprises a basic time sequence signal generating circuit, wherein the input end of the basic time sequence signal generatingcircuit is connected with a clock signal, while the output end is connected with a backward stage delay unit; the basic time sequence signal generating circuit comprises a delay unit; the delay unit comprises a resistance-capacitance unit, a first phase reverser and a second phase reverser; the input end of the first phase reverser is connected with a signal input end, the output end of the firstphase reverser is connected with one end of a resistor; the other end of the resistor is connected with grid electrodes of a plurality MOS tubes; the MOS tube comprises at least one PMOS tube and at least one NMOS tube; a source electrode and a drain electrode of the PMOS tube are connected with each other and are connected with a power supply externally; a source electrode and a drain electrode of the NMOS tube are connected with each other and are earthed; and the input end of the second phase reverser is connected with grid electrodes of a plurality of MOS tubes, and are earthed through a reset unit. The time sequence signal source circuit has the advantages of small usage of the phase reversers and better accuracy than the traditional time delay circuit.

Description

Time sequence signal source circuit

Technical field

The present invention relates to a kind of signal source circuit, sequential (timing) signal source circuit that especially adopts basic delay unit and logical block to form is used for the static synchronous random access memory of high speed etc.

Technical background

Static synchronous random access memory is with address signal, and input data signal and other control signals are triggered by clock synchronization, is loaded into memory inside, and a clock cycle carries out a read or write.

Static synchronous random access memory is usually by memory cell array, address decoder, and sense amplifier, precharge control circuit, input control, output control and other logical circuits part or the like are formed.

In a clock, precharge control, modules such as input and output control are worked it orderly, thereby are finished read/write operation by the sequencing control corresponding with its difference in a clock.

Fig. 1 and 2 has provided a kind of more common sequential source circuit and oscillogram thereof respectively, this circuit utilizes the inverter of some series connection to realize time-delay, but because inverter itself has inverter functionality, can not precisely control its delay function, the clock signal that produces is more single, multiple clock signal is provided if desired, also need a lot of accessory logic circuits, cause the expending of loaded down with trivial details and chip area of design, among Fig. 2, signal Td, T0, each time-delay Δ t that T1 realizes, Δ t1, Δ t2 are respectively by corresponding 2N+1 among Fig. 1,2N1,2N2 reverser combine and realize.And the Δ t that sort circuit produces has limitation, and Δ t can not be greater than half clock cycle, and this is to be limited to by the operation principle of sort circuit.

Summary of the invention

At the problems referred to above, the present invention proposes a kind of time sequence signal source circuit, at a high speed (in the design of f＞100Mhz), can provide output relatively accurately and various clock signal, and can easily and accurately change sequential relationship between the signal by option.

Time sequence signal source circuit of the present invention, described circuit comprises that a basic clock signal produces circuit, its input connects clock signal, output connects back level delay cell, it is characterized in that, described basic clock signal produces circuit and comprises a delay cell, described delay cell comprises a capacitor resistor unit, first, second inverter, the input of first inverter connects a signal input part, its output connects an end of a resistance, the other end of described resistance links to each other with the grid of some metal-oxide-semiconductors, described metal-oxide-semiconductor comprises at least one PMOS pipe and at least one NMOS pipe, the source electrode of wherein said PMOS pipe and drain electrode interconnection and external power supply, the source electrode of described NMOS pipe and drain electrode interconnection and ground connection, the input of second inverter links to each other with the grid of described some metal-oxide-semiconductors, and by a reset cell ground connection.

Reasonablely be, described time sequence signal source circuit further comprises: three, the 4th inverter and with door, the input of described the 3rd inverter connects a clock signal input part, clock signal after anti-phase is sent into the signal input part of described delay cell, the signal output part of described delay cell connects first input end described and door, described another input with door is connected the output of described the 4th inverter, and the input of described the 4th inverter connects the output of described the 3rd inverter.

Reasonablely be, described reset cell is connected with described signal input part, and described time sequence signal source circuit is the monolateral delay circuit of trailing edge.

Reasonablely be, described reset cell is connected with VSS, and described time sequence signal source circuit is bilateral delay circuit.

The present invention has simplification, with devices such as small number of logic gates and area and reach than traditional more accurate effect in clock signal source.

Description of drawings

Below, with reference to accompanying drawing, for those skilled in the art that, from detailed description of the present invention, above-mentioned and other purposes of the present invention, feature and advantage will be apparent.

Fig. 1 is a kind of existing sequential source circuit figure;

Fig. 2 is the oscillogram of Fig. 1 circuit;

Fig. 3 is the preferred embodiment of a kind of basic delay cell of the present invention;

Fig. 4 is a kind of timing sequence generating circuit structure chart of application drawing 3 among the present invention;

Fig. 5 is the oscillogram of Fig. 4 circuit.

Concrete working method

See also shown in the accompanying drawing 3, the delay time Δ t of the delay cell of using in the sequence circuit of the present invention is by resistance R and several mos capacitances N1, N2, and P1, the RC network that P2 (this embodiment only provides two NMOS, two PMOS) constitutes produces.Specifically, this delay cell comprises that the input of a RC unit 30, first inverter 31 and second inverter, 32, the first inverters 31 connects signal input part V _INIts output connects an end of resistance R, and the other end of resistance R links to each other with the grid of some metal-oxide-semiconductors, and the metal-oxide-semiconductor here comprises two PMOS pipe P1, P2, with NMOS pipe N1, N2, wherein P1, the source electrode of P2 and drain electrode interconnection and external power supply Vdd, the source electrode of N1 and N2 and drain electrode interconnection and ground connection Vgnd, the input of second inverter 32 links to each other with the grid of above-mentioned metal-oxide-semiconductor, and this input is by a RESET unit ground connection in addition.

On domain, can be by control PMOS pipe, the size that NMOS pipe and the selection connecting line (option) of resistance R are controlled mos capacitance C changes the size of Δ t.Here with RESET unit and signal input part V _INBe connected together, this delay unit circuit is the monolateral delay circuit of trailing edge.

Fig. 4 has provided a kind of timing sequence generating circuit of application drawing 3, specifically comprise, basic clock signal produces circuit 41, this circuit comprises the 3rd inverter 411, the 4th inverter 412, delay cell 410 and adder 413, the input of the 3rd inverter 411 connects a clock signal input part clk, clock signal after anti-phase is sent into the signal input part of delay cell 410, the signal output part of this delay cell connects the first input end of adder 413, another input of this adder 413 connects the output of the 4th inverter 412, the input of the 4th inverter 412 connects the output of the 3rd inverter 411, and this basic clock signal produces circuit 41 and produces a basic clock signal Td, the clock signal of continuous if desired multiple relation, continue to connect one-level level delay cell at this output that produces circuit, like this, can on the basis of basic clock signal Td, produce the clock signal of continuous multiple relation, T0, T1, T2 or the like ...Like this, the designer can select needed timing control signal as required, can also change Δ t by revising basic delay unit simultaneously.

This in addition structure also can be provided with the selection of selecting connecting line to change clock signal very easily in domain.

Novel sequential of the present invention source is than the structure of conventional inverter, has following advantage: first, negligible amounts, because the delay time of single inverter is less, if will produce bigger time-delay, need some inverter tandems to form, and the present invention is easier to control owing to be how many control time-delay length of MOS quantity by layout design; The second, more traditional delay circuit is more accurate, because the consistency of inverter is relatively poor, if realize certain time-delay, difficult with precise control, and the present invention is very good by the controllability of delay unit.

Among Fig. 4, the RESET unit is met VSS (logical zero or ground), the delay unit circuit of Xing Chenging produces bilateral inhibit signal like this.

The front provides the description to preferred embodiment, so that any technical staff in this area can use or utilize the present invention.Various modifications to these embodiment are conspicuous to those skilled in the art, can be applied to other embodiment to total principle described here and not use creativeness.Thereby, the embodiment shown in the present invention will be not limited to here, and the wide region of principle that should disclose and new feature according to meeting here.

Claims

1. time sequence signal source circuit, described circuit comprise that a basic clock signal produces circuit, and its input connects clock signal, and output connects back level delay cell, it is characterized in that,

Described basic clock signal produces circuit and comprises a delay cell, described delay cell comprises a capacitor resistor unit, first, second inverter, the input of first inverter connects a signal input part, its output connects an end of a resistance, the other end of described resistance links to each other with the grid of some metal-oxide-semiconductors, described metal-oxide-semiconductor comprises at least one PMOS pipe and at least one NMOS pipe, the source electrode of wherein said PMOS pipe and drain electrode interconnection and external power supply, the source electrode of described NMOS pipe and drain electrode interconnection and ground connection, the input of second inverter links to each other with the grid of described some metal-oxide-semiconductors, and by a reset cell ground connection;

Wherein, described basic clock signal generation circuit further comprises:

Three, the 4th inverter and with door, the input of described the 3rd inverter connects described clock signal, clock signal after anti-phase is sent into the signal input part of described delay cell, the output of second inverter is the signal output part of described delay cell, the signal output part of described delay cell connects first input end described and door, described another input with door is connected the output of described the 4th inverter, and the input of described the 4th inverter connects the output of described the 3rd inverter.

2. time sequence signal source circuit according to claim 1 is characterized in that,

Described reset cell is connected with described signal input part, and described time sequence signal source circuit is the monolateral delay circuit of trailing edge.

3. time sequence signal source circuit according to claim 1 is characterized in that,

Described reset cell is connected with logical zero or ground, and described time sequence signal source circuit is bilateral delay circuit.