CN101556953A - Semiconductor component and making method thereof - Google Patents
Semiconductor component and making method thereof Download PDFInfo
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- CN101556953A CN101556953A CNA2008100921720A CN200810092172A CN101556953A CN 101556953 A CN101556953 A CN 101556953A CN A2008100921720 A CNA2008100921720 A CN A2008100921720A CN 200810092172 A CN200810092172 A CN 200810092172A CN 101556953 A CN101556953 A CN 101556953A
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- semiconductor device
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- ditches
- irrigation canals
- semiconductor
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Abstract
The invention provides a semiconductor component and a making method thereof. The semiconductor component comprises an epitaxial layer arranged on a semiconductor substrate, a plurality of electronic components arranged on the epitaxial layer, and a ditch isolation structure arranged among the electronic components, wherein the ditch isolation structure comprises a ditch arranged in the epitaxial layer and the semiconductor substrate, an oxidation underlayer which is arranged in the ditch and covers the side wall and the bottom of the ditch, and a doped polycrystalline silicon layer filling the ditch. In addition, bias voltage of zero volt can also be applied to the doped polycrystalline silicon layer. The ditch isolation structure can effectively isolate electronic components or high-voltage components with different operation voltage.
Description
Technical field
The invention relates to semiconductor device, the semiconductor device that is particularly to have channel isolating structure with and manufacture method.
Background technology
In semiconductor technology now,, be that the circuit of controller, memory, low voltage operating and the power device of high voltage operation are integrated in the one chip in order to reach the operation of system-on-a-chip (single-chip system).Because the electronic device of different operating voltage need be provided on one chip simultaneously, for example therefore high voltage electric crystal device and low voltage complementary formula metal-oxide semiconductor (MOS) (CMOS) circuit devcie need to make the electronic device of an isolation structures with isolated different operating voltage on technology.
See also Fig. 1, it shows a kind of generalized section of isolation structures of known electronic device.On semiconductor silicon base 10, has an epitaxial layer (epitaxy layer) 12, in epitaxial layer 12, be provided with two electronic devices 14 and 16, isolation structures between electronic device 14 and 16 is isolated (junction isolation) 18 for connecing face, it is to utilize ion to implant mode admixture to be driven in (drive-in) and form, because the face that connects is isolated in and needs on the chip layout than large tracts of land, and its real shallow trench isolation has bigger error, therefore can make the size of required chip increase.
In addition, the isolation structures of the electronic device that another kind is known is the deep trenches isolation structures, and it is to form a deep trenches between two electronic devices, and inserts oxide or unadulterated polysilicon in deep trenches.Though utilize the deep trenches structure can reduce the shared area of isolation structures between the electronic device, and shallow trench isolation is comparatively accurate, yet, its isolated effect between the electronic device of different operating voltage can be subjected to the depth-to-width ratio of irrigation canals and ditches and the wherein dielectric constant influence of filler, can't be applicable to the electronic device of various different operating voltages, make that its range of application is narrower.
Therefore, industry is needed a kind of isolation structure of semiconductor device badly at present, to overcome above-mentioned shortcoming with not enough.
Summary of the invention
The invention provides a kind of semiconductor device, comprise that epitaxial layer is arranged at at semiconductor-based the end, a plurality of electronic devices are arranged on the epitaxial layer, interlayer dielectric layer is arranged on the electronic device, and channel isolating structure is arranged between those electronic devices, and wherein channel isolating structure comprises: irrigation canals and ditches were arranged in this epitaxial layer and this semiconductor-based end, and the oxidation lining is arranged in the irrigation canals and ditches, cover the sidewall and the bottom of irrigation canals and ditches, and doped polycrystalline silicon layer is filled up irrigation canals and ditches.
In addition, the invention provides a kind of manufacture method of semiconductor device, comprise: the semiconductor-based end is provided, form epitaxial layer on the semiconductor-based end, form a plurality of electronic devices on epitaxial layer, form interlayer dielectric layer and cover those electronic devices, and form channel isolating structure between those electronic devices, the step that wherein forms channel isolating structure comprises: with little shadow etching technics, form irrigation canals and ditches in interlayer dielectric layer, epitaxial layer and at semiconductor-based the end; Form the oxidation lining and cover the sidewall of irrigation canals and ditches and the surface of bottom and interlayer dielectric layer, the formation doped polycrystalline silicon layer is in the last of oxidation lining and fill up irrigation canals and ditches, and with chemical mechanical milling tech, remove a part of oxidation lining and doped polycrystalline silicon layer, until the surface that exposes interlayer dielectric layer.
Owing to fill the polysilicon that mixes in the irrigation canals and ditches isolation structures of the present invention, it can be used as electrode, when applying a bias voltage (bias voltage) on the polysilicon that mixes, can force equipotential line to walk around the irrigation canals and ditches isolation structures, therefore the electronic device for different operating voltage has preferable isolation effect, and also preferable for the isolated effect of high voltage device.
For allow above-mentioned purpose of the present invention, feature, and advantage can become apparent, below cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is known generalized section with semiconductor device of isolation structures;
Fig. 2 is the generalized section according to the semiconductor device with irrigation canals and ditches isolation structures of one embodiment of the invention;
Fig. 3 A to 3F is the generalized section according to the manufacture method of the irrigation canals and ditches isolation structures of one embodiment of the invention.
Drawing reference numeral
10, the 100～semiconductor-based end; 12,102～epitaxial layer;
14,16,104,106～electronic device; 18～the face that connects is isolated;
108～interlayer dielectric layer; 110～irrigation canals and ditches isolation structures;
112～irrigation canals and ditches; 114,124,126,128～oxidation lining;
The polysilicon of 116～doping; 120～photoresist layer;
122～opening.
Embodiment
See also Fig. 2, it shows the generalized section of semiconductor device of the present invention, on the semiconductor-based end 100, has an epitaxial layer 102, on epitaxial layer, form two electronic devices 104 and 106, this be with two electronic devices as embodiment with the explanation the present invention, be familiar with this skill personage when understanding, in semiconductor device, can comprise plural electronic device.Electronic device 104 can have different operating voltages with 106, perhaps has identical but higher operating voltage, it for example is drive integrated circult device (driver ICs), logical device (logic device), mixed mode device (mix mode device), two-carrier CMOS (Complementary Metal Oxide Semiconductor) diffusing metal dioxide semiconductor device (bipolar-CMOS-DMOS is called for short BCD), high voltage device (high-voltage device), smart-power IC (smart power ICs) or aforesaid combination.The detailed structure of electronic device is to have the form of knowing usually known to the knowledgeable in the affiliated technical field in graphic, indicates to simplify at this.
On electronic device 104 and 106, be coated with interlayer dielectric layer (interlayer dielectric, be called for short ILD) 108, with the protection electronic device and as the usefulness of insulation.Between electronic device 104 and 106, has irrigation canals and ditches isolation structures 110, irrigation canals and ditches isolation structures 110 comprises irrigation canals and ditches 112, sidewall and bottom capping oxidation lining 114 at irrigation canals and ditches 112, and the polysilicon 116 that has doping on oxidation lining 114 fills up irrigation canals and ditches 112, and the surface of the polysilicon 116 of oxidation lining 114 and doping and the apparent height of interlayer dielectric layer 108 trim.
In one embodiment, oxidation lining 114 can be the oxide layer of plural layer, for example is tetraethoxysilane (TEOS) oxide layer of plural layer, and the thickness of each layer can be different, are about
Extremely
Between, it is the difference that depends on the operating voltage of the size of irrigation canals and ditches and electronic device.In one embodiment, the polysilicon 116 of doping can be heavily doped N type (N
+) or heavily doped P type (P
+) polysilicon, wherein be preferably P
+Polysilicon.In one embodiment, irrigation canals and ditches 112 are deep trenches (deep trench), its width is about between 1 μ m to the 10 μ m, the degree of depth is about between 5 μ m to the 50 μ m, its depth-to-width ratio (aspect ratio) is about between 5: 1 to 15: 1, the width of irrigation canals and ditches 112 depends on the isolated effect that electronic device is required, and its degree of depth depends on the difference of the operating voltage of electronic device.
The polysilicon 116 that the invention is characterized in the doping of filling in the irrigation canals and ditches can be used as electrode, when applying a bias voltage (bias voltage) in the polysilicon that mixes, can force equipotential line (equipotentialline) to walk around irrigation canals and ditches, therefore can avoid producing between the electronic device of different operating voltage and interfere with each other, and can increase the isolated effect between the high voltage device, avoid leakage phenomenon to take place.In one embodiment, can apply on the polysilicon that is biased in doping of zero volt (0V).
See also Fig. 3 A to 3F, it shows the generalized section of the manufacture method of irrigation canals and ditches isolation structures of the present invention.As shown in Figure 3A, form epitaxial layer 102 on the surface at the semiconductor-based end 100, can form two electronic devices 104 and 106 as shown in Figure 2 on the epitaxial layer 102, for simplicity of illustration, those electronic devices are not drawn in Fig. 3 A to 3F.Then, on epitaxial layer 102, form interlayer dielectric layer (ILD) 108, cover the surface of entire semiconductor device.
See also Fig. 3 B, form the photoresist layer 120 with deep trenches pattern in interlayer dielectric layer (ILD) 108 tops, it is the width in order to the definition deep trenches.Utilize photoresist layer 120 as mask, etching is removed the exposed region of interlayer dielectric layer (ILD) 108, forms opening 122.
See also Fig. 3 C, utilize interlayer dielectric layer (ILD) 108 with opening as mask, etching is removed the epitaxial layer 102 and the semiconductor-based end 100 of opening 122 belows, forms deep trenches 112, and the width of deep trenches 112 for example is 2 μ m, and the degree of depth for example is 20 μ m.Then, see also Fig. 3 D, with sidewall and the bottom of Low Pressure Chemical Vapor Deposition (LPCVD) the deposition first oxidation lining 124 in deep trenches 112, and on the surface of interlayer dielectric layer 108, then, deposit the second and the 3rd oxidation lining 126 and 128 in regular turn with Low Pressure Chemical Vapor Deposition equally and cover the first oxidation lining 124.First, second and the 3rd oxidation lining can be tetraethoxysilane (TEOS) oxide layers, and its thickness for example is respectively
With
Utilize Low Pressure Chemical Vapor Deposition with the oxidation lining that repeatedly forms plural layer in the sidewall and the bottom of deep trenches 112, can reach preferable gradient coating performance, make oxidation lining film in the irrigation canals and ditches of high-aspect-ratio, reach uniform covering.
Then, see also Fig. 3 E, utilize chemical vapour deposition technique (CVD) depositing doped polycrystalline silicon 116, it is the surface of filling up deep trenches 112 and covering entire semiconductor device.Can use silicomethane (SiH
4) as reacting gas, and with helium (He) as carrier, doped with boron ion (B in deposition process
+), for example add diboron hexahydride (B
2H
6) in admixture of gas, form heavily doped P type (P
+) polysilicon membrane.
Then, see also Fig. 3 F, utilize chemical mechanical milling tech (CMP) that the polysilicon 116 and the oxidation lining 124,126 and 128 of the doping of part are removed, until the surface that exposes interlayer dielectric layer 108, make the surface of polysilicon of oxidation lining and doping and the apparent height of interlayer dielectric layer trim, finish irrigation canals and ditches isolation structures of the present invention.
Owing to fill the polysilicon that mixes in the irrigation canals and ditches isolation structures of the present invention, it can be used as electrode, when applying a bias voltage (bias voltage) on the polysilicon that mixes, can force equipotential line to walk around the irrigation canals and ditches isolation structures, therefore the electronic device for different operating voltage has preferable isolation effect, and also preferable for the isolated effect of high voltage device.Simultaneously, the size of irrigation canals and ditches isolation structures of the present invention can reduce, and be applicable to the electronic device of different operating voltage, its isolated effect can't be subjected to the dielectric constant influence of packing material in the irrigation canals and ditches, therefore its range of application is wider, applicable to the electronic device and the high voltage device of various different operating voltages.
Though the present invention has disclosed preferred embodiment as above; right its is not in order to qualification the present invention, any those who are familiar with this art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention attached claim before looking defines and is as the criterion.
Claims (11)
1. a semiconductor device is characterized in that, this device comprises:
The semiconductor substrate;
One epitaxial layer was arranged on this semiconductor-based end;
A plurality of electronic devices are arranged on this epitaxial layer; And
One channel isolating structure is arranged between those electronic devices, and wherein this channel isolating structure comprises:
One irrigation canals and ditches are arranged at described epitaxial layer and, have a sidewall and a bottom at described the semiconductor-based end;
One oxidation lining is arranged in these irrigation canals and ditches, covers described sidewall and described bottom; And
One doped polycrystalline silicon layer is filled up described irrigation canals and ditches.
2. semiconductor device as claimed in claim 1 is characterized in that, this semiconductor device comprises that more one zero volts bias voltage puts on the described doped polycrystalline silicon layer.
3. semiconductor device as claimed in claim 1 is characterized in that described irrigation canals and ditches comprise a deep trenches, and described deep trenches has a depth-to-width ratio between 5: 1 to 15: 1.
4. semiconductor device as claimed in claim 1 is characterized in that, described oxidation lining comprises the tetraethoxysilane oxide layer of plural layer.
5. semiconductor device as claimed in claim 1 is characterized in that, described doped polycrystalline silicon layer comprises the polysilicon of heavily doped N type or heavily doped P type.
6. semiconductor device as claimed in claim 1, it is characterized in that, described semiconductor device comprises that more an interlayer dielectric layer is arranged on the described epitaxial layer, covers more described electronic device, and the surface of wherein said channel isolating structure and the surface of described interlayer dielectric layer trim.
7. the manufacture method of a semiconductor device, this method comprises:
The semiconductor substrate is provided;
Form an epitaxial layer on the described semiconductor-based end;
Form a plurality of electronic devices on described epitaxial layer;
Form an interlayer dielectric layer on described epitaxial layer, and cover more described electronic device; And
Form a channel isolating structure between more described electronic device, the step that wherein forms described channel isolating structure comprises:
With little shadow etching technics, form irrigation canals and ditches in described interlayer dielectric layer, described epitaxial layer and at described the semiconductor-based end;
Form an oxidation lining, cover the sidewall and the bottom of described irrigation canals and ditches, and the surface of described interlayer dielectric layer;
Form a doped polycrystalline silicon layer on described oxidation lining, and fill up described irrigation canals and ditches; And
With chemical mechanical milling tech, remove a part of described oxidation lining and described doped polycrystalline silicon layer, until the surface that exposes described interlayer dielectric layer.
8. the manufacture method of semiconductor device as claimed in claim 7 is characterized in that, this manufacture method more comprises and applying on the described doped polycrystalline silicon layer of one zero volts be biased in.
9. the manufacture method of semiconductor device as claimed in claim 7 is characterized in that, described irrigation canals and ditches comprise a deep trenches, and described deep trenches has a depth-to-width ratio between 5: 1 to 15: 1.
10. the manufacture method of semiconductor device as claimed in claim 7 is characterized in that, the mode that forms described oxidation lining comprises Low Pressure Chemical Vapor Deposition, and described oxidation lining comprises the tetraethoxysilane oxide layer of plural layer.
11. the manufacture method of semiconductor device as claimed in claim 7 is characterized in that, the formation of described doped polycrystalline silicon layer comprises chemical vapour deposition technique, and described doped polycrystalline silicon layer comprises the polysilicon of heavily doped N type or heavily doped P type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100921720A CN101556953A (en) | 2008-04-10 | 2008-04-10 | Semiconductor component and making method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100921720A CN101556953A (en) | 2008-04-10 | 2008-04-10 | Semiconductor component and making method thereof |
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| Publication Number | Publication Date |
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| CN101556953A true CN101556953A (en) | 2009-10-14 |
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|---|---|---|---|
| CNA2008100921720A Pending CN101556953A (en) | 2008-04-10 | 2008-04-10 | Semiconductor component and making method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937918A (en) * | 2010-07-08 | 2011-01-05 | 芯巧科技股份有限公司 | Semiconductor structure and manufacture method thereof |
| CN105097851A (en) * | 2014-05-04 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | CMOS image sensor, manufacturing method thereof and electronic device |
| CN107275325A (en) * | 2016-04-08 | 2017-10-20 | 世界先进积体电路股份有限公司 | Protection device and operating system |
-
2008
- 2008-04-10 CN CNA2008100921720A patent/CN101556953A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101937918A (en) * | 2010-07-08 | 2011-01-05 | 芯巧科技股份有限公司 | Semiconductor structure and manufacture method thereof |
| CN105097851A (en) * | 2014-05-04 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | CMOS image sensor, manufacturing method thereof and electronic device |
| CN107275325A (en) * | 2016-04-08 | 2017-10-20 | 世界先进积体电路股份有限公司 | Protection device and operating system |
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Open date: 20091014 |