CN101556566B - Electronic device for detecting bidirectional bus competition and related method thereof - Google Patents
Electronic device for detecting bidirectional bus competition and related method thereof Download PDFInfo
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- CN101556566B CN101556566B CN2008100886515A CN200810088651A CN101556566B CN 101556566 B CN101556566 B CN 101556566B CN 2008100886515 A CN2008100886515 A CN 2008100886515A CN 200810088651 A CN200810088651 A CN 200810088651A CN 101556566 B CN101556566 B CN 101556566B
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Abstract
An electronic device for detecting bidirectional bus competition and a related method thereof are provided, wherein the electronic device comprises an output end, an input end, a data output unit, a comparison time schedule controller and a comparison unit. The output end outputs an output data signal to the bidirectional bus. The input terminal is coupled to the input terminal for receiving a reception data signal from the bidirectional bus. The data output unit provides the output data signal. The comparison time sequence controller is used for generating a comparison time sequence signal according to the output data signal. The comparing unit compares the received data signal with the output data signal according to the comparison timing signal to determine a bus contention state of the bidirectional bus.
Description
Technical field
The present invention relates to a kind of electronic installation and correlation technique thereof of testbus competition, particularly a kind of electronic installation and correlation technique thereof that is used for half-duplex bus testbus competition.
Background technology
Bus is a transmission interface, is used for transmitting the data between two or several electronic installations.In general, bus can be divided into unidirectional and two-way, and unidirectional bus only can transmit data to second end by the first end, can't transmit data to first end by the second end, and bidirectional bus allows first and second two ends to pass data mutually.For a chip component, the benefit of using bidirectional bus is than using unidirectional bus to need less stitch.
Please refer to Fig. 1, Fig. 1 is the functional block diagram of an existing master slave system 10.Master slave system 10 is carried out the data transmission between a main device 14 and the slave unit 16 through the bidirectional bus 12 of a half-duplex.Main device 14 comprises a forwarder 142 and a receiver 144, and slave unit 16 comprises a forwarder 162 and a receiver 164.Under normal operation, when forwarder 142 output one data-signal S1, receiver 164 receives and forwarder 162 must stop to transmit data; When forwarder 162 output one data-signal S2, receiver 144 receives and forwarder 142 must stop to transmit data.In brief, under normal transfer mechanism, bidirectional bus 12 only can allow that in the single time end device drives.Therefore; In order to drive bidirectional bus 12, main device 14 must be at war with (Contention) with slave unit 16, yet during competing in during the transition of transmission signal; Bidirectional bus 12 possibly driven or abandon simultaneously to drive by two end devices simultaneously, thereby causes 12 failures of driving bidirectional bus.For instance, data-signal S1 and data-signal S2 are if be transferred into bidirectional bus 12 simultaneously, and then the transition of two signals forms negative function, causes receiver 164 and receiver 144 to take defeat.
Summary of the invention
Therefore, the present invention provides a kind of electronic installation and correlation technique thereof that is used for two-way bus testbus competition, fails because of bus contention causes output data to bidirectional bus avoiding.
The present invention discloses a kind of electronic installation that is used for a two-way bus testbus competition, and it includes an output terminal, an input end, a data output unit, relatively a time schedule controller and a comparing unit.This output terminal is coupled to this bidirectional bus, is used for exporting an outputting data signals to this bidirectional bus.This input end is coupled to this input end and this bidirectional bus, is used for receiving data-signal from this bidirectional bus.This data output unit is used to provide this outputting data signals.This comparison time schedule controller is a delay cell preferably, is used for according to this outputting data signals, produces one and compares clock signal.This comparing unit is coupled to this input end, this data output unit and this comparison time schedule controller, is used for according to this comparison clock signal, relatively should receive data-signal and this outputting data signals, to judge the bus contention state of this bidirectional bus.
The present invention discloses a kind of method that is used for a two-way bus testbus competition in addition.This bidirectional bus transmits an outputting data signals or receives data-signal.This method is included in this bidirectional bus and transmits before this outputting data signals, according to this outputting data signals, produces one and compares clock signal; And, relatively should receive data-signal and this outputting data signals, to judge the collision status of this bidirectional bus according to this comparison clock signal.
The present invention discloses a kind of electronic installation that is used for a two-way bus testbus competition in addition, and it includes an output terminal, an input end, a data output unit, a timing generator, a sampling unit, a detection clock generator and a comparing unit.This output terminal is coupled to this bidirectional bus, is used for exporting an outputting data signals to this bidirectional bus.This input end is coupled to this input end and this bidirectional bus, is used for receiving data-signal from this bidirectional bus.This data output unit is used to provide this outputting data signals.This timing generator is coupled to this data output unit, is used for according to this outputting data signals, produces a timing signal.This sampling unit is coupled to this data output unit and this timing generator, is used for according to this timing signal, and this outputting data signals of taking a sample is to produce a sampled data.Detect clock generator and be coupled to this data output unit, be used for, produce one and detect clock signal according to this outputting data signals.This comparing unit is coupled to this input end, this sampling unit and this detection clock generator, is used for according to this detection clock signal, relatively should receive data-signal and this sampled data, to judge the bus contention state of this bidirectional bus.
The present invention discloses a kind of method that is used for a two-way bus testbus competition in addition.This bidirectional bus transmits an outputting data signals or receives data-signal.This method includes according to this outputting data signals, produces a timing signal; According to this timing signal, this outputting data signals of taking a sample is to produce a sampled data; When this outputting data signals transition, produce one and detect clock signal; And, relatively should receive data-signal and this sampled data, to judge the bus contention state of this bidirectional bus according to this detection clock signal.
Description of drawings
Fig. 1 is the functional block diagram of an existing master slave system.
Fig. 2 is the functional block diagram of first embodiment of the invention one electronic installation.
Fig. 3 is the functional block diagram according to Fig. 1 one flow process.
Fig. 4 is the waveform synoptic diagram of coherent signal in the electronic installation of embodiment of the invention Fig. 1.
Fig. 5 is the functional block diagram of second embodiment of the invention one electronic installation.
Fig. 6 is the waveform synoptic diagram of coherent signal in the electronic installation of embodiment of the invention Fig. 5.
Fig. 7 is the functional block diagram according to Fig. 5 one flow process 70.
The reference numeral explanation
10 master slave systems
12 bidirectional buses
14 main devices
16 slave units
142,162 forwarders
144,164 receivers
S1, S2 data-signal
20,50 electronic installations
22,24 two-way binding paths
OUT1, OUT2 output terminal
IN1, IN2 input end
200,202 output buffers
210,212 input buffers
220 clock generators
230 data decoder
240 data input cell
242,500 data output units
250 compare time schedule controller
260,540 comparing units
SRP, SRN receive data-signal
The CLK clock signal
SOP, SON outputting data signals
ST transition signal
SCT is clock signal relatively
T1 time delay
T2, T3 time
510 timing generators
520 sampling units
530 detect clock generator
S_SMTP, S_SMTN timing signal
SOP_SM, SON_SM sampled signal
S_DTP, S_DTN detect clock signal
30,70 flow processs
300,302,304,306,308,700,702,704,706,708,710 steps.
Embodiment
Please refer to Fig. 2, Fig. 2 is the functional block diagram of first embodiment of the invention one electronic installation 20.Electronic installation 20 is a subordinate (Slave) device; Be used to detect the two-way binding path 22 of a half-duplex bidirectional bus and 24 bus contention, it includes output terminal OUT1 and OUT2, input end IN1 and IN2, output buffer 200 and 202, input buffer 210 and 212, a clock generator 220, a data decoder 230, a data input cell 240, a data output unit 242, relatively a time schedule controller 250 and a comparing unit 260.Input end IN1 and IN2 are respectively from two- way binding path 22 and 24 receive data-signal SRP and SRN; And by input buffer 210 and 212 (being all a smith trigger) according to a plurality of preset signals level; Decision receives the signal level of data-signal SRP and SRN, to carry out change such as signal.No matter any reception or outputting data signals, two signals that transmitted on the two- way binding path 22 and 24 are complementary signal, and when promptly the data-signal of one " 0 " attitude was transmitted in a two-way binding path, the data-signal of an one state was then transmitted in another two-way binding path.By this characteristic, clock generator 220 can data-signal SRP and SRN carry out mutual exclusion or (Exclusive OR, logical operation XOR) is to produce the clock signal clk that includes, as the system clock of electronic installation 20 to receiving.Data decoder 230 decodes the instruction that includes that receives data-signal SRP and SRN according to clock signal clk.Back-end device (like central processing unit) is delivered in the instruction that data input cell 240 is solved data decoder 230 again.Data output unit 242 provides outputting data signals SOP and the SON from back-end device.Output buffer 200 and 202 is deposited outputting data signals SOP and SON respectively, and exports two- way binding path 22 and 24 to by output terminal OUT1 and OUT2.
For the testbus competition, when data output unit 242 carries out a signal transition at any signal of outputting data signals SOP and SON, produce a transition signal ST.Relatively time schedule controller 250 is preferably by delay cell realizations, and it is used for postponing transition signal ST, to produce a comparison clock signal SCT.Comparing unit 260 is according to comparing clock signal SCT; Relatively receive data-signal SRP and outputting data signals SOP respectively; And receive data-signal SRN and outputting data signals SON, to judge the bus contention state of two- way binding path 22 and 24, it judges that principle is following.When outputting data signals SOP exported two-way binding path 22 to, because output terminal OUT1 is coupled to input end IN1, therefore under the state that does not have collision, the reception data-signal SRP that comparing unit 260 is received can be identical with the waveform of outputting data signals SOP.On the contrary; Occurring under the case of collision; Change owing to the outputting data signals SOP on the two-way binding path 22 receives the influence of other end device driving to produce signal, so the reception data-signal SRP that comparing unit 260 is received can be different with the waveform of outputting data signals SOP.
Please refer to Fig. 3, Fig. 3 is the functional block diagram of the embodiment of the invention one flow process 30.Flow process 30 is implemented in the electronic installation 20, is used for detecting the bus contention in two-way binding path 22.By on can know that two-way binding path 22 is transmitted outputting data signals SOP or received data-signal SRP.Flow process 30 includes the following step:
Step 300: beginning.
Step 302: when outputting data signals SRP carries out a signal transition, produce transition signal ST.
Step 304: according to transition signal ST, produce relatively clock signal SCT, it falls behind this signal transition T1 one time delay.
Step 306:, relatively receive data-signal SRP and outputting data signals SOP, to judge the collision status in two-way binding path 22 according to comparing clock signal SCT.
Step 308: finish.
According to flow process 30; When outputting data signals SRP carries out the signal transition; The embodiment of the invention promptly produces transition signal ST; And produce the comparison clock signal SCT that a sequential lags behind transition signal ST T1 time delay in view of the above, compare with the logic state that receives data-signal SRP and outputting data signals SOP, and then judge collision status.Because flow process 30 is implemented in electronic installation 20, so detailed process please refer to preceding text, repeats no more at this.In addition, flow process 30 also is applicable to the bus contention that detects two-way binding path 24.
Please refer to Fig. 4, Fig. 4 is the waveform synoptic diagram of coherent signal in the first embodiment of the invention electronic installation 20.The waveform of coherent signal from top to bottom is outputting data signals SOP and SON, and clock signal clk.Clock signal clk system to outputting data signals SOP and SON carry out mutual exclusion or logical operation and get.Fig. 4 only explains notion of the present invention with the signal transition wherein of outputting data signals SOP.Can know by Fig. 4, when time T 2, outputting data signals SOP transition, and data output unit 244 produces transition signal ST.Behind time delay T1, relatively time schedule controller 250 produces relatively clock signal SCT to carry out signal relatively.Preferably, time delay, T1 was less than mistiming of two continuous signal transitions, that is the mistiming of time T 2 and T 3.
Therefore, can know that embodiment of the invention system detects the transition of outputting data signals earlier by above-mentioned explanation, and after transition one period time delay, relatively receive data-signal and outputting data signals again.
What pay special attention to is that the mode that clock signal SCT is compared in comparison time schedule controller 250 generations of Fig. 2 is not limited to category of the present invention only as the embodiment of the invention.Relatively time schedule controller 250 can carry out signal Processing according to the characteristic (like transition time, signal difference or the like) of outputting data signals or to outputting data signals, produces the comparison clock signal, with the comparison sequential of control comparing unit.
Please refer to Fig. 5, Fig. 5 is the functional block diagram of second embodiment of the invention one electronic installation 50.Electronic installation 50 is roughly identical with electronic installation 20, and both differences are to be used for the element of testbus competition, wherein, represent with same-sign that with electronic installation 20 components identical it has identical functions and operation, so do not give unnecessary details in addition.Electronic installation 50 also has the function of the bus contention that detects two- way binding path 22 and 24, and it includes output terminal OUT1 and OUT2, input end IN1 and IN2, output buffer 200 and 202, an input buffer 210 and 212, one clock generator 220, a data decoder 230, a data input cell 240, a data output unit 500, a timing generator 510, a sampling unit 520, detects a clock generator 530 and a comparing unit 540.
Data output unit 500 is used to provide outputting data signals SOP and SON gives timing generator 510, sampling unit 520 and detects clock generator 530.Timing generator 510 produces a timing signal S_SMTP according to the signal transition of outputting data signals SOP, reaches the signal transition according to outputting data signals SON, produces a timing signal S_SMTN.Sampling unit 520 is according to timing signal S_SMTP or S_SMTN, and take a sample respectively outputting data signals SOP or SON give comparing unit 540 to produce sampled signal SOP_SM or SON_SM.Detect clock generator 530 when outputting data signals SOP transition, produce one and detect clock signal S_DTP, or when outputting data signals SON transition, produce one and detect clock signal S_DTN.Comparing unit 540 relatively receives data-signal SRP and outputting data signals SOP_SM or receives data-signal SRN and outputting data signals SON_SM, to judge the bus contention state of two-way binding path 22 and 24 according to detecting clock signal S_DTP or S_DTN.In addition, note that in order correctly to compare operation at this; Comparing unit 540 can be ignored detection clock generator 530 when outputting data signals SOP and SON transition for the first time; The detection clock signal that is produced, certainly, such operation is merely one embodiment of the invention; The dealer also can detect clock signal in this and compare operation, so also without prejudice to spirit of the present invention.
Please refer to Fig. 6, Fig. 6 is the waveform synoptic diagram of coherent signal in the second embodiment of the invention electronic installation 50.The waveform of coherent signal from top to bottom is signal, timing signal S_SMTP or S_SMTN, sampled signal SOP_SM or the SON_SM of outputting data signals SOP and SON, output terminal OUT1 and OUT2 and detects clock signal S_DTP or S_DTN.Because the waveform after load effect, outputting data signals SOP and SON are exported via output buffer 200 and 202 is shown in the signal of output terminal OUT1 and OUT2.Coherent signal with two-way binding path 22 is an example, and when outputting data signals SOP transition, timing signal S_SMTP produces with sampled data signal SOP, and then produces sampled signal SOP_SM.On the other hand, during each outputting data signals SOP transition, detect clock signal S_DTP and produce to receive the comparison of data-signal SRP and sampled signal SOP_SM.In addition, as previously mentioned, the detection clock signal S_DTP/S_DTN that the present invention is produced in the time of can ignoring outputting data signals SOP and SON transition for the first time, so this two signal just is not illustrated among the figure in addition.
Identical ground, if it is identical with sampled signal SOP_SM to detect reception data-signal SRP this moment, so just representing should uncontested generation on the two-way binding path 22.
Can know that by Fig. 6 for the waveform of an output information of falling after rising number, what electronic installation 50 detected outputting data signals earlier rises edge (Rising Edge), takes a sample, and when falling edge (Falling Edge) by the time, relatively receives data-signal and sampled signal again.
Please refer to Fig. 7, Fig. 7 is the functional block diagram of the embodiment of the invention one flow process 70.Flow process 70 is implemented in the electronic installation 50, is used for detecting the bus contention in two-way binding path 22.By on can know that two-way binding path 22 is transmitted outputting data signals SOP or received data-signal SRP.Flow process 70 includes the following step:
Step 700: beginning.
Step 702:, produce timing signal S_SMTP according to the signal transition of outputting data signals SOP.
Step 704: according to timing signal S_SMTP, sampling outputting data signals SOP is to produce sampled data SOP_SM.
Step 706: when outputting data signals SOP transition, produce and detect clock signal S_DTP.
Step 708:, relatively receive data-signal SRP and sampled data SOP_SM, to judge the race condition in two-way binding path 22 according to detecting clock signal S_DTP.
Step 710: finish.
According to flow process 70, when outputting data signals SRP carried out a signal transition, the embodiment of the invention produced timing signal S_SMTP, and the outputting data signals SOP that takes a sample in view of the above, to produce sampled data SOP_SM.When next signal transition of this signal transition took place, the embodiment of the invention produced and detects clock signal S_DTP, receiving the comparison of data-signal SRP and sampled data SOP_SM, and then judged the bus contention state in two-way binding path 22.Because flow process 70 is implemented in electronic installation 50, so detailed process please refer to preceding text, repeats no more at this.In addition, flow process 70 also is applicable to the bus contention that detects two-way binding path 24.
In sum, first embodiment of the invention is one period time delay after each signal transition, the testbus competition; Second embodiment of the invention is when first transition of two continuous transitions, and the sampling output data and when second transition, is carried out signal relatively, competes with testbus.Therefore, the embodiment of the invention bus driver failure that can avoid causing because of bus contention.
The above is merely preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (22)
1. one kind is used for the electronic installation that a two-way bus testbus is competed, and includes:
One output terminal is coupled to this bidirectional bus, is used for exporting an outputting data signals to this bidirectional bus;
One input end is coupled to this output terminal and this bidirectional bus, is used for receiving data-signal;
One data output unit is used for when this outputting data signals carries out a signal transition, producing a transition signal;
One compares time schedule controller, is used for according to this transition signal, produces one and compares clock signal; And
One comparing unit is coupled to this input end, this data output unit and this comparison time schedule controller, is used for according to this comparison clock signal, relatively should receive data-signal and this outputting data signals, to judge the bus contention state of this bidirectional bus.
2. electronic installation as claimed in claim 1, it comprises an input buffer in addition, is coupled between this input end and this comparing unit, is used for determining the signal level of this reception data-signal according to a plurality of preset signals level.
3. electronic installation as claimed in claim 1, it comprises an output buffer in addition, is coupled between this output terminal and this data output unit, is used for depositing this outputting data signals.
4. electronic installation as claimed in claim 1, wherein, this comparison time schedule controller comprises a delay cell, is used for to postpone this transition signal a time delay, to produce relatively clock signal.
5. electronic installation as claimed in claim 4, wherein, this time delay is less than the mistiming between next signal transition of this signal transition and this signal transition.
6. electronic installation as claimed in claim 1, wherein, this bidirectional bus is the bidirectional bus of a half-duplex.
7. one kind is used for the method that a two-way bus testbus is competed, and this bidirectional bus transmits an outputting data signals or receives data-signal, and this method includes:
When this outputting data signals carries out a signal transition, produce a transition signal;
Before this bidirectional bus transmits this outputting data signals,, produce one and compare clock signal according to this transition signal; And
Compare clock signal according to this, relatively should receive data-signal and this outputting data signals, to judge the collision status of this bidirectional bus.
8. method as claimed in claim 7, it is included in addition according to this comparison clock signal and relatively before this reception data-signal and this outputting data signals, according to a plurality of preset signals level, determines the signal level of this reception data-signal.
9. method as claimed in claim 7, it is included in this bidirectional bus in addition and transmits before this outputting data signals, deposits this outputting data signals.
10. method as claimed in claim 7, wherein, before this bidirectional bus transmits this outputting data signals, to postpone this transition signal a time delay, to produce relatively clock signal.
11. method as claimed in claim 10, wherein, this time delay is less than the mistiming between next signal transition of this signal transition and this signal transition.
12. method as claimed in claim 7, wherein, this bidirectional bus is the bidirectional bus of a half-duplex.
13. an electronic installation that is used for a two-way bus testbus competition includes:
One output terminal is coupled to this bidirectional bus, is used for exporting an outputting data signals to this bidirectional bus;
One input end is coupled to this input end and this bidirectional bus, is used for receiving data-signal from this bidirectional bus;
One data output unit is used to provide this outputting data signals;
One timing generator is coupled to this data output unit, is used for a signal transition according to this outputting data signals, produces a timing signal;
One sampling unit is coupled to this data output unit and this timing generator, is used for according to this timing signal, and this outputting data signals of taking a sample is to produce a sampled data;
One detects clock generator, is coupled to this data output unit, is used for when this outputting data signals transition, produces one and detects clock signal; And
One comparing unit is coupled to this input end, this sampling unit and this detection clock generator, is used for according to this detection clock signal, relatively should receive data-signal and this sampled data, to judge the bus contention state of this bidirectional bus.
14. electronic installation as claimed in claim 13, it comprises an input buffer in addition, is coupled between this input end and this comparing unit, is used for determining the signal level of this reception data-signal according to a plurality of preset signals level.
15. electronic installation as claimed in claim 13, it comprises an output buffer in addition, is coupled between this output terminal and this data output unit, is used for depositing this outputting data signals.
16. electronic installation as claimed in claim 13, wherein, this comparing unit is ignored this detection clock generator when the transition for the first time of this outputting data signals, this detection clock signal that is produced.
17. electronic installation as claimed in claim 13, wherein, this bidirectional bus is the bidirectional bus of a half-duplex.
18. a method that is used for a two-way bus testbus competition, this bidirectional bus transmits an outputting data signals or receives data-signal, and this method includes:
Signal transition according to this outputting data signals produces a timing signal;
According to this timing signal, this outputting data signals of taking a sample is to produce a sampled data;
When this outputting data signals transition, produce one and detect clock signal; And
Detect clock signal according to this, relatively should receive data-signal and this sampled data, to judge the bus contention state of this bidirectional bus.
19. method as claimed in claim 18, it is included in addition according to this detection clock signal and relatively before this reception data-signal and this outputting data signals, according to a plurality of preset signals level, determines the signal level of this reception data-signal.
20. method as claimed in claim 18, it is included in this bidirectional bus in addition and transmits before this outputting data signals, deposits this outputting data signals.
21. method as claimed in claim 18, wherein, when this outputting data signals transition, the step that produces this detection clock signal includes:
Ignore this detection clock signal that when the transition for the first time of this outputting data signals, is produced.
22. method as claimed in claim 18, wherein, this bidirectional bus is the bidirectional bus of a half-duplex.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5319642A (en) * | 1991-04-26 | 1994-06-07 | Fuji Xerox Co., Ltd. | Method of communication using a two-way bus with contention detection |
| US6108663A (en) * | 1993-01-09 | 2000-08-22 | Compaq Computer Corporation | Autonomous relational database coprocessor |
| CN1389800A (en) * | 2001-06-04 | 2003-01-08 | 四零四科技股份有限公司 | Transmission direction change-over device and method |
| CN1828568A (en) * | 2005-03-03 | 2006-09-06 | 凌阳科技股份有限公司 | Method and device for solving transmission interface bi-directional signal conflict |
| CN101146121A (en) * | 2007-06-20 | 2008-03-19 | 中兴通讯股份有限公司 | Bus relay device |
-
2008
- 2008-04-10 CN CN2008100886515A patent/CN101556566B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5319642A (en) * | 1991-04-26 | 1994-06-07 | Fuji Xerox Co., Ltd. | Method of communication using a two-way bus with contention detection |
| US6108663A (en) * | 1993-01-09 | 2000-08-22 | Compaq Computer Corporation | Autonomous relational database coprocessor |
| CN1389800A (en) * | 2001-06-04 | 2003-01-08 | 四零四科技股份有限公司 | Transmission direction change-over device and method |
| CN1828568A (en) * | 2005-03-03 | 2006-09-06 | 凌阳科技股份有限公司 | Method and device for solving transmission interface bi-directional signal conflict |
| CN101146121A (en) * | 2007-06-20 | 2008-03-19 | 中兴通讯股份有限公司 | Bus relay device |
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