CN101552029A - Storage module and method storing same - Google Patents
Storage module and method storing same Download PDFInfo
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- CN101552029A CN101552029A CNA2008100911019A CN200810091101A CN101552029A CN 101552029 A CN101552029 A CN 101552029A CN A2008100911019 A CNA2008100911019 A CN A2008100911019A CN 200810091101 A CN200810091101 A CN 200810091101A CN 101552029 A CN101552029 A CN 101552029A
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Abstract
The invention provides a storage module which comprises a plurality of storage sub-modules and a plurality of groups of input pins, wherein each storage sub-module comprises a plurality of storage chips which are connected in series; in addition, the input pins are respectively coupled to the storage sub-modules and used for receiving a plurality of same input signals, wherein each group of input pins comprises a plurality of input pins used for transmitting the input signals to the corresponding storage sub-module.
Description
Technical field
The relevant a kind of memory module of the present invention refers to a kind of rising/fall time and the memory module of increase foundation/retention time and the method for this memory module of access that can improve input signal especially.
Background technology
With reference to figure 1, Fig. 1 is traditional dual inline memory modules (Dual In-line Memory Module, DIMM) synoptic diagram of 100.As shown in Figure 1, dual inline memory modules 100 includes eight memory chip 110_1～110_8, and wherein each memory chip all includes 29 input pins.In the operation of dual inline memory modules 100, as shown in Figure 1,29 input signals are to be produced by a controller 120, and input to memory chip 110_1 via input pin (not shown), transfer to memory chip 110_2 afterwards in proper order, 110_3,110_8, yet, the memory chip of rear end (110_7 for example, 110_8) can cause the rise time (rising time) of input signal and fall time (falling time) to increase, and cause the reduction of the Time Created (setup time) and the retention time (hold time) of input signal because of equivalent RLC (resistance/inductance/capacitance) the signal attenuation effect of front-end memory chip.With reference to figure 2, Fig. 2 is the eye pattern (eye pattern) of the input signal of memory chip 110_1～110_8 shown in Figure 1.As shown in Figure 2, get over the memory chip of rear end, its wide (eye width) W is also more little, especially the eye of last memory chip 110_8 is wide is 919 psecs (pico-second), eye wide (1057 psec) much smaller than memory chip 110_1, therefore for the memory chip of rear end, may be not enough and produce the situation of jitter and cause and be easy to generate mistake on the data interpretation in the Time Created of higher frequency signals (setup time).
Summary of the invention
Therefore one of purpose of the present invention is to provide a kind of rising/fall time and the memory module of foundation/retention time and the method for access memory module that can improve input signal, to solve the above problems.
According to one embodiment of the present of invention, it discloses a kind of memory module.This memory module includes a plurality of storer secondary modules and many group input pins, wherein each storer secondary module includes a plurality of memory chips and this a plurality of memory chip series connection, in addition, should be coupled to this a plurality of storer secondary modules respectively by many group input pins, in order to receive identical a plurality of input signals, each group input pin is in order to being sent in the corresponding storer secondary module by a plurality of input signals, and each group input pin includes two nineteens input pin, and this two nineteens input pin is used for receiving two clock signals respectively, 16 storage address input signals, three bank-address input signals, one chip select signal, one row address strobe (row address strobe) signal, one column address gating signal (column addressstrobe), one write-enable (write enable) signal, one internal interrupt resistance (on-die termination) signal, one clock enable signal (CKE), one calibrating signal (ZQ) and replacement (reset) signal.
According to another embodiment of the present invention, it discloses a kind of memory module.This memory module includes a plurality of storer secondary modules and many group input pins, wherein each storer secondary module includes a plurality of memory chips and this a plurality of memory chip series connection, in addition, should be coupled to this a plurality of storer secondary modules respectively by many group input pins, in order to receive identical a plurality of input signals, each group input pin is in order to being sent in the corresponding storer secondary module by a plurality of input signals, and each group input pin includes nineteen input pin at least, this at least nineteen input pin be used for receiving at least six row address signals respectively, at least five column address signals, delegation's address chip is selected signal, one column address chip select signal, two clock signals, one internal interrupt resistance signal, one clock enable signal, one calibrating signal and a reset signal.
According to another embodiment of the present invention, it discloses a kind of method of access memory module.This method includes: in this memory module a plurality of storer secondary modules are set, wherein each storer secondary module includes a plurality of memory chips and this a plurality of memory chip series connection; In this memory module many group input pins are set, in order to receive identical a plurality of input signals; And transmit these a plurality of input signals to corresponding storer secondary module, wherein these a plurality of input signals include two clock signals, 16 storage address input signals, three bank-address input signals, a chip select signal, a rwo address strobe signals, a column address gating signal, a write-enable signal, an internal interrupt resistance signal, a clock enable signal, a calibrating signal (CKE) and reset signals.
According to another embodiment of the present invention, it discloses a kind of method of access memory module.This method includes: in this memory module a plurality of storer secondary modules are set, wherein each storer secondary module includes a plurality of memory chips and this a plurality of memory chip series connection; In this memory module many group input pins are set, in order to receive identical a plurality of input signals; And transmit these a plurality of input signals to corresponding storer secondary module, wherein these a plurality of input signals include at least six row address signals, at least five column address signals, delegation's address chips are selected signal, a column address chip select signal, two clock signals, an internal interrupt resistance signal, a clock enable signal (CKE), a calibrating signal and reset signals.
According to the method for memory module provided by the present invention and access memory module, rising/fall time and the foundation/retention time that can improve input signal, and then the correctness of promoting data interpretation.
Description of drawings
Fig. 1 is the synoptic diagram of traditional dual inline memory modules.
Fig. 2 is the eye pattern of the input signal of memory chip shown in Figure 1.
Fig. 3 is the synoptic diagram of an embodiment of memory module of the present invention.
Fig. 4 is the synoptic diagram of another embodiment of memory module of the present invention.
Fig. 5 is the synoptic diagram of six row address signals of the embodiment of the invention.
Fig. 6 is the synoptic diagram of five column address signals of the embodiment of the invention.
[primary clustering symbol description]
| 100 | Biserial pin memory body module |
| 110_1～110_8、310_1～310_8、 410_1～410_8 | Memory |
| 300、400 | The memory body module |
| 302_1、302_2、402_1、402_2 | The memory body secondary module |
| 304_1、304_2、404_1、404_2 | The |
| 120、320、420 | Controller |
| RowAdr0、RowAdr1、RowAdr2、 RowAdr3、RowAdr4、RowAdr5、 | Row address signal |
| A0～A15 | The setting information of memory body address |
| BA0～BA3 | The setting information of data base address |
| CMD0～CMD3 | Recall the setting information of body control command |
| ColAdr0、ColAdr1、ColAdr2、 ColAdr3、ColAdr4 | Row address signal |
| WE | Write the activation input command |
| AP | The auto-precharge input command |
| BC4/BL8 | Burst interruption/burst-length input command |
Embodiment
With reference to figure 3, Fig. 3 is the synoptic diagram of an embodiment of memory module of the present invention.As shown in Figure 3, memory module 300 includes (but being not limited to) two storer secondary modules 302_1,302_2 and first, two groups of input pin 304_1,304_2, storer secondary module 302_1 wherein, 302_2 includes a plurality of memory chip 310_1～310_4 and 310_5～310_8 respectively, wherein each memory chip all includes 29 input pins, and memory chip 310_1～310_4 and memory chip 310_5～310_8 connect respectively, in addition, first, two groups of input pin 304_1,304_2 includes 29 input pins respectively, and first, two groups of input pin 304_1,304_2 is connected to memory chip 310_4 and 310_5 respectively.
In the operation of memory module 300, as shown in Figure 3, first group of input signal produced by a controller 320, and inputs among the memory chip 310_4 via first group of input pin 304_1, transfers to memory chip 310_3,310_2,310_1 afterwards in proper order; Similarly, second group of input signal also produced by controller 320, and inputs among the memory chip 310_5 via second group of input pin 304_2, transfers to memory chip 310_6,310_7,310_8 afterwards in proper order.First group of input signal and second group of input signal are identical signal, and first and second group input signal includes 29 input signals respectively, and wherein these 29 input signals are two clock signals, 16 storage address input signals, three bank-address input signals, a chip select signal, a rwo address strobe signals, a column address gating signal, a write-enable signal, a clock enable signal (CKE), internal interrupt resistance ODT (on-die termination) signal, a calibrating signal (ZQ) and reset signals (reset).
Compared to traditional dual inline memory modules 100, in one embodiment of the present of invention, each group input signal only can be sent to four memory chips in the memory module 300, measurement with traditional dual inline memory modules 100 shown in Figure 2 is an example, the memory chip 310_1 of the rearmost end in the memory module 300,310_8, the wide W of eye of its input signal is 1004 psecs, compared to the wide W of eye is the memory chip 110_8 of traditional dual inline memory modules 100 of 919 psecs, the present invention can improve the input signal quality of memory chip really, and reduces the chance of data interpretation mistake.
Be noted that, the quantity of above-mentioned storer secondary module and many group input pins only is one embodiment of the present of invention, on real the work, the quantity of storer secondary module and many group input pins can change to some extent according to considering of deviser, and the variations in these designs all are under the jurisdiction of category of the present invention.
Yet, though memory module 300 can be improved the quality of the received input signal of memory chip, but but need two groups of input signal pins, that is memory module 300 needs 58 input pins altogether, thus can be because of memory module (DIMM) circuit board (printed circuit board, limitation in height PCB) and increase the degree of difficulty of PCB wiring (Layout).Therefore, the present invention provides framework after a kind of improvement of memory module to solve the above problems in addition.With reference to figure 4, Fig. 4 is the synoptic diagram of another embodiment of memory module of the present invention.As shown in Figure 4, memory module 400 includes two storer secondary module 402_1,402_2 and first, two groups of input pin 404_1,404_2, storer secondary module 402_1 wherein, 402_2 includes a plurality of memory chip 410_1～410_4 and 410_5～410_8 respectively, wherein each memory chip all includes 19 input pins, and memory chip 410_1～410_4 and memory chip 410_5～410_8 connect respectively, in addition, first, two groups of input pin 404_1,404_2 includes 19 input pins respectively, and first, two groups of input pin 404_1,404_2 is connected to memory chip 410_4 and 410_5 respectively.In the present invention, these 19 input pins are respectively six row address signal pins, five column address signal pins, delegation's address chips and select signal pin, a column address chip select signal pin, two clock signal pins, internal interrupt resistance ODT (on-die termination) signal pin, clock enable signal (CKE) pin, a calibrating signal (ZQ) pin and a reset signal (reset) pins.
In the operation of memory module 400, as shown in Figure 4, first group of input signal produced by a controller 420, and inputs among the memory chip 410_4 via first group of input pin 404_1, transfers to memory chip 410_3,410_2,410_1 afterwards in proper order; Similarly, second group of input signal also is to be produced by controller 420, and input among the memory chip 410_5 via second group of input pin 404_2, transfer to memory chip 410_6 afterwards in proper order, 410_7,410_8, wherein first group of input signal and second group of input signal are identical signal, and first, two groups of input signals include 19 input signals respectively, and wherein these 19 input signals are six row address signals, five column address signals, delegation's address chip is selected signal, one column address chip select signal, two clock signals, one internal interrupt resistance ODT (on-die termination) signal, one clock enable signal (CKE), one calibrating signal (ZQ) and a reset signal (reset).
With reference to figure 5, Fig. 5 is the synoptic diagram of six row (row) address signal of the embodiment of the invention.As shown in Figure 5, (length of delegation's address command grouping (rowaddress command package) of RowAdr0～RowAdr5) is four clock period of a clock signal clk to each row address signal, and the row address command packet includes four capable input commands, therefore, six row address command packet of six row address signals include 24 capable input commands altogether, in the present embodiment, these 24 capable input commands include the set information BA0～BA3 of four bank-address, set information A0～the A15 of 16 storage addresss and the set information CMD0～CMD3 of four storer control commands, wherein the set information BA0～BA3 of four bank-address equals the bank-address input signal BA0～BA3 under traditional double data rate Synchronous Dynamic Random Access Memory framework, and the set information A0～A15 of 16 storage addresss equals the storage address input signal A0～A15 under traditional double data rate Synchronous Dynamic Random Access Memory framework.In addition, set information CMD0～the CMD3 of four storer control commands is via decoding to produce the control command in a plurality of storer control commands, wherein these a plurality of storer control commands can include startup (Active), precharge (Precharge), upgrade (Refresh), temporary (the mode register set) MRS that sets of pattern, self (self-refresh entry, SRE), enter low-power consumption (power down entry), long calibration/weak point calibration (ZQ calibration long/ZQ calibration short, ZQCL/ZQCS) or the like.
With reference to figure 6, Fig. 6 is the synoptic diagram of five row (column) address signal of the embodiment of the invention.As shown in Figure 6, (length of the column address command packet (columnaddress command package) of ColAdr0～ColAdr4) is four clock period of a clock signal clk to each column address signal, and the column address command packet includes four row input commands, therefore, five row address command packet of five column address signals include 20 row input commands altogether, these 20 row input commands include the set information of four bank-address, the set information of 13 storage addresss, one write-enable (Write Enable, WE) input command, one auto-precharge (Auto Pre-charge, AP) 4/ burst-length 8 (Burst Chop 4/Burst Length 8 is interrupted in an input command and a burst, BC4/BL8) input command, wherein the set information BA0～BA3 of four bank-address equals the bank-address input signal BA0～BA3 under traditional double data rate Synchronous Dynamic Random Access Memory framework, and the set information A0～A12 of 13 storage addresss equals the storage address input signal A0～A12 under traditional double data rate Synchronous Dynamic Random Access Memory framework.
Be noted that the input command that six row address command packet of six row address signals shown in Figure 5 are comprised respectively only as the usefulness of example explanation, on real the work, can exchange arbitrarily by 24 capable input commands shown in Figure 5; In like manner, storage operation of the present invention can be exchanged and not influence to 20 row input commands shown in Figure 6 also arbitrarily.In addition, the above line address signal (RowAdr0～RowAdr5), ((quantity of BA0～BA3) is also only as the usefulness of example explanation for the ColAdr0～ColAdr4) and the set information of bank-address for column address signal, on real the work, if want the capacity of extended storage, that is increase the set information of storage address or increase bank number, then row address signal can for seven or above and column address signal can for six or more than, for example, first, two groups of input signal pins can increase a row address signal pin and a column address signal pin, wherein the row address signal pin is used for receiving a row address signal RowAdr6, and the row address command packet of row address signal RowAdr6 includes the set information BA4 of two bank-address, BA5, and the set information A16 of two storage addresss, A17; And the column address signal pin is used for receiving a column address signal ColAdr5, and the column address command packet of column address signal ColAdr5 includes set information BA4, the BA5 of two bank-address, and set information A13, the A14 of two storage addresss.
In addition, the row address chip select signal is used for selecting to use a memory chip to receive this a plurality of row address signals, and the column address chip select signal is used for selecting to use a memory chip to receive this a plurality of column address signals, when row address chip select signal CSR or column address chip select signal CSC enabled, this memory chip just can receive row address signal or column address signal.
As mentioned above, each group input pin only includes 19 input pins in the memory module 400, therefore two groups of input pins have comprised 38 input signal pins altogether, 58 input pins compared to memory module shown in Figure 3 300, memory module 400 can be under the less input pin of needs, improve the input signal quality of memory chip simultaneously, and can under the limitation in height of memory module (DIMM) circuit board, promote the easness of wiring (Layout).
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (20)
1, a kind of memory module is characterized in that including:
A plurality of storer secondary modules, wherein each storer secondary module includes a plurality of memory chips and this a plurality of memory chip series connection; And
Many group input pins are coupled to this a plurality of storer secondary modules respectively, and in order to receive identical a plurality of input signals, wherein each group input pin includes a plurality of input pins, in order to being sent in the corresponding storer secondary module by a plurality of input signals.
2,, it is characterized in that these a plurality of storer secondary modules and should organize the quantity of importing pins more being two as claim 1 a described memory module.
3,, it is characterized in that each group input pin only is connected to a memory chip in the corresponding storer secondary module as claim 1 a described memory module.
4, as claim 1 a described memory module, it is characterized in that each group input pin includes two nineteens input pin, and this two nineteens input pin is used for receiving two clock signals, 16 storage address input signals, three bank-address input signals, a chip select signal, a rwo address strobe signals, a column address gating signal, a write-enable signal, an internal interrupt resistance signal, a clock enable signal, a calibrating signal and reset signals respectively.
5,, it is characterized in that these a plurality of input pins include as claim 1 a described memory module:
At least six row address signal pins, be used for receiving at least six row address signals, wherein the length of delegation's address command grouping of each row address signal is a plurality of clock period of a clock signal, and this row address command packet includes a plurality of capable input commands; And
At least five column address signal pins, be used for receiving at least five column address signals, wherein the length of a column address command packet of each column address signal is a plurality of clock period of this clock signal, and this column address command packet includes a plurality of row input commands.
6, as claim 5 a described memory module, the length that it is characterized in that this row address command packet and this column address command packet is four clock period, and this row address command packet and this column address command packet include four capable input commands.
7, as claim 6 a described memory module, it is characterized in that a plurality of capable input command at least six row address command packet that this a plurality of row address signal transmits includes the set information of the set information of at least four bank-address, 16 storage addresss and the set information of four storer control commands, and the set information of these four storer control commands is used for decoded to produce a storer control command.
8,, it is characterized in that a plurality of row input commands at least five column address command packet that this a plurality of column address signal transmits include the set information of at least four bank-address and the set information of 13 storage addresss as claim 7 a described memory module.
9,, it is characterized in that a plurality of row input commands at least five column address command packet that this a plurality of column address signal transmits include at least one write-enable input command, an auto-precharge input command and a burst interruption/burst-length input command as claim 8 a described memory module.
10,, it is characterized in that these a plurality of input pins include as claim 5 a described memory module:
Delegation's address chip is selected the signal pin, is used for receiving delegation's address chip and selects signal to select a using memory chip to receive this a plurality of row address signals;
One column address chip select signal pin is used for receiving a column address chip select signal to select a using memory chip to receive this a plurality of column address signals;
Two clock signal pins are used for receiving two clock signals respectively;
One internal interrupt resistance signal pin is used for receiving an internal interrupt resistance signal;
One clock enable signal pin is used for receiving a clock enable signal;
One internal interrupt resistance pin is used for receiving an internal interrupt resistance signal;
One calibrating signal pin is used for receiving a calibrating signal; And
One reset signal pin is used for receiving a reset signal.
11, a kind of method of access memory module is characterized in that including:
In this memory module a plurality of storer secondary modules are set, wherein each storer secondary module includes a plurality of memory chips and this a plurality of memory chip series connection;
In this memory module many group input pins are set, in order to receive identical a plurality of input signals; And
Transmit these a plurality of input signals to corresponding storer secondary module.
12,, it is characterized in that these a plurality of storer secondary modules and should organize the quantity of importing pins more being two as claim 11 a described access memory modular approach.
13, as claim 11 a described access memory modular approach, be characterised in that in addition to include:
At each storer secondary module, a plurality of input signals are inputed in the memory chip of this storer secondary module via corresponding group of input pin.
14, as claim 11 a described access memory modular approach, the number of signals that it is characterized in that these a plurality of input signals is 29, and this two nineteens input signal includes two clock signals, 16 storage address input signals, three bank-address input signals, a chip select signal, a rwo address strobe signals, a column address gating signal, a write-enable signal, a clock enable signal, an internal interrupt resistance signal, a calibrating signal and reset signals.
15,, it is characterized in that these a plurality of input signals include as claim 11 a described access memory modular approach:
At least six row address signals, wherein the length of delegation's address command grouping of each row address signal is a plurality of clock period of a clock signal, and this row address command packet includes a plurality of capable input commands; And
At least five column address signals, wherein the length of a column address command packet of each column address signal is a plurality of clock period of this clock signal, and this column address command packet includes a plurality of row input commands.
16, as claim 15 a described access memory modular approach, the length that it is characterized in that this row address command packet and this column address command packet is four clock period, and this row address command packet and this column address command packet include four capable input commands.
17, as claim 16 a described access memory modular approach, it is characterized in that a plurality of capable input command at least six row address command packet that this a plurality of row address signal transmits includes the set information of the set information of at least four bank-address, 16 storage addresss and the set information of four storer control commands, and the set information of these four storer control commands is used for decoded to produce a storer control command.
18,, it is characterized in that a plurality of row input commands at least five column address command packet that this a plurality of column address signal transmits include the set information of at least four bank-address and the set information of 13 storage addresss as claim 16 a described access memory modular approach.
19,, it is characterized in that a plurality of row input commands at least five column address command packet that this a plurality of column address signal transmits include at least one write-enable input command, an auto-precharge input command and a burst interruption/burst-length input command as claim 18 a described method.
20,, it is characterized in that these a plurality of input signals include as claim 15 a described access memory modular approach:
Delegation's address chip is selected signal, is used for selecting to use a memory chip to receive this a plurality of row address signals;
One column address chip select signal is used for selecting to use a memory chip to receive this a plurality of column address signals;
Two clock signals;
One internal interrupt resistance signal;
One clock enable signal;
One calibrating signal; And
One reset signal.
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|---|---|---|---|
| CNA2008100911019A CN101552029A (en) | 2008-04-02 | 2008-04-02 | Storage module and method storing same |
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| CNA2008100911019A CN101552029A (en) | 2008-04-02 | 2008-04-02 | Storage module and method storing same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106971751A (en) * | 2015-10-29 | 2017-07-21 | 三星电子株式会社 | Semiconductor devices and multi-chip package with chip id generative circuit |
| CN109410828A (en) * | 2018-11-29 | 2019-03-01 | 宗仁科技(平潭)有限公司 | LED point light source driving method, system and controller |
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2008
- 2008-04-02 CN CNA2008100911019A patent/CN101552029A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106971751A (en) * | 2015-10-29 | 2017-07-21 | 三星电子株式会社 | Semiconductor devices and multi-chip package with chip id generative circuit |
| CN106971751B (en) * | 2015-10-29 | 2021-07-13 | 三星电子株式会社 | Semiconductor device having chip ID generating circuit and multi-chip package |
| CN109410828A (en) * | 2018-11-29 | 2019-03-01 | 宗仁科技(平潭)有限公司 | LED point light source driving method, system and controller |
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Application publication date: 20091007 |