CN101546083B - Liquid crystal display - Google Patents

Liquid crystal display Download PDF

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Publication number
CN101546083B
CN101546083B CN2009101352401A CN200910135240A CN101546083B CN 101546083 B CN101546083 B CN 101546083B CN 2009101352401 A CN2009101352401 A CN 2009101352401A CN 200910135240 A CN200910135240 A CN 200910135240A CN 101546083 B CN101546083 B CN 101546083B
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pixel
npn
voltage
transistor
drain electrode
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CN101546083A (en
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林敬桓
林祥麟
许时嘉
刘圣超
刘匡祥
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AU Optronics Corp
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AU Optronics Corp
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Abstract

The invention discloses a liquid crystal display comprising a display panel and voltage supply device. The display panel comprises multiple scanning line, multiple data lines vertically installed with the multiple scanning lines, and multiple pixels which are separately electrically connected with corresponding data line and scanning line, and arranged in matrix style; each pixel comprises common wiring and compensated wiring, the common wiring is positioned in penetration area for receiving a common voltage; the compensation wiring is positioned in reflection area for receiving a stable voltage; the voltage supply device is coupled with compensation wiring of each pixel for continuously and correspondingly supply the stable voltage to each compensation wiring of each pixel.

Description

LCD
Technical field
The present invention relates to a kind of flat-panel screens, and particularly relevant for the semitransparent and half-reflective liquid crystal display of a kind of single bug hole spacing (singlecell gap).
Background technology
LCD roughly can be divided into penetration, reflective, and the semi-penetration, semi-reflective three major types.Wherein, Can use the semitransparent and half-reflective liquid crystal display (transflective LCD) of backlight and external light source to be fit to be applied to mobile phone (mobile phone), personal digital assistant (personaldigital assistant simultaneously; PDA) and on the e-book pocket electronic products such as (e-Book), therefore receive each side gradually and attract attention.
Generally speaking, semitransparent and half-reflective liquid crystal display can be divided into the semitransparent and half-reflective liquid crystal display of single bug hole spacing (single cellgap) and the semi-penetrated semi-reflected liquid crystal display two big classes of dual bug hole spacing (dual cell gap) again.Wherein, because that the semi-penetration semi-reflective of the semitransparent and half-reflective liquid crystal display of single bug hole spacing more dual bug hole spacing on making is penetrated the formula LCD is simple, and cost of manufacture is also lower.Therefore, the semitransparent and half-reflective liquid crystal display of single bug hole spacing becomes the application first-selection of all kinds of portable type electronic products immediately.
Yet; The greatest problem that semitransparent and half-reflective liquid crystal display faced of single now bug hole spacing be each pixel penetrating region the reflection gamma curve that penetrates gamma curve and echo area and do not match, and so will make single bug hole spacing semitransparent and half-reflective liquid crystal display penetrate display effect with the reflection display effect can't reach optimization simultaneously.
Summary of the invention
In view of this, the present invention provides a kind of semitransparent and half-reflective liquid crystal display of single bug hole spacing, and it penetrates display effect can reach optimization simultaneously with the reflection display effect.
The present invention provides a kind of LCD, and it comprises display panel and voltage supply device.Said display panel comprises multi-strip scanning line, many cardinal principles and the vertically disposed data line of said multi-strip scanning line, and a plurality of pixel.Said a plurality of pixel electrically connects with corresponding data line and sweep trace respectively, and arranges with matrix-style.Each pixel comprises shared distribution and compensation distribution, and wherein said shared distribution is used voltage altogether in order to receive; And said compensation distribution is in order to receive a burning voltage.Said voltage supply device couples the compensation distribution of each pixel, in order to continue and to supply the compensation distribution that said burning voltage is given each pixel accordingly.
The present invention continues to supply/apply the voltage folder of the echo area that mode that a burning voltage gives the compensation distribution of the echo area that is positioned at each pixel changes each pixel through voltage supply device poor; Adjust the reflection gamma curve of the echo area of each pixel whereby, and make it to mate with the gamma curve that penetrates of penetrating region.Thus, the semitransparent and half-reflective liquid crystal display of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
Will be appreciated that above-mentioned general description and following embodiment are merely exemplary and illustrative, it is not able to limit the scope that institute of the present invention desire is advocated.
Description of drawings
For letting above-mentioned and other purposes of the present invention, characteristic, advantage and the embodiment can be more obviously understandable, the detailed description of appended accompanying drawing be following:
Fig. 1 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's first example embodiment;
Fig. 2 A and Fig. 2 B illustrate the circuit diagram of the voltage feeding unit that is first example embodiment respectively;
Fig. 3 illustrates the time sequential routine figure of the voltage feeding unit that is first example embodiment;
Fig. 4 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's second example embodiment;
Fig. 5 illustrates the time sequential routine figure of the voltage feeding unit that is second example embodiment;
Fig. 6 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 3rd example embodiment;
Fig. 7 A and Fig. 7 B illustrate the circuit diagram of the voltage feeding unit that is the 3rd example embodiment respectively;
Fig. 8 illustrates the time sequential routine figure of the voltage feeding unit that is the 3rd example embodiment;
Fig. 9 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 4th example embodiment;
Figure 10 illustrates the time sequential routine figure of the voltage feeding unit that is the 4th example embodiment;
Figure 11 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 5th example embodiment;
Figure 12 A and Figure 12 B illustrate the circuit diagram of the voltage feeding unit that is the 5th example embodiment respectively;
Figure 13 illustrates the time sequential routine figure of the voltage feeding unit that is the 5th example embodiment;
Figure 14 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 6th example embodiment;
Figure 15 illustrates the time sequential routine figure of the voltage feeding unit that is the 6th example embodiment;
Figure 16 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 7th example embodiment;
Figure 17 A～Figure 17 D illustrates the circuit diagram of the voltage feeding unit that is the 7th example embodiment respectively;
Figure 18 A～Figure 18 B illustrates the time sequential routine figure of the voltage feeding unit that is the 7th example embodiment respectively;
Figure 19 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 8th example embodiment;
Figure 20 A and Figure 20 B illustrate the time sequential routine figure of the voltage feeding unit that is the 8th example embodiment respectively;
Figure 21 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 9th example embodiment;
Figure 22 A～Figure 22 D illustrates the circuit diagram of the voltage feeding unit that is the 9th example embodiment respectively;
Figure 23 A and Figure 23 B illustrate the time sequential routine figure of the voltage feeding unit that is the 9th example embodiment respectively;
Figure 24 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the tenth example embodiment;
Figure 25 A and Figure 25 B illustrate the time sequential routine figure of the voltage feeding unit that is the tenth example embodiment respectively;
Figure 26 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 11 example embodiment;
Figure 27 A～Figure 27 D illustrates the circuit diagram of the voltage feeding unit that is first example embodiment respectively;
Figure 28 A and Figure 28 B illustrate the time sequential routine figure of the voltage feeding unit that is the 11 example embodiment respectively;
Figure 29 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 12 example embodiment;
Figure 30 A and Figure 30 B illustrate the time sequential routine figure of the voltage feeding unit that is the 12 example embodiment respectively;
Figure 31 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 13 example embodiment;
Figure 32 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 14 example embodiment;
Figure 33 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 15 example embodiment;
Figure 34 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 16 example embodiment;
Figure 35 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 17 example embodiment;
Figure 36 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 18 example embodiment;
Figure 37 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 19 example embodiment;
Figure 38 A and Figure 38 B illustrate the time sequential routine figure of the voltage feeding unit that is the 19 example embodiment respectively;
Figure 39 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 20 example embodiment;
Figure 40 A and Figure 40 B illustrate the time sequential routine figure of the voltage feeding unit that is the 20 example embodiment respectively;
Figure 41 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 21 example embodiment;
Figure 42 A and Figure 42 B illustrate the time sequential routine figure of the voltage feeding unit that is the 21 example embodiment respectively;
Figure 43 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 22 example embodiment;
Figure 44 A and Figure 44 B illustrate the time sequential routine figure of the voltage feeding unit that is the 22 example embodiment respectively;
Figure 45 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 23 example embodiment;
Figure 46 A and Figure 46 B illustrate the time sequential routine figure of the voltage feeding unit that is the 23 example embodiment respectively;
Figure 47 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 24 example embodiment;
Figure 48 A and Figure 48 B illustrate the time sequential routine figure of the voltage feeding unit that is the 24 example embodiment respectively;
Figure 49 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 25 example embodiment;
Figure 50 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 26 example embodiment;
Figure 51 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 27 example embodiment;
Figure 52 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 28 example embodiment;
Figure 53 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 29 example embodiment;
Figure 54 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display of the single bug hole spacing of the present invention's the 30 example embodiment.
Wherein, Reference numeral
100,400,600,900,1100,1400,1600,1900,2100,2400,2600,2900,3100,3200,3300,3400,3500,3600,3700,3900,4100,4300,4500,4700,4900,5000,5100,5200,5300,5400: the semitransparent and half-reflective liquid crystal display of single bug hole spacing
101,401,1601,1901,3101,3201,3701,3901,4901,5001: display panel
103,603,1103: voltage supply device
1603,1605,2103,2105,2603,2605: sub-voltage supply device
103_1,103_2,603_1,603_2,1103_1,1103_2,1603_1,1603_2,1605_1,1605_2,2103_1,2103_2,2105_1,2105_2,2603_1,2603_2,2605_1,2605_2: voltage feeding unit
N 1～N 6: the N transistor npn npn
G1～G3: sweep trace
SS1～SS3: sweep signal
D1, D2: data line
AA: viewing area
P 11, P 12, P 21, P 22, P 31, P 32: pixel
CE 1: common electrode
CE 2: shared distribution
CE 3: auxiliary shared distribution
CL: compensation distribution
TA: penetrating region
Vcom: common voltage
RA: echo area
VS1, VS2, VS3, VS4: burning voltage
VS+: the burning voltage of positive polarity
VS-: the burning voltage of negative polarity
T: pixel transistor
C LC1, C LC2: liquid crystal capacitance
C ST, C ST1, C ST2: storage capacitors
C 1～C 4: electric capacity
CK, XCK, CK1, CK2, XCK2: clock signal
FP: during the picture
Embodiment
Existing with detailed reference several example embodiment of the present invention, the instance of said several example embodiment will be described in the accompanying drawings.In addition, all possibility parts use element/member of same numeral to represent identical or similar portions in accompanying drawing and embodiment.
[first example embodiment]
Fig. 1 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 100 of the single bug hole spacing of the present invention's first example embodiment.Please with reference to Fig. 1, the semitransparent and half-reflective liquid crystal display 100 of single bug hole spacing comprises display panel 101 and voltage supply device 103, and wherein display panel 101 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 100 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but first example embodiment only shows the parts relevant with the present invention.
Display panel 101 comprises multi-strip scanning line G2 and G3 (only showing 2 sweep traces conveniently to do explanation), many cardinal principles and sweep trace G2 and vertically disposed data line D1 of G3 and D2 (only showing 2 data lines conveniently to do explanation), and a plurality of pixel P that are positioned at the viewing area AA of display panel 101 21, P 22, P 31With P 32(only showing 4 pixels) conveniently to do explanation.
Pixel P 21, P 22, P 31With P 32Can electrically connect with corresponding data line and sweep trace respectively, and arrange with matrix-style.For instance, pixel P 21Electrically connect with data line D1 and sweep trace G2 respectively; Pixel P 22Electrically connect with data line D2 and sweep trace G2 respectively; Pixel P 31Electrically connect with data line D1 and sweep trace G3 respectively; And pixel P 32Electrically connect with data line D2 and sweep trace G3 respectively.In addition, pixel P 21Be expressed as the 1st pixel in the 2nd row pixel in the display panel 101; Pixel P 22Be expressed as the 2nd pixel in the 2nd row pixel in the display panel 101; Pixel P 31Be expressed as the 1st pixel in the 3rd row pixel in the display panel 101; And pixel P 32Be expressed as the 2nd pixel in the 3rd row pixel in the display panel 101.
Each pixel P 21, P 22, P 31With P 32Comprise shared distribution CE 2With compensation distribution CL.Shared distribution CE 2Be positioned at each pixel P for example 21, P 22, P 31With P 32Penetrating region TA in, in order to receive common voltage Vcom.Compensation distribution CL is positioned at each pixel P for example 21, P 22, P 31With P 32Echo area RA in, in order to receive and to transmit burning voltage VS1 and VS2 accordingly, in other words, each pixel P 21, P 22, P 31With P 32Compensation distribution CL transmits is burning voltage VS1 and VS2.In addition, each pixel P 21, P 22, P 31With P 32More comprise pixel transistor T, the first liquid crystal capacitance C LC1, storage capacitors C ST, first capacitor C 1, the second liquid crystal capacitance C LC2, and second capacitor C 2Because all pixel P 21, P 22, P 31With P 32Circuit structure with to couple relation all similar, so below only describe with single pixel.
With pixel P 21Be example, the grid of pixel transistor T couples sweep trace G2, and the source electrode of pixel transistor T then is coupled to data line D1.Generally speaking, the pixel electrode (pixel electrode) that electrically connects with the drain electrode of pixel transistor T with in order to receive the common electrode CE of common voltage Vcom 1Between can form the first liquid crystal capacitance C LC1, and with shared distribution CE 2Between can form storage capacitors C ST
The first liquid crystal capacitance C LC1First end couple the drain electrode of pixel transistor T, and the first liquid crystal capacitance C LC1Second end then be coupled to common electrode CE 1Storage capacitors C STFirst end couple the drain electrode of pixel transistor T, and storage capacitors C STSecond end then be coupled to shared distribution CE 2Wherein, pixel transistor T, the first liquid crystal capacitance C LC1And storage capacitors C STBe positioned at pixel P 21Penetrating region TA in.Though first embodiment is an example with the semitransparent and half-reflective liquid crystal display, yet does not limit to, main element configuration of the present invention can be applicable to penetrating LCD or reflective liquid-crystal display, in order to improve color offset phenomenon (color washout).In addition, the first liquid crystal capacitance C LC1With storage capacitors C STCommon voltage Vcom be not limited to identically, visual demand is adjusted into difference.
In addition, first capacitor C 1First end couple the drain electrode of pixel transistor T.The second liquid crystal capacitance C LC2First end couple first capacitor C 1Second end, and the second liquid crystal capacitance C LC2Second end then be coupled to common electrode CE 1Second capacitor C 2First end couple first capacitor C 1Second end, and second capacitor C 2Second end then be coupled to compensation distribution CL.Wherein, first capacitor C 1, the second liquid crystal capacitance C LC2And second capacitor C 2Be positioned at pixel P 21Echo area RA in.
In first example embodiment, voltage supply device 103 couples each pixel P 21, P 22, P 31With P 32Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to each pixel P 21, P 22, P 31With P 32Compensation distribution CL.
Clearer, voltage supply device 103 has a plurality of voltage feeding unit 103_1 and 103_2 (that is voltage feeding unit of each row pixel collocation).When the type of drive that adopts row counter-rotatings (row inversion) drives display panel 101; Then the 1st voltage feeding unit 103_1 can (for example be produced by time schedule controller according to first and second clock signal CK and the XCK of the 1st sweep signal SS1 (generally being produced by gate drivers) and phase differential 180 degree; But be not restricted to this), the burning voltage VS1 (that is VS-) of negative polarity gives each the pixel P in the 2nd row pixel and for example provide 21With P 22Compensation distribution CL.
In addition, the 2nd voltage feeding unit 103_2 can be according to first and second clock signal CK and the XCK of the 2nd sweep signal SS2 and phase differential 180 degree, and the burning voltage VS2 (that is VS+) of positive polarity gives each the pixel P in the 3rd row pixel and for example provide 31With P 32Compensation distribution CL.Wherein, first and second clock signal CK and the work period (duty cycle) of XCK are essentially (identical during the activation of sweep signal SS1 and SS2 usually) during the activation of sweep signal SS1 or SS2.
It is the voltage feeding unit 103_1 of first example embodiment and the circuit diagram of 103_2 that Fig. 2 A and Fig. 2 B illustrate respectively.Please merge with reference to Fig. 2 A and Fig. 2 B, voltage feeding unit 103_1 and 103_2 all comprise a N transistor npn npn N 1, the 3rd capacitor C 3, the 2nd N transistor npn npn N 2, the 3rd N transistor npn npn N 3, the 4th capacitor C 4, and the 4th N transistor npn npn N 4Because the circuit structure of voltage feeding unit 103_1 and 103_2 and the relation that couples are all similar, thus below only describe with single voltage feeding unit.
With voltage feeding unit 103_1 is example, a N transistor npn npn N 1Grid couple the 1st sweep trace G1 receiving sweep signal SS1, an and N transistor npn npn N 1Source electrode in order to receive the first clock signal CK.The 3rd capacitor C 3First end couple a N transistor npn npn N 1Drain electrode, and the 3rd capacitor C 3Second end then be coupled to shared distribution CE 2The 2nd N transistor npn npn N 2Grid couple a N transistor npn npn N 1Drain electrode, the 2nd N transistor npn npn N 2Source electrode in order to receiving the burning voltage VS+ of positive polarity, and the 2nd N transistor npn npn N 2Drain electrode then be coupled to each the pixel P in the 2nd row pixel 21With P 22Compensation distribution CL.Voltage feeding unit 103_2 can copy above-mentioned explanation to understand its element setting and receiving side signal formula, does not give unnecessary details at this.
The 3rd N transistor npn npn N 3Grid couple the 1st sweep trace G1 receiving sweep signal SS1, and the 3rd N transistor npn npn N 3Source electrode then in order to receive the second clock signal XCK.The 4th capacitor C 4First end couple the 3rd N transistor npn npn N 3Drain electrode, and the 4th capacitor C 4Second end then be coupled to common electrode CE 1The 4th N transistor npn npn N 4Grid couple the 3rd N transistor npn npn N 3Drain electrode, the 4th N transistor npn npn N 4Source electrode in order to receiving the burning voltage VS-of negative polarity, and the 4th N transistor npn npn N 4Drain electrode then be coupled to each the pixel P in the 2nd row pixel 21With P 22Compensation distribution CL.Though above-mentioned transistor N 1～N 4With the N transistor npn npn is example; But do not limit to; Viewable design changes to the P transistor npn npn, and assistant is to adjust its corresponding grid control signal and source electrode acknowledge(ment) signal, to reach function and the effect that voltage feeding unit 103_1 or voltage feeding unit 103_2 desire to provide.
Fig. 3 illustrates the time sequential routine figure of the voltage feeding unit 103_1 and the 103_2 that are first example embodiment.Please merge with reference to Fig. 1～Fig. 3, from Fig. 3, can know and find out, when sweep signal SS1 activation, the N transistor npn npn N in the voltage feeding unit 103_1 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK was in the state of forbidden energy, and the second clock signal XCK is in the state of activation.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 103_1 2Can be ended, and the 4th N transistor npn npn N 4Can be switched on.Thus, voltage feeding unit 103_1 promptly can provide the burning voltage VS1 (that is VS-) of negative polarity to give each the pixel P in the 2nd row pixel by FP (frame period) during a picture 21With P 22Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the N transistor npn npn N in the voltage feeding unit 103_2 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK was in the state of activation, and the second clock signal XCK is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 103_2 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 103_2 promptly can provide the burning voltage VS2 (that is VS+) of positive polarity to give each the pixel P in the 3rd row pixel by FP during same picture 31With P 32Compensation distribution CL.
Know based on above-mentioned, because voltage supply device 103 can continue and provide/apply a burning voltage VS1 and VS2 to being positioned at each pixel P accordingly 21, P 22, P 31With P 32Compensation distribution CL, so as to changing each pixel P 21, P 22, P 31With P 32The voltage folder of echo area RA poor, and then adjust each pixel P 21, P 22, P 31With P 32The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 100 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because voltage supply device 103 meetings are lasting and provide/apply a burning voltage VS1 and VS2 to being positioned at each pixel P accordingly 21, P 22, P 31With P 32Compensation distribution CL.Therefore, each pixel P 21, P 22, P 31With P 32The current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make whole cross-talk (cross-talk) phenomenons of semitransparent and half-reflective liquid crystal display 100 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[second example embodiment]
Fig. 4 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 400 of the single bug hole spacing of the present invention's second example embodiment.Please with reference to Fig. 4, the semitransparent and half-reflective liquid crystal display 400 of single bug hole spacing comprises single bug hole spacing display panel 401 and voltage supply device 103, and wherein display panel 401 is a display panels.Certainly; The semitransparent and half-reflective liquid crystal display 400 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but second example embodiment only shows the parts relevant with the present invention.
Display panel 401 comprises multi-strip scanning line G1 and G2 (only showing 2 sweep traces conveniently to do explanation), many cardinal principles and sweep trace G1 and vertically disposed data line D1 of G2 and D2 (only showing 2 data lines conveniently to do explanation), and a plurality of pixel P that are positioned at the viewing area AA of display panel 401 11, P 12, P 21With P 22(only showing 4 pixels) conveniently to do explanation.
Pixel P 11, P 12, P 21With P 22Can electrically connect with corresponding data line and sweep trace respectively, and arrange with matrix-style.For instance, pixel P 11Electrically connect with data line D1 and sweep trace G1 respectively; Pixel P 12Electrically connect with data line D2 and sweep trace G1 respectively; Pixel P 21Electrically connect with data line D1 and sweep trace G2 respectively; And pixel P 22Electrically connect with data line D2 and sweep trace G2 respectively.In addition, pixel P 11Be expressed as the 1st pixel in the 1st row pixel in the display panel 401; Pixel P 12Be expressed as the 2nd pixel in the 1st row pixel in the display panel 401; Pixel P 21Be expressed as the 1st pixel in the 2nd row pixel in the display panel 401; And pixel P 22Be expressed as the 2nd pixel in the 2nd row pixel in the display panel 401.
Each pixel P 11, P 12, P 21With P 22Comprise shared distribution CE 2With compensation distribution CL.Shared distribution CE 2Be positioned at each pixel P for example 11, P 12, P 21With P 22Penetrating region TA in, in order to receive common voltage Vcom.Compensation distribution CL is positioned at each pixel P for example 11, P 12, P 21With P 22Echo area RA in, in order to receive burning voltage VS1 and VS2 accordingly.In addition, each pixel P 11, P 12, P 21With P 22More comprise pixel transistor T, the first liquid crystal capacitance C LC1, storage capacitors C ST, first capacitor C 1, the second liquid crystal capacitance C LC2, and second capacitor C 2Because all pixel P 11, P 12, P 21With P 22Circuit structure with to couple relation all similar, so followingly only describe with single pixel.
With pixel P 11Be example, the grid of pixel transistor T couples sweep trace G1, and the source electrode of pixel transistor T then is coupled to data line D1.Generally speaking, the pixel electrode (pixel electrode) that electrically connects with the drain electrode of pixel transistor T with in order to receive the common electrode CE of common voltage Vcom 1Between can form the first liquid crystal capacitance C LC1, and with shared distribution CE 2Between can form storage capacitors C ST
The first liquid crystal capacitance C LC1First end couple the drain electrode of pixel transistor T, and the first liquid crystal capacitance C LC1Second end then be coupled to common electrode CE 1Storage capacitors C STFirst end couple the drain electrode of pixel transistor T, and storage capacitors C STSecond end then be coupled to shared distribution CE 2Wherein, pixel transistor T, the first liquid crystal capacitance C LC1And storage capacitors C STBe positioned at pixel P 11Penetrating region TA in.Though second embodiment is an example with the semitransparent and half-reflective liquid crystal display, yet does not limit to, main element configuration of the present invention can be applicable to penetrating LCD or reflective liquid-crystal display, in order to improve color offset phenomenon (color washout).In addition, the first liquid crystal capacitance C LC1With storage capacitors C STCommon voltage Vcom be not limited to identically, visual demand is adjusted into difference.
In addition, first capacitor C 1First end couple the drain electrode of pixel transistor T.The second liquid crystal capacitance C LC2First end couple first capacitor C 1Second end, and the second liquid crystal capacitance C LC2Second end then be coupled to common electrode CE 1Second capacitor C 2First end couple first capacitor C 1Second end, and second capacitor C 2Second end then be coupled to compensation distribution CL.Wherein, first capacitor C 1, the second liquid crystal capacitance C LC2And second capacitor C 2Be positioned at pixel P 11Echo area RA in.
In second example embodiment, voltage supply device 103 couples each pixel P 11, P 12, P 21With P 22Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to each pixel P 11, P 12, P 21With P 22Compensation distribution CL.
Clearer, voltage supply device 103 has a plurality of voltage feeding unit 103_1 and 103_2 (that is voltage feeding unit of each row pixel collocation).When the type of drive that adopts row counter-rotatings (row inversion) drives display panel 401; Then the 1st voltage feeding unit 103_1 can (for example be produced by time schedule controller according to first and second clock signal CK and the XCK of the 1st sweep signal SS1 (generally being produced by gate drivers) and phase differential 180 degree; But be not restricted to this), the burning voltage VS1 (that is VS+) of positive polarity gives each the pixel P in the 1st row pixel and for example provide 11With P 12Compensation distribution CL.
In addition, the 2nd voltage feeding unit 103_2 can be according to first and second clock signal CK and the XCK of the 2nd sweep signal SS2 and phase differential 180 degree, and the burning voltage VS2 (that is VS-) of negative polarity gives each the pixel P in the 2nd row pixel and for example provide 21With P 22Compensation distribution CL.Wherein, first and second clock signal CK and the work period (duty cycle) of XCK are essentially (identical during the activation of sweep signal SS1 and SS2 usually) during the activation of sweep signal SS1 or SS2.
In second example embodiment, voltage feeding unit 103_1 is identical with first example embodiment with the circuit structure of 103_2, so also no longer give unnecessary details it at this.
In addition, Fig. 5 illustrates the time sequential routine figure of the voltage feeding unit 103_1 and the 103_2 that are second example embodiment.Please merge with reference to Fig. 2 A, Fig. 2 B, Fig. 4 and Fig. 5, from Fig. 5, can know and find out, when sweep signal SS1 activation, a N transistor npn npn N1 and the 3rd N transistor npn npn N in the voltage feeding unit 103_1 3Can be switched on.Because this moment, the first clock signal CK was in the state of activation, and the second clock signal XCK is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 103_1 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 103_1 promptly can provide the burning voltage VS1 (that is VS+) of positive polarity to give each the pixel P in the 1st row pixel by (frame period) FP during a picture 11With P 12Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the N transistor npn npn N in the voltage feeding unit 103_2 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK was in the state of forbidden energy, and the second clock signal XCK is in the state of activation.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 103_2 2Can be ended, and the 4th N transistor npn npn N 4Can be switched on.Thus, voltage feeding unit 103_2 promptly can provide the burning voltage VS2 (that is VS-) of negative polarity to give each the pixel P in the 2nd row pixel by FP during same picture 21With P 22Compensation distribution CL.
Know based on above-mentioned, because voltage supply device 103 can continue and provide/apply a burning voltage VS1 and VS2 to being positioned at each pixel P accordingly 11, P 12, P 21With P 22Compensation distribution CL, so as to changing each pixel P 11, P 12, P 21With P 22The voltage folder of echo area RA poor, and then adjust each pixel P 11, P 12, P 21With P 22The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 400 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because voltage supply device 103 meetings are lasting and provide/apply a burning voltage VS1 and VS2 to being positioned at each pixel P accordingly 11, P 12, P 21With P 22Compensation distribution CL.Therefore, each pixel P 11, P 12, P 21With P 22Echo area RA in the current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 400 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[the 3rd example embodiment]
Fig. 6 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 600 of the single bug hole spacing of the present invention's the 3rd example embodiment.Please with reference to Fig. 6, the semitransparent and half-reflective liquid crystal display 600 of single bug hole spacing comprises single bug hole spacing display panel 101 and voltage supply device 603, and wherein display panel 101 is a display panels.Certainly; The semitransparent and half-reflective liquid crystal display 600 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 3rd example embodiment only shows the parts relevant with the present invention.
In the 3rd example embodiment, the structure of display panel 101 is identical with first example embodiment, so also no longer give unnecessary details it at this.In addition, voltage supply device 603 couples each pixel P 21, P 22, P 31With P 32Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to each pixel P 21, P 22, P 31With P 32Compensation distribution CL.
Clearer, voltage supply device 603 has a plurality of voltage feeding unit 603_1 and 603_2 (that is voltage feeding unit of each row pixel collocation).When the type of drive that adopts row counter-rotatings (row inversion) drives display panel 101; Then the 1st voltage feeding unit 603_1 can (for example be produced by time schedule controller according to the 1st sweep signal SS1 (generally being produced by gate drivers) and first and second clock signal CK1 and CK2; But be not restricted to this), the burning voltage VS1 (that is VS+) of positive polarity gives each the pixel P in the 2nd row pixel and for example provide 21With P 22Compensation distribution CL.
In addition, the 2nd voltage feeding unit 6032 can be according to the 2nd sweep signal SS2 and first and second clock signal CK1 and CK2, and the burning voltage VS2 (that is VS-) of negative polarity gives each the pixel P in the 3rd row pixel and for example provide 31With P 32Compensation distribution CL.Wherein, the work period of the first clock signal CK1 be essentially the activation of sweep signal SS1 or SS2 during (identical during the activation of sweep signal SS1 and SS2 usually), the second clock signal CK2 then continues to maintain the state of activation.
It is the voltage feeding unit 603_1 of the 3rd example embodiment and the circuit diagram of 603_2 that Fig. 7 A and Fig. 7 B illustrate respectively.Please merge with reference to Fig. 7 A and Fig. 7 B, voltage feeding unit 703-1 and 703-2 all comprise a N transistor npn npn N 1, the 2nd N transistor npn npn N 2, the 3rd capacitor C 3, the 3rd N transistor npn npn N 3, the 4th N transistor npn npn N 4, and the 5th N transistor npn npn N 5Because the circuit structure of voltage feeding unit 603_1 and 603_2 and the relation that couples are all similar, thus below only describe with single voltage feeding unit.
With voltage feeding unit 603_1 is example, a N transistor npn npn N 1Grid be coupled in source electrode, to receive the second clock signal CK2.The 2nd N transistor npn npn N 2Grid couple a N transistor npn npn N 1Drain electrode, the 2nd N transistor npn npn N 2Source electrode in order to receiving the burning voltage VS+ of positive polarity, and the 2nd N transistor npn npn N 2Drain electrode then be coupled to each the pixel P in the 2nd row pixel 21With P 22Compensation distribution CL.The 3rd N transistor npn npn N 3Grid couple the 1st sweep trace G1 receiving sweep signal SS1, and the 3rd N transistor npn npn N 3Source electrode then in order to receive the first clock signal CK1.
The 3rd capacitor C 3First end couple the 3rd N transistor npn npn N 3Drain electrode, and the 3rd capacitor C 3Second end then be coupled to shared distribution CE 2The 4th N transistor npn npn N 4Grid couple the 3rd N transistor npn npn N 3Drain electrode, the 4th N transistor npn npn N 4Source electrode in order to receiving the burning voltage VS-of negative polarity, and the 4th N transistor npn npn N 4Drain electrode then be coupled to the 2nd N transistor npn npn N 2Grid.The 5th N transistor npn npn N 5Grid couple the 3rd N transistor npn npn N 3Drain electrode, the 5th N transistor npn npn N 5Source electrode in order to receiving the burning voltage VS-of negative polarity, and the 5th N transistor npn npn N 5Drain electrode then be coupled to each the pixel P in the 2nd row pixel 21With P 22Compensation distribution CL.Though above-mentioned transistor N 1～N 5With the N transistor npn npn is example; But do not limit to; Viewable design changes to the P transistor npn npn, and assistant is to adjust its corresponding grid control signal and source electrode acknowledge(ment) signal, to reach function and the effect that voltage feeding unit 603_1 or voltage feeding unit 603_2 desire to provide.
Fig. 8 illustrates the time sequential routine figure of the voltage feeding unit 603_1 and the 603_2 that are the 3rd example embodiment.Please merge with reference to Fig. 6～Fig. 8, from Fig. 8, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 603_1 3Can be switched on.Because this moment, the first clock signal CK1 was in the state of forbidden energy, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 603_1 4With N 5Can be ended, and the 2nd N transistor npn npn N 2Can be switched on.Thus, voltage feeding unit 603_1 promptly can provide the burning voltage VS1 (that is VS+) of positive polarity to give each the pixel P in the 2nd row pixel by FP during a picture 21With P 22Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 603_2 3Can be switched on.Because this moment, the first clock signal CK1 was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 603_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 603_2 promptly can provide the burning voltage VS2 (that is VS-) of negative polarity to give each the pixel P in the 3rd row pixel by FP during same picture 31With P 32Compensation distribution CL.
Know based on above-mentioned, because voltage supply device 603 can continue and provide/apply a burning voltage VS1 and VS2 to being positioned at each pixel P accordingly 21, P 22, P 31With P 32Compensation distribution CL, so as to changing each pixel P 21, P 22, P 31With P 32The voltage folder of echo area RA poor, and then adjust each pixel P 21, P 22, P 31With P 32The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 600 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because voltage supply device 603 meetings are lasting and provide/apply a burning voltage VS1 and VS2 to being positioned at each pixel P accordingly 21, P 22, P 31With P 32Compensation distribution CL.Therefore, each pixel P 21, P 22, P 31With P 32The current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 600 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[the 4th example embodiment]
Fig. 9 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 900 of the single bug hole spacing of the present invention's the 4th example embodiment.Please with reference to Fig. 9, the semitransparent and half-reflective liquid crystal display 900 of single bug hole spacing comprises single bug hole spacing display panel 401 and voltage supply device 603, and wherein display panel 401 is a display panels.Certainly; The semitransparent and half-reflective liquid crystal display 900 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 4th example embodiment only shows the parts relevant with the present invention.
In the 4th example embodiment, the structure of display panel 401 is identical with second example embodiment, so also no longer give unnecessary details it at this.In addition, voltage supply device 603 couples each pixel P 11, P 12, P 21With P 22Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to each pixel P 11, P 12, P 21With P 22Compensation distribution CL.
Clearer, voltage supply device 603 has a plurality of voltage feeding unit 603_1 and 603_2 (that is voltage feeding unit of each row pixel collocation).When the type of drive that adopts row counter-rotatings (row inversion) drives display panel 401; Then the 1st voltage feeding unit 603_1 can (for example be produced by time schedule controller according to the 1st sweep signal SS1 (generally being produced by gate drivers) and first and second clock signal CK1 and CK2; But be not restricted to this), the burning voltage VS1 (that is VS-) of negative polarity gives each the pixel P in the 1st row pixel and for example provide 11With P 12Compensation distribution CL.
In addition, the 2nd voltage feeding unit 603_2 can be according to the 2nd sweep signal SS2 and first and second clock signal CK1 and CK2, and the burning voltage VS2 (that is VS+) of positive polarity gives each the pixel P in the 2nd row pixel and for example provide 21With P 22Compensation distribution CL.Wherein, the work period of the first clock signal CK1 be essentially the activation of sweep signal SS1 or SS2 during (identical during the activation of sweep signal SS1 and SS2 usually), the second clock signal CK2 then continues to maintain the state of activation.
In the 4th example embodiment, voltage feeding unit 603_1 is identical with the 3rd example embodiment with the circuit structure of 603_2, so also no longer give unnecessary details it at this.
In addition, Figure 10 illustrates the time sequential routine figure of the voltage feeding unit 603_1 and the 603_2 that are the 4th example embodiment.Please merge with reference to Fig. 7 A, Fig. 7 B, Fig. 9 and Figure 10, from Figure 10, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 603_1 3Can be switched on.Because this moment, the first clock signal CK1 was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 603_1 4With N 5Can be switched on, in addition, the 2nd N transistor npn npn N 2Can't be switched on.Thus, voltage feeding unit 603_1 promptly can provide the burning voltage VS1 (that is VS-) of negative polarity to give each the pixel P in the 1st row pixel by FP during a picture 11With P 12Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 603_2 3Can be switched on.Because this moment, the first clock signal CK1 was in the state of forbidden energy, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 603_2 4With N 5Can be ended, in addition, the 2nd N transistor npn npn N 2Can be switched on.Thus, voltage feeding unit 603_2 promptly can provide the burning voltage VS2 (that is VS+) of positive polarity to give each the pixel P in the 2nd row pixel by FP during same picture 21With P 22Compensation distribution CL.
Know based on above-mentioned, because voltage supply device 603 can continue and provide/apply a burning voltage VS1 and VS2 to being positioned at each pixel P accordingly 11, P 12, P 21With P 22Compensation distribution CL, so as to changing each pixel P 11, P 12, P 21With P 22The voltage folder of echo area RA poor, and then adjust each pixel P 11, P 12, P 21With P 22The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 900 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because voltage supply device 603 meetings are lasting and provide/apply a burning voltage VS1 and VS2 to being positioned at each pixel P accordingly 11, P 12, P 21With P 22Echo area RA in compensation distribution CL.Therefore, each pixel P 11, P 12, P 21With P 22The current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 900 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[the 5th example embodiment]
Figure 11 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 1100 of the single bug hole spacing of the present invention's the 5th example embodiment.Please with reference to Figure 11, the semitransparent and half-reflective liquid crystal display 1100 of single bug hole spacing comprises display panel 101 and voltage supply device 1103, and wherein display panel 101 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 1100 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 5th example embodiment only shows the parts relevant with the present invention.
In the 5th example embodiment, the structure of display panel 101 is identical with first example embodiment, so also no longer give unnecessary details it at this.In addition, voltage supply device 1103 couples each pixel P 21, P 22, P 31With P 32Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to each pixel P 21, P 22, P 31With P 32Compensation distribution CL.
Clearer, voltage supply device 603 has a plurality of voltage feeding unit 1103_1 and 1103_2 (that is voltage feeding unit of each row pixel collocation).When the type of drive that adopts row counter-rotatings (row inversion) drives display panel 101; Then the 1st voltage feeding unit 1103_1 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 1st sweep signal SS1 (generally being produced by gate drivers), the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS1 (that is VS+) of positive polarity gives each the pixel P in the 2nd row pixel and for example provide 21With P 22Compensation distribution CL.
In addition; The 2nd voltage feeding unit 1103_2 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 2nd sweep signal SS2, the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS2 (that is VS-) of negative polarity gives each the pixel P in the 3rd row pixel and for example provide 31With P 32Compensation distribution CL.Wherein, first, second and the 3rd clock signal CK1, CK2 and the work period of XCK2 are essentially (identical during the activation of sweep signal SS1 and SS2 usually) during the activation of sweep signal SS1 or SS2.
It is the voltage feeding unit 1103_1 of the 5th example embodiment and the circuit diagram of 1103_2 that Figure 12 A and Figure 12 B illustrate respectively.Please merge with reference to Figure 12 A and Figure 12 B, voltage feeding unit 1103_1 and 1103_2 all comprise a N transistor npn npn N 1, the 2nd N transistor npn npn N 2, the 3rd capacitor C 3, the 3rd N transistor npn npn N 3, the 4th N transistor npn npn N 4, the 5th N transistor npn npn N 5, and the 6th N transistor npn npn N 6Because the circuit structure of voltage feeding unit 1103_1 and 1103_2 and the relation that couples are all similar, thus below only describe with single voltage feeding unit.
With voltage feeding unit 1103_1 is example, a N transistor npn npn N 1Grid be coupled in source electrode, to receive the second clock signal CK2.The 2nd N transistor npn npn N 2Grid couple a N transistor npn npn N 1Drain electrode, the 2nd N transistor npn npn N 2Source electrode in order to receiving the burning voltage VS+ of positive polarity, and the 2nd N transistor npn npn N 2Drain electrode then be coupled to each the pixel P in the 2nd row pixel 21With P 22Compensation distribution CL.
The 6th N transistor npn npn N 6Grid be coupled in source electrode, receiving the 3rd clock signal XCK2, and the 6th N transistor npn npn N 6Drain electrode then be coupled to a N transistor npn npn N 1Drain electrode.The 3rd N transistor npn npn N 3Grid couple the 1st sweep trace G1 receiving sweep signal SS1, and the 3rd N transistor npn npn N 3Source electrode then in order to receive the first clock signal CK1.The 3rd capacitor C 3First end couple the 3rd N transistor npn npn N 3Drain electrode, and the 3rd capacitor C 3Second end then be coupled to shared distribution CE 2
The 4th N transistor npn npn N 4Grid couple the 3rd N transistor npn npn N 3Drain electrode, the 4th N transistor npn npn N 4Source electrode in order to receiving the burning voltage VS-of negative polarity, and the 4th N transistor npn npn N 4Drain electrode then be coupled to the 2nd N transistor npn npn N 2Grid.The 5th N transistor npn npn N 5Grid couple the 3rd N transistor npn npn N 3Drain electrode, the 5th N transistor npn npn N 5Source electrode in order to receiving the burning voltage VS-of negative polarity, and the 5th N transistor npn npn N 5Drain electrode then be coupled to each the pixel P in the 2nd row pixel 21With P 22Compensation distribution CL.
Figure 13 illustrates the time sequential routine figure of the voltage feeding unit 1103_1 and the 1103_2 that are the 5th example embodiment.Please merge with reference to Figure 11～Figure 13, from Figure 13, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 1103_1 3Can be switched on.Because this moment, first and second clock signal CK1 and CK2 were in the state of forbidden energy, and the 3rd clock signal XCK2 is in the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 1103_1 4With N 5Can be ended, in addition, the 2nd N transistor npn npn N 2Can be switched on.Thus, voltage feeding unit 1103_1 promptly can provide the burning voltage VS1 (that is VS+) of positive polarity to give each the pixel P in the 2nd row pixel by FP during a picture 21With P 22Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 1103_2 3Can be switched on.Because this moment, first and second clock signal CK1 and CK2 were in the state of activation, and the 3rd clock signal XCK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 1103_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 1103_2 promptly can provide the burning voltage VS2 (that is VS-) of negative polarity to give each the pixel P in the 3rd row pixel by FP during same picture 31With P 32Compensation distribution CL.
Know based on above-mentioned, because voltage supply device 1103 can continue and provide/apply a burning voltage VS1 and VS2 to being positioned at each pixel P accordingly 21, P 22, P 31With P 32Compensation distribution CL, so as to changing each pixel P 21, P 22, P 31With P 32The voltage folder of echo area RA poor, and then adjust each pixel P 21, P 22, P 31With P 32The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 1100 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because voltage supply device 1103 meetings are lasting and provide/apply a burning voltage VS1 and VS2 to being positioned at each pixel P accordingly 21, P 22, P 31With P 32Compensation distribution CL.Therefore, each pixel P 21, P 22, P 31With P 32The current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 1100 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2 %, but be not restricted to this).
[the 6th example embodiment]
Figure 14 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 1400 of the single bug hole spacing of the present invention's the 6th example embodiment.Please with reference to Figure 14, the semitransparent and half-reflective liquid crystal display 1400 of single bug hole spacing comprises display panel 401 and voltage supply device 1103, and wherein display panel 401 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 1400 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 6th example embodiment only shows the parts relevant with the present invention.
In the 6th example embodiment, the structure of display panel 401 is identical with second example embodiment, so also no longer give unnecessary details it at this.In addition, voltage supply device 1103 couples each pixel P 11, P 12, P 21With P 22Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to each pixel P 11, P 12, P 21With P 22Compensation distribution CL.
Clearer, voltage supply device 1103 has a plurality of voltage feeding unit 1103_1 and 1103_2 (that is voltage feeding unit of each row pixel collocation).When the type of drive that adopts row counter-rotatings (row inversion) drives display panel 401; Then the 1st voltage feeding unit 1103_1 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 1st sweep signal SS1 (generally being produced by gate drivers), the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS1 (that is VS-) of negative polarity gives each the pixel P in the 1st row pixel and for example provide 11With P 12Compensation distribution CL.
In addition; The 2nd voltage feeding unit 1103_2 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 2nd sweep signal SS2, the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS2 (that is VS+) of positive polarity gives each the pixel P in the 2nd row pixel and for example provide 21With P 22Compensation distribution CL.Wherein, first, second and the 3rd clock signal CK1, CK2 and the work period of XCK2 are essentially (identical during the activation of sweep signal SS1 and SS2 usually) during the activation of sweep signal SS1 or SS2.
In the 6th example embodiment, voltage feeding unit 1103_1 is identical with the 5th example embodiment with the circuit structure of 1103_2, so also no longer give unnecessary details it at this.
In addition, Figure 15 illustrates the time sequential routine figure of the voltage feeding unit 1103_1 and the 1103_2 that are the 6th example embodiment.Please merge with reference to Figure 12 A, Figure 12 B, Figure 14 and Figure 15, from Figure 15, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 1103_1 3Can be switched on.Because this moment, first and second clock signal CK1 and CK2 were in the state of activation, and the 3rd clock signal XCK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 1103_1 4With N 5Can be switched on, in addition, the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 1103_1 promptly can provide the burning voltage VS1 (that is VS-) of negative polarity to give each the pixel P in the 1st row pixel by FP during a picture 11With P 12Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 1103_2 3Can be switched on.Because this moment, first and second clock signal CK1 and CK2 were in the state of forbidden energy, and the 3rd clock signal XCK2 is in the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 1103_2 4With N 5Can be ended, in addition, the 2nd N transistor npn npn N 2Can be switched on.Thus, voltage feeding unit 1103_2 promptly can provide the burning voltage VS2 (that is VS+) of positive polarity to give each the pixel P in the 2nd row pixel by FP during same picture 21With P 22Compensation distribution CL.
Know based on above-mentioned, because voltage supply device 1103 can continue and provide/apply a burning voltage VS1 and VS2 to being positioned at each pixel P accordingly 11, P 12, P 21With P 22Compensation distribution CL, so as to changing each pixel P 11, P 12, P 21With P 22The voltage folder of echo area RA poor, and then adjust each pixel P 11, P 12, P 21With P 22The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 1400 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because voltage supply device 1103 meetings are lasting and provide/apply a burning voltage VS1 and VS2 to being positioned at each pixel P accordingly 11, P 12, P 21With P 22Compensation distribution CL.Therefore, each pixel P 11, P 12, P 21With P 22The current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 1400 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[the 7th example embodiment]
Figure 16 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 1600 of the single bug hole spacing of the present invention's the 7th example embodiment.Please with reference to Figure 16; The semitransparent and half-reflective liquid crystal display 1600 of single bug hole spacing comprises display panel 1601 and the voltage supply device that is made up of first and second sub-voltage supply device 1603 and 1605, and wherein display panel 1601 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 1600 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 7th example embodiment only shows the parts relevant with the present invention.
Display panel 1601 comprises multi-strip scanning line G2 and G3 (only showing 2 sweep traces conveniently to do explanation), many cardinal principles and sweep trace G2 and vertically disposed data line D1 of G3 and D2 (only showing 2 data lines conveniently to do explanation), and a plurality of pixel P that are positioned at the viewing area AA of display panel 1601 21, P 22, P 31With P 32(only showing 4 pixels) conveniently to do explanation.
Pixel P 21, P 22, P 31With P 32Can electrically connect with corresponding data line and sweep trace respectively, and arrange with matrix-style.For instance, pixel P 21Electrically connect with data line D1 and sweep trace G2 respectively; Pixel P 22Electrically connect with data line D2 and sweep trace G2 respectively; Pixel P 31Electrically connect with data line D1 and sweep trace G3 respectively; And pixel P 32Electrically connect with data line D2 and sweep trace G3 respectively.In addition, pixel P 21Be expressed as the 1st pixel in the 2nd row pixel in the display panel 1601; Pixel P 22Be expressed as the 2nd pixel in the 2nd row pixel in the display panel 1601; Pixel P 31Be expressed as the 1st pixel in the 3rd row pixel in the display panel 1601; And pixel P 32Be expressed as the 2nd pixel in the 3rd row pixel in the display panel 1601.
Each pixel P 21, P 22, P 31With P 32Comprise shared distribution CE 2With compensation distribution CL.Shared distribution CE 2Be positioned at each pixel P for example 21, P 22, P 31With P 32Penetrating region TA in, in order to receive common voltage Vcom.Compensation distribution CL is positioned at each pixel P for example 21, P 22, P 31With P 32Echo area RA in, in order to receive burning voltage VS1～VS4 respectively.In addition, each pixel P 21, P 22, P 31With P 32More comprise pixel transistor T, the first liquid crystal capacitance C LC1, storage capacitors C ST, first capacitor C 1, the second liquid crystal capacitance C LC2, and second capacitor C 2Because all pixel P 21, P 22, P 31With P 32Circuit structure with to couple relation all similar, so below only describe with single pixel.
With pixel P 21Be example, the grid of pixel transistor T couples sweep trace G2, and the source electrode of pixel transistor T then is coupled to data line D1.Generally speaking, the pixel electrode (pixel electrode) that electrically connects with the drain electrode of pixel transistor T with in order to receive the common electrode CE of common voltage Vcom 1Between can form the first liquid crystal capacitance C LC1, and with shared distribution CE 2Between can form storage capacitors C ST
The first liquid crystal capacitance C LC1First end couple the drain electrode of pixel transistor T, and the first liquid crystal capacitance C LC1Second end then be coupled to common electrode CE 1Storage capacitors C STFirst end couple the drain electrode of pixel transistor T, and storage capacitors C STSecond end then be coupled to shared distribution CE 2Wherein, pixel transistor T, the first liquid crystal capacitance C LC1And storage capacitors C STBe positioned at pixel P 21Penetrating region TA in.
In addition, first capacitor C 1First end couple the drain electrode of pixel transistor T.The second liquid crystal capacitance C LC2First end couple first capacitor C 1Second end, and the second liquid crystal capacitance C LC2Second end then be coupled to common electrode CE 1Second capacitor C 2First end couple first capacitor C 1Second end, and second capacitor C 2Second end then be coupled to compensation distribution CL.Wherein, first capacitor C 1, the second liquid crystal capacitance C LC2And second capacitor C 2Be positioned at pixel P 21Echo area RA in.
In the 7th example embodiment, the first sub-voltage supply device 1603 couples the odd pixel P in each row pixel 21With P 31Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to pixel P 21With P 31Compensation distribution CL.In addition, the second sub-voltage supply device 1605 couples all the dual pixel P in each row pixel 22With P 32Compensation distribution CL, in order to continue and to supply burning voltage VS3 and VS4 respectively accordingly to pixel P 22With P 32Compensation distribution CL.Strange here pixel refers to the pixel of odd pixel row, and dual pixel refers to the pixel of even pixel row.
Clearer, the first sub-voltage supply device 1603 has a plurality of voltage feeding unit 1603_1 and 1603_2.When the type of drive that adopts row counter-rotating (column inversion) drives display panel 1601; Then the 1st voltage feeding unit 1603_1 can (for example be produced by time schedule controller according to first and second clock signal CK and the XCK of the 1st sweep signal SS1 (generally being produced by gate drivers) and phase differential 180 degree; But be not restricted to this), the burning voltage VS1 (that is VS+) of positive polarity gives the strange pixel P in the 2nd row pixel and for example provide 21Compensation distribution CL.
In addition, the 2nd voltage feeding unit 1603_2 can be according to first and second clock signal CK and the XCK of the 2nd sweep signal SS2 and phase differential 180 degree, and the burning voltage VS2 (that is VS+) of positive polarity gives the strange pixel P in the 3rd row pixel and for example provide 31Compensation distribution CL.Wherein, the work period of first and second clock signal CK and XCK (duty cycle) is essentially (frame period) during the picture of semitransparent and half-reflective liquid crystal display 1600 of single bug hole spacing.
In addition, the second sub-voltage supply device 1605 has a plurality of voltage feeding unit 1605_1 and 1605_2.When the type of drive that adopts row counter-rotating (column inversion) drives display panel 1601; Then the 1st voltage feeding unit 1605_1 can be according to first and second clock signal CK and the XCK of the 1st sweep signal SS1 and phase differential 180 degree, and the burning voltage VS3 (that is VS-) of negative polarity gives the dual pixel P in the 2nd row pixel and for example provide 22Compensation distribution CL.In addition, the 2nd voltage feeding unit 1605_2 can be according to first and second clock signal CK and the XCK of the 2nd sweep signal SS2 and phase differential 180 degree, and the burning voltage VS4 (that is VS-) of negative polarity gives the dual pixel P in the 3rd row pixel and for example provide 32Compensation distribution CL.
It is the voltage feeding unit 1603_1 of the 7th example embodiment and the circuit diagram of 1603_2 that Figure 17 A and Figure 17 B illustrate respectively.Please merge with reference to Figure 17 A and Figure 17 B, voltage feeding unit 1603_1 and 1603_2 all comprise a N transistor npn npn N 1, the 3rd capacitor C 3, the 2nd N transistor npn npn N 2, the 3rd N transistor npn npn N 3, the 4th capacitor C 4, and the 4th N transistor npn npn N 4Because the circuit structure of voltage feeding unit 1603_1 and 1603_2 and the relation that couples are all similar, thus below only describe with single voltage feeding unit.
With voltage feeding unit 1603_1 is example, a N transistor npn npn N 1Grid couple the 1st sweep trace G1 receiving sweep signal SS1, an and N transistor npn npn N 1Source electrode in order to receive the first clock signal CK.The 3rd capacitor C 3First end couple a N transistor npn npn N 1Drain electrode, and the 3rd capacitor C 3Second end then be coupled to shared distribution CE 2The 2nd N transistor npn npn N 2Grid couple a N transistor npn npn N 1Drain electrode, the 2nd N transistor npn npn N 2Source electrode in order to receiving the burning voltage VS+ of positive polarity, and the 2nd N transistor npn npn N 2Drain electrode then be coupled to the strange pixel P in the 2nd row pixel 21Compensation distribution CL.
The 3rd N transistor npn npn N 3Grid couple the 1st sweep trace G1 receiving sweep signal SS1, and the 3rd N transistor npn npn N 3Source electrode then in order to receive the second clock signal XCK.The 4th capacitor C 4First end couple the 3rd N transistor npn npn N 3Drain electrode, and the 4th capacitor C 4Second end then be coupled to shared distribution CE 2The 4th N transistor npn npn N 4Grid couple the 3rd N transistor npn npn N 3Drain electrode, the 4th N transistor npn npn N 4Source electrode in order to receiving the burning voltage VS-of negative polarity, and the 4th N transistor npn npn N 4Drain electrode then be coupled to the strange pixel P in the 2nd row pixel 21Compensation distribution CL.Though above-mentioned transistor N 1～N 4With the N transistor npn npn is example; But do not limit to; Viewable design changes to the P transistor npn npn, and helps and draw acknowledge(ment) signal to adjust its corresponding grid control signal and source, to reach function and the effect that voltage feeding unit 1603_1 or voltage feeding unit 1603_2 desire to provide.
It is the voltage feeding unit 1605_1 of the 7th example embodiment and the circuit diagram of 1605_2 that Figure 17 C and Figure 17 D illustrate respectively.Please merge with reference to Figure 17 C and Figure 17 D, voltage feeding unit 1605_1 and 1605_2 all comprise a N transistor npn npn N 1, the 3rd capacitor C 3, the 2nd N transistor npn npn N 2, the 3rd N transistor npn npn N 3, the 4th capacitor C 4, and the 4th N transistor npn npn N 4Because the circuit structure of voltage feeding unit 1605_1 and 1605_2 and the relation that couples are all similar, thus below only describe with single voltage feeding unit.
With voltage feeding unit 1605_1 is example, a N transistor npn npn N 1Grid couple the 1st sweep trace G1 receiving sweep signal SS1, an and N transistor npn npn N 1Source electrode in order to receive the first clock signal CK.The 3rd capacitor C 3First end couple a N transistor npn npn N 1Drain electrode, and the 3rd capacitor C 3Second end then be coupled to shared distribution CE 2The 2nd N transistor npn npn N 2Grid couple a N transistor npn npn N 1Drain electrode, the 2nd N transistor npn npn N 2Source electrode in order to receiving the burning voltage VS-of negative polarity, and the 2nd N transistor npn npn N 2Drain electrode then be coupled to the dual pixel P in the 2nd row pixel 22Compensation distribution CL.
The 3rd N transistor npn npn N 3Grid couple the 1st sweep trace G1 receiving sweep signal SS1, and the 3rd N transistor npn npn N 3Source electrode then in order to receive the second clock signal XCK.The 4th capacitor C 4First end couple the 3rd N transistor npn npn N 3Drain electrode, and the 4th capacitor C 4Second end then be coupled to shared distribution CE 2The 4th N transistor npn npn N 4Grid couple the 3rd N transistor npn npn N 3Drain electrode, the 4th N transistor npn npn N 4Source electrode in order to receiving the burning voltage VS+ of positive polarity, and the 4th N transistor npn npn N 4Drain electrode then be coupled to the dual pixel P in the 2nd row pixel 22Compensation distribution CL.
Figure 18 A illustrates the time sequential routine figure of the voltage feeding unit 1603_1 and the 1603_2 that are the 7th example embodiment.Please merge with reference to Figure 16, Figure 17 A, Figure 17 B and Figure 18 A, from Figure 18 A, can know and find out, when sweep signal SS1 activation, the N transistor npn npn N in the voltage feeding unit 1603_1 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK was in the state of activation, and the second clock signal XCK is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 1603_1 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 1603_1 promptly can provide the burning voltage VS1 (that is VS+) of positive polarity to give the strange pixel P in the 2nd row pixel by FP during a picture 21Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the N transistor npn npn N in the voltage feeding unit 1603_2 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK still was in the state of activation, and the second clock signal XCK still is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 1603_2 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 1603_2 promptly can provide the burning voltage VS2 (that is VS+) of positive polarity to give the strange pixel P in the 3rd row pixel by FP during same picture 31Compensation distribution CL.
Figure 18 B illustrates the time sequential routine figure of the voltage feeding unit 1605_1 and the 1605_2 that are the 7th example embodiment.Please merge with reference to Figure 16, Figure 17 C, Figure 17 D and Figure 18 B, from Figure 18 B, can know and find out, when sweep signal SS1 activation, the N transistor npn npn N in the voltage feeding unit 1605_1 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK was in the state of activation, and the second clock signal XCK is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 1605_1 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 1605_1 promptly can provide the burning voltage VS3 (that is VS-) of negative polarity to give the dual pixel P in the 2nd row pixel by FP during same picture 22Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the N transistor npn npn N in the voltage feeding unit 1605_2 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK still was in the state of activation, and the second clock signal XCK still is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 1605_2 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 1605_2 promptly can provide the burning voltage VS4 (that is VS-) of negative polarity to give the dual pixel P in the 3rd row pixel by FP during same picture 32Compensation distribution CL.
Know based on above-mentioned, because the voltage supply device that first and second sub-voltage supply device 1603 and 1605 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 21, P 22, P 31With P 32Compensation distribution CL, so as to changing each pixel P 21, P 22, P 31With P 32The voltage folder of echo area RA poor, and then adjust each pixel P 21, P 22, P 31With P 32The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 1600 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because the voltage supply device that first and second sub-voltage supply device 1603 and 1605 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 21, P 22, P 31With P 32Compensation distribution CL.Therefore, each pixel P 21, P 22, P 31With P 32The current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 1600 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[the 8th example embodiment]
Figure 19 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 1900 of the single bug hole spacing of the present invention's the 8th example embodiment.Please with reference to Figure 19; The semitransparent and half-reflective liquid crystal display 1900 of single bug hole spacing comprises display panel 1901 and the voltage supply device that is made up of first and second sub-voltage supply device 1603 and 1605, and wherein display panel 1901 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 1900 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 8th example embodiment only shows the parts relevant with the present invention.
Display panel 1901 comprises multi-strip scanning line G1 and G2 (only showing 2 sweep traces conveniently to do explanation), many cardinal principles and sweep trace G1 and vertically disposed data line D1 of G2 and D2 (only showing 2 data lines conveniently to do explanation), and a plurality of pixel P that are positioned at the viewing area AA of display panel 1901 11, P 12, P 21With P 22(only showing 4 pixels) conveniently to do explanation.
Pixel P 11, P 12, P 21With P 22Can electrically connect with corresponding data line and sweep trace respectively, and arrange with matrix-style.For instance, pixel P 11Electrically connect with data line D1 and sweep trace G1 respectively; Pixel P 12Electrically connect with data line D2 and sweep trace G1 respectively; Pixel P 21Electrically connect with data line D1 and sweep trace G2 respectively; And pixel P 22Electrically connect with data line D2 and sweep trace G2 respectively.In addition, pixel P 11Be expressed as the 1st pixel in the 1st row pixel in the display panel 1901; Pixel P 12Be expressed as the 2nd pixel in the 1st row pixel in the display panel 1901; Pixel P 21Be expressed as the 1st pixel in the 2nd row pixel in the display panel 1901; And pixel P 22Be expressed as the 2nd pixel in the 2nd row pixel in the display panel 1901.
Each pixel P 11, P 12, P 21With P 22Comprise shared distribution CE 2With compensation distribution CL.Shared distribution CE 2Be positioned at each pixel P for example 11, P 12, P 21With P 22Penetrating region TA in, in order to receive common voltage Vcom.Compensation distribution CL is positioned at each pixel P for example 11, P 12, P 21With P 22Echo area RA in, in order to receive burning voltage VS1～VS4 respectively accordingly.In addition, each pixel P 11, P 12, P 21With P 22More comprise pixel transistor T, the first liquid crystal capacitance C LC1, storage capacitors C ST, first capacitor C 1, the second liquid crystal capacitance C LC2, and second capacitor C 2Because all pixel P 11, P 12, P 21With P 22Circuit structure with to couple relation all similar, so below only describe with single pixel.
With pixel P 11Be example, the grid of pixel transistor T couples sweep trace G1, and the source electrode of pixel transistor T then is coupled to data line D1.Generally speaking, the pixel electrode (pixel electrode) that electrically connects with the drain electrode of pixel transistor T with in order to receive the common electrode CE of common voltage Vcom 1Between can form the first liquid crystal capacitance C LC1, and with shared distribution CE 2Between can form storage capacitors C ST
The first liquid crystal capacitance C LC1First end couple the drain electrode of pixel transistor T, and the first liquid crystal capacitance C LC1Second end then be coupled to common electrode C E1Storage capacitors C STFirst end couple the drain electrode of pixel transistor T, and storage capacitors C STSecond end then be coupled to shared distribution CE 2Wherein, pixel transistor T, the first liquid crystal capacitance C LC1And storage capacitors C STBe positioned at pixel P 11Penetrating region TA in.
In addition, first capacitor C 1First end couple the drain electrode of pixel transistor T.The second liquid crystal capacitance C LC2First end couple first capacitor C 1Second end, and the second liquid crystal capacitance C LC2Second end then be coupled to common electrode CE 1Second capacitor C 2First end couple first capacitor C 1Second end, and second capacitor C 2Second end then be coupled to compensation distribution CL.Wherein, first capacitor C 1, the second liquid crystal capacitance C LC2And second capacitor C 2Be positioned at pixel P 11Echo area RA in.
In the 8th example embodiment, the first sub-voltage supply device 1603 couples the odd pixel P in each row pixel 11With P 21Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to pixel P 11With P 21Compensation distribution CL.In addition, the second sub-voltage supply device 1605 couples all the dual pixel P in each row pixel 12With P 22Compensation distribution CL, in order to continue and to supply burning voltage VS3 and VS4 accordingly to pixel P 12With P 22Compensation distribution CL.
Clearer, the first sub-voltage supply device 1603 has a plurality of voltage feeding unit 1603_1 and 1603_2.When the type of drive that adopts row counter-rotating (column inversion) drives display panel 1901; Then the 1st voltage feeding unit 1603_1 can (for example be produced by time schedule controller according to first and second clock signal CK and the XCK of the 1st sweep signal SS1 (generally being produced by gate drivers) and phase differential 180 degree; But be not restricted to this), the burning voltage VS1 (that is VS+) of positive polarity gives the strange pixel P in the 1st row pixel and for example provide 11Compensation distribution CL.
In addition, the 2nd voltage feeding unit 1603_2 can be according to first and second clock signal CK and the XCK of the 2nd sweep signal SS2 and phase differential 180 degree, and the burning voltage VS2 (that is VS+) of positive polarity gives the strange pixel P in the 2nd row pixel and for example provide 21Compensation distribution CL.Wherein, the work period of first and second clock signal CK and XCK (duty cycle) is essentially during the picture of semitransparent and half-reflective liquid crystal display 1900 of single bug hole spacing.
In addition, the second sub-voltage supply device 1605 has a plurality of voltage feeding unit 1605_1 and 1605_2.When the type of drive that adopts row counter-rotating (column inversion) drives display panel 1901; Then the 1st voltage feeding unit 1605_1 can be according to first and second clock signal CK and the XCK of the 1st sweep signal SS1 and phase differential 180 degree, and the burning voltage VS3 (that is VS-) of negative polarity gives the dual pixel P in the 1st row pixel and for example provide 12Compensation distribution CL.In addition, the 2nd voltage feeding unit 1605_2 can be according to first and second clock signal CK and the XCK of the 2nd sweep signal SS2 and phase differential 180 degree, and the burning voltage VS4 (that is VS-) of negative polarity gives the dual pixel P in the 2nd row pixel and for example provide 22Compensation distribution CL.
In the 8th example embodiment, voltage feeding unit 1603_1,1603_2,1605_1 are identical with the 7th example embodiment with the circuit structure of 1605_2, so at this and no longer give unnecessary details it.
In addition, Figure 20 A illustrates the time sequential routine figure of the voltage feeding unit 1603_1 and the 1603_2 that are the 8th example embodiment.Please merge with reference to Figure 17 A, Figure 17 B, Figure 19 and Figure 20 A, from Figure 20 A, can know and find out, when sweep signal SS1 activation, the N transistor npn npn N in the voltage feeding unit 1603_1 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK was in the state of activation, and the second clock signal XCK is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 1603_1 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 1603_1 promptly can provide the burning voltage VS1 (that is VS+) of positive polarity to give the strange pixel P in the 1st row pixel by FP during a picture 11Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the N transistor npn npn N in the voltage feeding unit 1603_2 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK still was in the state of activation, and the second clock signal XCK still is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 1603_2 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 1603_2 promptly can provide the burning voltage VS2 (that is VS+) of positive polarity to give the strange pixel P in the 2nd row pixel by FP during same picture 21Compensation distribution CL.
Figure 20 B illustrates the time sequential routine figure of the voltage feeding unit 1605_1 and the 1605_2 that are the 8th example embodiment.Please merge with reference to Figure 17 C, Figure 17 D, Figure 19 and Figure 20 B, from Figure 20 B, can know and find out, when sweep signal SS1 activation, the N transistor npn npn N in the voltage feeding unit 1605_1 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK was in the state of activation, and the second clock signal XCK is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 1605_1 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 1605_1 promptly can provide the burning voltage VS3 (that is VS-) of negative polarity to give the dual pixel P in the 1st row pixel by FP during same picture 12Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the N transistor npn npn N in the voltage feeding unit 1605_2 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK still was in the state of activation, and the second clock signal XCK still is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 1605_2 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 1605_2 promptly can provide the burning voltage VS4 (that is VS-) of negative polarity to give the dual pixel P in the 2nd row pixel by FP during same picture 22Compensation distribution CL.
Know based on above-mentioned, because the voltage supply device that first and second sub-voltage supply device 1603 and 1605 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 11, P 12, P 21With P 22Compensation distribution CL, so as to changing each pixel P 11, P 12, P 21With P 22The voltage folder of echo area RA poor, and then adjust each pixel P 11, P 12, P 21With P 22The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 1900 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because the voltage supply device that first and second sub-voltage supply device 1603 and 1605 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 11, P 12, P 21With P 22Echo area RA in compensation distribution CL.Therefore, each pixel P 11, P 12, P 21With P 22Echo area RA in the current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 1900 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[the 9th example embodiment]
Figure 21 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 2100 of the single bug hole spacing of the present invention's the 9th example embodiment.Please with reference to Figure 21; The semitransparent and half-reflective liquid crystal display 2100 of single bug hole spacing comprises display panel 1601 and the voltage supply device that is made up of first and second sub-voltage supply device 2103 and 2105, and wherein display panel 1601 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 2100 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 9th example embodiment only shows the parts relevant with the present invention.
In the 9th example embodiment, the structure of display panel 1601 is identical with the 7th example embodiment, so also no longer give unnecessary details it at this.In addition, the first sub-voltage supply device 2103 couples the odd pixel P in each row pixel 21With P 31Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to pixel P 21With P 31Compensation distribution CL.In addition, the second sub-voltage supply device 2105 couples all the dual pixel P in each row pixel 22With P 32Compensation distribution CL, in order to continue and to supply burning voltage VS3 and VS4 accordingly to pixel P 22With P 32Compensation distribution CL.
Clearer, the first sub-voltage supply device 2103 has a plurality of voltage feeding unit 2103_1 and 2103_2.When the type of drive that adopts row counter-rotating (column inversion) drives display panel 1601; Then the 1st voltage feeding unit 2103_1 can (for example be produced by time schedule controller according to the 1st sweep signal SS1 (generally being produced by gate drivers) and first and second clock signal CK1 and CK2; But be not restricted to this), the burning voltage VS1 (that is VS-) of negative polarity gives the strange pixel P in the 2nd row pixel and for example provide 21Compensation distribution CL.
In addition, the 2nd voltage feeding unit 2103_2 can be according to the 2nd sweep signal SS2 and first and second clock signal CK1 and CK2, and the burning voltage VS2 (that is VS-) of negative polarity gives the strange pixel P in the 3rd row pixel and for example provide 31Compensation distribution CL.Wherein, the work period of the first clock signal CK1 is essentially during the picture of semitransparent and half-reflective liquid crystal display 2100 of single bug hole spacing, and the second clock signal CK2 then continues to maintain the state of activation.
In addition, the second sub-voltage supply device 2105 has a plurality of voltage feeding unit 2105_1 and 2105_2.When the type of drive that adopts row counter-rotating (column inversion) drives display panel 1601; Then the 1st voltage feeding unit 2105_1 can be according to the 1st sweep signal SS1 and first and second clock signal CK1 and CK2, and the burning voltage VS3 (that is VS+) of positive polarity gives the dual pixel P in the 2nd row pixel and for example provide 22Compensation distribution CL.In addition, the 2nd voltage feeding unit 2105_2 can be according to the 2nd sweep signal SS2 and first and second clock signal CK1 and CK2, and the burning voltage VS4 (that is VS+) of positive polarity gives the dual pixel P in the 3rd row pixel and for example provide 32Compensation distribution CL.
It is the voltage feeding unit 2103_1 of the 9th example embodiment and the circuit diagram of 2103_2 that Figure 22 A and Figure 22 B illustrate respectively.Please merge with reference to Figure 22 A and Figure 22 B, voltage feeding unit 2103_1 and 2103_2 all comprise a N transistor npn npn N 1, the 2nd N transistor npn npn N 2, the 3rd capacitor C 3, the 3rd N transistor npn npn N 3, the 4th N transistor npn npn N 4, and the 5th N transistor npn npn N 5Because the circuit structure of voltage feeding unit 2103_1 and 2103_2 and the relation that couples are all similar, thus below only describe with single voltage feeding unit.
With voltage feeding unit 2103_1 is example, a N transistor npn npn N 1Grid be coupled in source electrode, to receive the second clock signal CK2.The 2nd N transistor npn npn N 2Grid couple a N transistor npn npn N 1Drain electrode, the 2nd N transistor npn npn N 2Source electrode in order to receiving the burning voltage VS+ of positive polarity, and the 2nd N transistor npn npn N 2Drain electrode then be coupled to the strange pixel P in the 2nd row pixel 21Compensation distribution CL.The 3rd N transistor npn npn N 3Grid couple the 1st sweep trace G1 receiving sweep signal SS1, and the 3rd N transistor npn npn N 3Source electrode then in order to receive the first clock signal CK1.
The 3rd capacitor C 3First end couple the 3rd N transistor npn npn N 3Drain electrode, and the 3rd capacitor C 3Second end then be coupled to shared distribution CE 2The 4th N transistor npn npn N 4Grid couple the 3rd N transistor npn npn N 3Drain electrode, the 4th N transistor npn npn N 4Source electrode in order to receiving the burning voltage VS-of negative polarity, and the 4th N transistor npn npn N 4Drain electrode then be coupled to the 2nd N transistor npn npn N 2Grid.The 5th N transistor npn npn N 5Grid couple the 3rd N transistor npn npn N 3Drain electrode, the 5th N transistor npn npn N 5Source electrode in order to receiving the burning voltage VS-of negative polarity, and the 5th N transistor npn npn N 5Drain electrode then be coupled to the strange pixel P in the 2nd row pixel 21Compensation distribution CL.
It is the voltage feeding unit 2105_1 of the 9th example embodiment and the circuit diagram of 2105_2 that Figure 22 C and Figure 22 D illustrate respectively.Please merge with reference to Figure 22 C and Figure 22 D, voltage feeding unit 2105_1 and 2105_2 all comprise a N transistor npn npn N 1, the 2nd N transistor npn npn N 2, the 3rd capacitor C 3, the 3rd N transistor npn npn N 3, the 4th N transistor npn npn N 4, and the 5th N transistor npn npn N 5Because the circuit structure of voltage feeding unit 2105_1 and 2105_2 and the relation that couples are all similar, thus below only describe with single voltage feeding unit.
With voltage feeding unit 2105_1 is example, a N transistor npn npn N 1Grid be coupled in source electrode, to receive the second clock signal CK2.The 2nd N transistor npn npn N 2Grid couple a N transistor npn npn N 1Drain electrode, the 2nd N transistor npn npn N 2Source electrode in order to receiving the burning voltage VS-of negative polarity, and the 2nd N transistor npn npn N 2Drain electrode then be coupled to the dual pixel P in the 2nd row pixel 22Compensation distribution CL.The 3rd N transistor npn npn N 3Grid couple the 1st sweep trace G1 receiving sweep signal SS1, and the 3rd N transistor npn npn N 3Source electrode then in order to receive the first clock signal CK1.
The 3rd capacitor C 3First end couple the 3rd N transistor npn npn N 3Drain electrode, and the 3rd capacitor C 3Second end then be coupled to shared distribution CE 2The 4th N transistor npn npn N 4Grid couple the 3rd N transistor npn npn N 3Drain electrode, the 4th N transistor npn npn N 4Source electrode in order to receiving the burning voltage VS-of negative polarity, and the 4th N transistor npn npn N 4Drain electrode then be coupled to the 2nd N transistor npn npn N 2Grid.The 5th N transistor npn npn N 5Grid couple the 3rd N transistor npn npn N 3Drain electrode, the 5th N transistor npn npn N 5Source electrode in order to receiving the burning voltage VS+ of positive polarity, and the 5th N transistor npn npn N 5Drain electrode then be coupled to the dual pixel P in the 2nd row pixel 22Compensation distribution CL.
Figure 23 A illustrates the time sequential routine figure of the voltage feeding unit 2103_1 and the 2103_2 that are the 9th example embodiment.Please merge with reference to Figure 21, Figure 22 A, Figure 22 B and Figure 23 A, from Figure 23 A, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2103_1 3Can be switched on.Because this moment, the first clock signal CK1 was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2103_1 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2103_1 promptly can provide the burning voltage VS1 (that is VS-) of negative polarity to give the strange pixel P in the 2nd row pixel by FP during a picture 21Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2103_2 3Can be switched on.Because this moment, the first clock signal CK1 still was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2103_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2103_2 promptly can provide the burning voltage VS2 (that is VS-) of negative polarity to give the strange pixel P in the 3rd row pixel by FP during same picture 31Compensation distribution CL.
In addition, Figure 23 B illustrates the time sequential routine figure of the voltage feeding unit 2503_1 and the 2503_2 that are the 9th example embodiment.Please merge with reference to Figure 21, Figure 22 C, Figure 22 D and Figure 23 B, from Figure 23 B, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2105_1 3Can be switched on.Because this moment, the first clock signal CK1 was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2105_1 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2105_1 promptly can provide the burning voltage VS3 (that is VS+) of positive polarity to give the dual pixel P in the 2nd row pixel by FP during same picture 22Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2105_2 3Can be switched on.Because this moment, the first clock signal CK1 still was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2105_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2105_2 promptly can provide the burning voltage VS4 (that is VS+) of positive polarity to give the dual pixel P in the 3rd row pixel by FP during same picture 32Compensation distribution CL.
Know based on above-mentioned, because the voltage supply device that first and second sub-voltage supply device 2103 and 2105 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 21, P 22, P 31With P 32Compensation distribution CL, so as to changing each pixel P 21, P 22, P 31With P 32The voltage folder of echo area RA poor, and then adjust each pixel P 21, P 22, P 31With P 32The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 2100 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because the voltage supply device that first and second sub-voltage supply device 2103 and 2105 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 21, P 22, P 31With P 32Compensation distribution CL.Therefore, each pixel P 21, P 22, P 31With P 32The current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 2100 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[the tenth example embodiment]
Figure 24 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 2400 of the single bug hole spacing of the present invention's the tenth example embodiment.Please with reference to Figure 24; The semitransparent and half-reflective liquid crystal display 2400 of single bug hole spacing comprises display panel 1901 and the voltage supply device that is made up of first and second sub-voltage supply device 2103 and 2105, and wherein display panel 1901 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 2400 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the tenth example embodiment only shows the parts relevant with the present invention.
In the tenth example embodiment, the structure of display panel 1901 is identical with the 8th example embodiment, so also no longer give unnecessary details it at this.In addition, the first sub-voltage supply device 2103 couples the odd pixel P in each row pixel 11With P 21Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to pixel P 11With P 21Compensation distribution CL.The second sub-voltage supply device 2105 couples all the dual pixel P in each row pixel 12With P 22Compensation distribution CL, in order to continue and to supply burning voltage VS3 and VS4 accordingly to pixel P 12With P 22Compensation distribution CL.
Clearer, the first sub-voltage supply device 2103 has a plurality of voltage feeding unit 2103_1 and 2103_2.When the type of drive that adopts row counter-rotating (column inversion) drives display panel 1901; Then the 1st voltage feeding unit 2103_1 can (for example be produced by time schedule controller according to the 1st sweep signal SS1 (generally being produced by gate drivers) and first and second clock signal CK1 and CK2; But be not restricted to this), the burning voltage VS1 (that is VS-) of negative polarity gives the strange pixel P in the 1st row pixel and for example provide 11Compensation distribution CL.
In addition, the 2nd voltage feeding unit 21032 can be according to the 2nd sweep signal SS2 and first and second clock signal CK1 and CK2, and the burning voltage VS2 (that is VS-) of negative polarity gives the strange pixel P in the 2nd row pixel and for example provide 21Compensation distribution CL.Wherein, the work period of the first clock signal CK1 is essentially during the picture of semitransparent and half-reflective liquid crystal display 2100 of single bug hole spacing, and the second clock signal CK2 then continues to maintain the state of activation.
In addition, the second sub-voltage supply device 2105 has a plurality of voltage feeding unit 2105_1 and 2105_2.When the type of drive of employing row counter-rotating (column inversion) drives display panel 1901; Then the 1st voltage feeding unit 2105_1 can be according to the 1st sweep signal SS1 and first and second clock signal CK1 and CK2, and the burning voltage VS3 (that is VS+) of positive polarity gives the dual pixel P in the 1st row pixel and for example provide 12Compensation distribution CL.In addition, the 2nd voltage feeding unit 2105_2 can be according to the 2nd sweep signal SS2 and first and second clock signal CK1 and CK2, and the burning voltage VS4 (that is VS+) of positive polarity gives the dual pixel P in the 2nd row pixel and for example provide 22Compensation distribution CL.
In the tenth example embodiment, the circuit structure of voltage feeding unit 2103_1,2103_2,2105_1 and 2105_2 is identical with the 9th example embodiment, so also no longer give unnecessary details it at this.
In addition, Figure 25 A illustrates the time sequential routine figure of the voltage feeding unit 2103_1 and the 2103_2 that are the tenth example embodiment.Please merge with reference to Figure 22 A, Figure 22 B, Figure 24 and Figure 25 A, from Figure 25 A, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2103_1 3Can be switched on.Because this moment, the first clock signal CK1 was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2103_1 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2103_1 promptly can provide the burning voltage VS1 (that is VS-) of negative polarity to give the strange pixel P in the 1st row pixel by FP during a picture 11Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2103_2 3Can be switched on.Because this moment, the first clock signal CK1 still was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2103_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2103_2 promptly can provide the burning voltage VS2 (that is VS-) of negative polarity to give the strange pixel P in the 2nd row pixel by FP during same picture 21Compensation distribution CL.
In addition, Figure 25 B illustrates the time sequential routine figure of the voltage feeding unit 2105_1 and the 2105_2 that are the tenth example embodiment.Please merge with reference to Figure 22 C, Figure 22 D, Figure 24 and Figure 25 B, from Figure 25 B, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2105_1 3Can be switched on.Because this moment, the first clock signal CK1 was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2105_1 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2105_1 promptly can provide the burning voltage VS3 (that is VS+) of positive polarity to give the dual pixel P in the 1st row pixel by FP during same picture 12Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2105_2 3Can be switched on.Because this moment, the first clock signal CK1 still was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2105_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2105_2 promptly can provide the burning voltage VS4 (that is VS+) of positive polarity to give the dual pixel P in the 2nd row pixel by FP during same picture 22Compensation distribution CL.
Know based on above-mentioned, because the voltage supply device that first and second sub-voltage supply device 2103 and 2105 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 11, P 12, P 21With P 22Compensation distribution CL, so as to changing each pixel P 11, P 12, P 21With P 22The voltage folder of echo area RA poor, and then adjust each pixel P 11, P 12, P 21With P 22The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 2400 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because the voltage supply device that first and second sub-voltage supply device 2103 and 2105 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 11, P 12, P 21With P 22Compensation distribution CL.Therefore, each pixel P 11, P 12, P 21With P 22The current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 2400 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[the 11 example embodiment]
Figure 26 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 2600 of the single bug hole spacing of the present invention's the 11 example embodiment.Please with reference to Figure 26; The semitransparent and half-reflective liquid crystal display 2600 of single bug hole spacing comprises display panel 1601 and the voltage supply device that is made up of first and second sub-voltage supply device 2603 and 2605, and wherein display panel 1601 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 2600 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 11 example embodiment only shows the parts relevant with the present invention.
In the 11 example embodiment, the structure of display panel 1601 is identical with the 7th example embodiment, so also no longer give unnecessary details it at this.In addition, the first sub-voltage supply device 2603 couples the strange pixel P in each row pixel 21With P 31Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to pixel P 21With P 31Compensation distribution CL.The second sub-voltage supply device 2605 couples the dual pixel P in each row pixel 22With P 32Compensation distribution CL, in order to continue and to supply burning voltage VS3 and VS4 accordingly to pixel P 22With P 32Compensation distribution CL.
Clearer, the first sub-voltage supply device 2603 has a plurality of voltage feeding unit 2603_1 and 2603_2.When the type of drive that adopts row counter-rotating (column inversion) drives display panel 1601; Then the 1st voltage feeding unit 2603_1 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 1st sweep signal SS1 (generally being produced by gate drivers), the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS1 (that is VS-) of negative polarity gives the strange pixel P in the 2nd row pixel and for example provide 21Compensation distribution CL.
In addition; The 2nd voltage feeding unit 2603_2 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 2nd sweep signal SS2, the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS2 (that is VS-) of negative polarity gives the strange pixel P in the 3rd row pixel and for example provide 31Compensation distribution CL.Wherein, The work period of the first clock signal CK1 is essentially during the picture of semitransparent and half-reflective liquid crystal display 2600 of single bug hole spacing, and second be essentially (identical during the activation of sweep signal SS1 and SS2 usually) during the activation of sweep signal SS1 or SS2 with the work period of the 3rd clock signal CK2 and XCK2.
In addition, the second sub-voltage supply device 2605 has a plurality of voltage feeding unit 2605_1 and 2605_2.When the type of drive that adopts row counter-rotating (column inversion) drives display panel 1601; Then the 1st voltage feeding unit 2605_1 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 1st sweep signal SS1, the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS3 (that is VS+) of positive polarity for example is provided the compensation distribution CL to the dual pixel P22 in the 2nd row pixel.In addition; The 2nd voltage feeding unit 2605_2 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 2nd sweep signal SS2, the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS4 (that is VS+) of positive polarity for example is provided the compensation distribution CL to the dual pixel P32 in the 3rd row pixel.
It is the voltage feeding unit 2603_1 of the 11 example embodiment and the circuit diagram of 2603_2 that Figure 27 A and Figure 27 B illustrate respectively.Please merge with reference to Figure 27 A and Figure 27 B, voltage feeding unit 2603_1 and 2603_2 all comprise a N transistor npn npn N 1, the 2nd N transistor npn npn N 2, the 3rd capacitor C 3, the 3rd N transistor npn npn N 3, the 4th N transistor npn npn N 4, the 5th N transistor npn npn N 5, and the 6th N transistor npn npn N 6Because the circuit structure of voltage feeding unit 2603_1 and 2603_2 and the relation that couples are all similar, thus below only describe with single voltage feeding unit.
With voltage feeding unit 2603_1 is example, a N transistor npn npn N 1Grid be coupled in source electrode, to receive the second clock signal CK2.The 2nd N transistor npn npn N 2Grid couple a N transistor npn npn N 1Drain electrode, the 2nd N transistor npn npn N 2Source electrode in order to receiving the burning voltage VS+ of positive polarity, and the 2nd N transistor npn npn N 2Drain electrode then be coupled to the strange pixel P in the 2nd row pixel 21Compensation distribution CL.
The 6th N transistor npn npn N 6Grid be coupled in source electrode, receiving the 3rd clock signal XCK2, and the 6th N transistor npn npn N 6Drain electrode then be coupled to a N transistor npn npn N 1Drain electrode.The 3rd N transistor npn npn N 3Grid couple the 1st sweep trace G1 receiving sweep signal SS1, and the 3rd N transistor npn npn N 3Source electrode then in order to receive the first clock signal CK1.The 3rd capacitor C 3First end couple the 3rd N transistor npn npn N 3Drain electrode, and the 3rd capacitor C 3Second end then be coupled to shared distribution CE 2
The 4th N transistor npn npn N 4Grid couple the 3rd N transistor npn npn N 3Drain electrode, the 4th N transistor npn npn N 4Source electrode in order to receiving the burning voltage VS-of negative polarity, and the 4th N transistor npn npn N 4Drain electrode then be coupled to the 2nd N transistor npn npn N 2Grid.The 5th N transistor npn npn N 5Grid couple the 3rd N transistor npn npn N 3Drain electrode, the 5th N transistor npn npn N 5Source electrode in order to receiving the burning voltage VS-of negative polarity, and the 5th N transistor npn npn N 5N 5Drain electrode then be coupled to the strange pixel P in the 2nd row pixel 21Compensation distribution CL.
It is the voltage feeding unit 2605_1 of the 11 example embodiment and the circuit diagram of 2605_2 that Figure 27 C and Figure 27 D illustrate respectively.Please merge with reference to Figure 27 C and Figure 27 D, voltage feeding unit 2605_1 and 2605_2 all comprise a N transistor npn npn N 1, the 2nd N transistor npn npn N 2, the 3rd capacitor C 3, the 3rd N transistor npn npn N 3N 3, the 4th N transistor npn npn N 4, the 5th N transistor npn npn N 5, and the 6th N transistor npn npn N 6Because the circuit structure of voltage feeding unit 2605_1 and 2605_2 and the relation that couples are all similar, thus below only describe with single voltage feeding unit.
With voltage feeding unit 2605_1 is example, a N transistor npn npn N 1Grid be coupled in source electrode, to receive the second clock signal CK2.The 2nd N transistor npn npn N 2Grid couple a N transistor npn npn N 1Drain electrode, the 2nd N transistor npn npn N 2Source electrode in order to receiving the burning voltage VS-of negative polarity, and the 2nd N transistor npn npn N 2Drain electrode then be coupled to the dual pixel P in the 2nd row pixel 22Compensation distribution CL.
The 6th N transistor npn npn N 6Grid be coupled in source electrode, receiving the 3rd clock signal XCK2, and the 6th N transistor npn npn N 6Drain electrode then be coupled to a N transistor npn npn N 1Drain electrode.The 3rd N transistor npn npn N 3Grid couple the 1st sweep trace G1 receiving sweep signal SS1, and the 3rd N transistor npn npn N 3Source electrode then in order to receive the first clock signal CK1.The 3rd capacitor C 3First end couple the 3rd N transistor npn npn N 3Drain electrode, and the 3rd capacitor C 3Second end then be coupled to shared distribution CE 2
The 4th N transistor npn npn N 4Grid couple the 3rd N transistor npn npn N 3Drain electrode, the 4th N transistor npn npn N 4Source electrode in order to receiving the burning voltage VS-of negative polarity, and the 4th N transistor npn npn N 4Drain electrode then be coupled to the 2nd N transistor npn npn N 2Grid.The 5th N transistor npn npn N 5Grid couple the 3rd N transistor npn npn N 3Drain electrode, the 5th N transistor npn npn N 5Source electrode in order to receiving the burning voltage VS+ of positive polarity, and the 5th N transistor npn npn N 5Drain electrode then be coupled to the dual pixel P in the 2nd row pixel 22Compensation distribution CL.
Figure 28 A illustrates the time sequential routine figure of the voltage feeding unit 2603_1 and the 2603_2 that are the 11 example embodiment.Please merge with reference to Figure 26, Figure 27 A, Figure 27 B and Figure 28 A, from Figure 28 A, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2603_1 3Can be switched on.Because this moment, the first and the 3rd clock signal CK1 and XCK2 were in the state of activation, and the second clock signal CK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2603_1 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2603_1 promptly can provide the burning voltage VS1 (that is VS-) of negative polarity to give the strange pixel P in the 2nd row pixel by FP during a picture 21Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2603_2 3Can be switched on.Because this moment, first and second clock signal CK1 and CK2 were in the state of activation, and the 3rd clock signal XCK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2603_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2603_2 promptly can provide the burning voltage VS2 (that is VS-) of negative polarity to give the strange pixel P in the 3rd row pixel by FP during same picture 31Compensation distribution CL.
In addition, Figure 28 B illustrates the time sequential routine figure of the voltage feeding unit 2605_1 and the 2605_2 that are the 11 example embodiment.Please merge with reference to Figure 26, Figure 27 C, Figure 27 D and Figure 28 B, from Figure 28 B, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2605_1 3Can be switched on.Because this moment, the first and the 3rd clock signal CK1 and XCK2 were in the state of activation, and the second clock signal CK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2605_1 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2605_1 promptly can provide the burning voltage VS3 (that is VS+) of positive polarity to give the dual pixel P in the 2nd row pixel by FP during same picture 22Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2605_2 3Can be switched on.Because this moment, first and second clock signal CK1 and CK2 were in the state of activation, and the 3rd clock signal XCK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2605_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2605_2 promptly can provide the burning voltage VS4 (that is VS+) of positive polarity to give the dual pixel P in the 3rd row pixel by FP during same picture 32Compensation distribution CL.
Know based on above-mentioned, because the voltage supply device that first and second sub-voltage supply device 2603 and 2605 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 21, P 22, P 31With P 32Compensation distribution CL, so as to changing each pixel P 21, P 22, P 31With P 32The voltage folder of echo area RA poor, and then adjust each pixel P 21, P 22, P 31With P 32The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 2600 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because the voltage supply device that first and second sub-voltage supply device 2603 and 2605 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 21, P 22, P 31With P 32Compensation distribution CL.Therefore, each pixel P 21, P 22, P 31With P 32The current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 2600 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[the 12 example embodiment]
Figure 29 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 2900 of the single bug hole spacing of the present invention's the 12 example embodiment.Please with reference to Figure 29; The semitransparent and half-reflective liquid crystal display 2900 of single bug hole spacing comprises display panel 1901 and the voltage supply device that is made up of first and second sub-voltage supply device 2603 and 2605, and wherein display panel 1901 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 2900 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 12 example embodiment only shows the parts relevant with the present invention.
In the 12 example embodiment, the structure of display panel 1901 is identical with the 8th example embodiment, so also no longer give unnecessary details it at this.In addition, the first sub-voltage supply device 2603 couples the odd pixel P in each row pixel 11With P 21Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to pixel P 11With P 21Compensation distribution CL.In addition, the second sub-voltage supply device 2605 couples all the dual pixel P in each row pixel 12With P 22Compensation distribution CL, in order to continue and to supply burning voltage VS3 and VS4 accordingly to pixel P 12With P 22Compensation distribution CL.
Clearer, the first sub-voltage supply device 2603 has a plurality of voltage feeding unit 2603_1 and 2603_2.When the type of drive that adopts row counter-rotating (column inversion) drives display panel 1901; Then the 1st voltage feeding unit 2603_1 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 1st sweep signal SS1 (generally being produced by gate drivers), the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS1 (that is VS-) of negative polarity gives the strange pixel P in the 1st row pixel and for example provide 11Compensation distribution CL.
In addition; The 2nd voltage feeding unit 2603_2 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 2nd sweep signal SS2, the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS2 (that is VS-) of negative polarity gives the strange pixel P in the 2nd row pixel and for example provide 21Compensation distribution CL.Wherein, The work period of the first clock signal CK1 is essentially during the picture of semitransparent and half-reflective liquid crystal display 2900 of single bug hole spacing, and second be essentially (identical during the activation of sweep signal SS1 and SS2 usually) during the activation of sweep signal SS1 or SS2 with the work period of the 3rd clock signal CK2 and XCK2.
In addition, the second sub-voltage supply device 2605 has a plurality of voltage feeding unit 2605_1 and 2605_2.When the type of drive that adopts row counter-rotating (column inversion) drives display panel 1901; Then the 1st voltage feeding unit 2605_1 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 1st sweep signal SS1, the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS3 (that is VS+) of positive polarity gives the dual pixel P in the 1st row pixel and for example provide 12Compensation distribution CL.In addition; The 2nd voltage feeding unit 2605_2 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 2nd sweep signal SS2, the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS4 (that is VS+) of positive polarity gives the dual pixel P in the 2nd row pixel and for example provide 22Compensation distribution CL.
In the 12 example embodiment, voltage feeding unit 2603_1,2603_2,2605_1 are identical with the 11 example embodiment with the circuit structure of 2605_2, so at this and no longer give unnecessary details it.
Figure 30 A illustrates the time sequential routine figure of the voltage feeding unit 2603_1 and the 2603_2 that are the 12 example embodiment.Please merge with reference to Figure 27 A, Figure 27 B, Figure 29 and Figure 30 A, from Figure 30 A, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2603_1 3Can be switched on.Because this moment, first and second clock signal CK1 and CK2 were in the state of activation, and the 3rd clock signal XCK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2603_1 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2603_1 promptly can provide the burning voltage VS1 (that is VS-) of negative polarity to give the strange pixel P in the 1st row pixel by FP during a picture 11Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2603_2 3Can be switched on.Because this moment, the first and the 3rd clock signal CK1 and XCK2 were in the state of activation, and the second clock signal CK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2603_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 26032 promptly can all provide the burning voltage VS2 (that is VS-) of negative polarity to give the strange pixel P in the 2nd row pixel by FP during same picture 21Compensation distribution CL.
In addition, Figure 30 B illustrates the time sequential routine figure of the voltage feeding unit 2605_1 and the 2605_2 that are the 12 example embodiment.Please merge with reference to Figure 27 C, Figure 27 D, Figure 29 and Figure 30 B, from Figure 30 B, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2605_1 3Can be switched on.Because this moment, first and second clock signal CK1 and CK2 were in the state of activation, and the 3rd clock signal XCK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2605_1 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2605_1 promptly can provide the burning voltage VS3 (that is VS+) of positive polarity to give the dual pixel P in the 1st row pixel by FP during same picture 12Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2605_2 3Can be switched on.Because this moment, the first and the 3rd clock signal CK1 and XCK2 were in the state of activation, and the second clock signal CK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2605_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2605_2 promptly can provide the burning voltage VS4 (that is VS+) of positive polarity to give the dual pixel P in the 2nd row pixel by FP during same picture 22Compensation distribution CL.
Know based on above-mentioned, because the voltage supply device that first and second sub-voltage supply device 2603 and 2605 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 11, P 12, P 21With P 22Compensation distribution CL, so as to changing each pixel P 11, P 12, P 21With P 22The voltage folder of echo area RA poor, and then adjust each pixel P 11, P 12, P 21With P 22The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 2900 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because the voltage supply device that first and second sub-voltage supply device 2603 and 2605 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 11, P 12, P 21With P 22Compensation distribution CL.Therefore, each pixel P 11, P 12, P 21With P 22The current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 2900 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[the 13 example embodiment]
Figure 31 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 3100 of the single bug hole spacing of the present invention's the 13 example embodiment.Please with reference to Figure 31; The semitransparent and half-reflective liquid crystal display 3100 of single bug hole spacing comprises display panel 3101 and the voltage supply device that is made up of first and second sub-voltage supply device 1603 and 1605, and wherein display panel 3101 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 3100 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 13 example embodiment only shows the parts relevant with the present invention.
Display panel 3101 comprises multi-strip scanning line G2 and G3 (only showing 2 sweep traces conveniently to do explanation), many cardinal principles and sweep trace G2 and vertically disposed data line D1 of G3 and D2 (only showing 2 data lines conveniently to do explanation), and a plurality of pixel P that are positioned at the viewing area AA of display panel 3101 21, P 22, P 31With P 32(only showing 4 pixels) conveniently to do explanation.
Pixel P 21, P 22, P 31With P 32Can electrically connect with corresponding data line and sweep trace respectively, and arrange with matrix-style.For instance, pixel P 21Electrically connect with data line D1 and sweep trace G2 respectively; Pixel P 22Electrically connect with data line D2 and sweep trace G2 respectively; Pixel P 31Electrically connect with data line D1 and sweep trace G3 respectively; And pixel P 32Electrically connect with data line D2 and sweep trace G3 respectively.In addition, pixel P 21Be expressed as the 1st pixel in the 2nd row pixel in the display panel 3101; Pixel P 22Be expressed as the 2nd pixel in the 2nd row pixel in the display panel 3101; Pixel P 31Be expressed as the 1st pixel in the 3rd row pixel in the display panel 3101; And pixel P 32Be expressed as the 2nd pixel in the 3rd row pixel in the display panel 3101.
Each pixel P 21, P 22, P 31With P 32Comprise shared distribution CE 2, auxiliary shared distribution CE 3With compensation distribution CL.Shared distribution CE 2, auxiliary shared distribution CE 3Be positioned at each pixel P for example 21, P 22, P 31With P 32Penetrating region TA in, in order to the burning voltage VS+ and the VS-of reception positive polarity out of the ordinary and negative polarity, yet do not limit to, the viewable design demand makes shared distribution CE 2, auxiliary shared distribution CE 3Receive common voltage Vcom as mentioning among the above-mentioned embodiment.Compensation distribution CL is positioned at each pixel P for example 21, P 22, P 31With P 32Echo area RA in, in order to receive burning voltage VS1～VS4 accordingly.In addition, each pixel P 21, P 22, P 31With P 32More comprise pixel transistor T, the first liquid crystal capacitance C LC1, the first storage capacitors C ST1, the second storage capacitors C ST2, first capacitor C 1, the second liquid crystal capacitance C LC2, and second capacitor C 2Because all pixel P 21, P 22, P 31With P 32Circuit structure with to couple relation all similar, so below only describe with single pixel.
With pixel P 21Be example, the grid of pixel transistor T couples sweep trace G2, and the source electrode of pixel transistor T then is coupled to data line D1.Generally speaking, the pixel electrode (pixel electrode) that electrically connects with the drain electrode of pixel transistor T with in order to receive the common electrode CE of common voltage Vcom 1Between can form the first liquid crystal capacitance C LC1, with shared distribution CE 2Between can form storage capacitors C ST1, and with auxiliary shared distribution CE 3Between can form storage capacitors C ST2
The first liquid crystal capacitance C LC1First end couple the drain electrode of pixel transistor T, and the first liquid crystal capacitance C LC1Second end then be coupled to common electrode CE.The first storage capacitors C ST1First end couple the drain electrode of pixel transistor T, and the first storage capacitors C ST1Second end then be coupled to shared distribution CE 2The second storage capacitors C ST2First end couple the drain electrode of pixel transistor T, and the second storage capacitors C ST2Second end then be coupled to auxiliary shared distribution CE 3Wherein, pixel transistor T, the first liquid crystal capacitance C LC1, the first storage capacitors C ST1And the second storage capacitors C ST2Be positioned at pixel P 21Penetrating region TA in.
In addition, first capacitor C 1First end couple the drain electrode of pixel transistor T.The second liquid crystal capacitance C LC2First end couple first capacitor C 1Second end, and the second liquid crystal capacitance C LC2Second end then be coupled to common electrode CE 1Second capacitor C 2First end couple first capacitor C 1Second end, and second capacitor C 2Second end then be coupled to compensation distribution CL.Wherein, first capacitor C 1, the second liquid crystal capacitance C LC2And second capacitor C 2Be positioned at pixel P 21Echo area RA in.
In the 13 example embodiment, voltage feeding unit 1603_1,1603_2,1605_1 are identical with the 7th example embodiment with the circuit structure of 1605_2, so at this and no longer give unnecessary details it.
Know that based on above-mentioned the different place of the 13 example embodiment and the 7th example embodiment only is each pixel P of the display panel 3101 of the 13 example embodiment 21, P 22, P 31With P 32In penetrating region TA in have two storage capacitors C ST1With C ST2, and storage capacitors C ST1With C ST2Second end can receive the burning voltage VS+ and the VS-of positive polarity and negative polarity respectively, and all the other are all identical with the 7th example embodiment.Therefore, can learn after the content that is please disclosed with reference to the 7th example embodiment about the detailed operation principle of the 13 example embodiment, so at this and no longer give unnecessary details it.
[the 14 example embodiment]
Figure 32 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 3200 of the single bug hole spacing of the present invention's the 14 example embodiment.Please with reference to Figure 32; The semitransparent and half-reflective liquid crystal display 3200 of single bug hole spacing comprises display panel 3201 and the voltage supply device that is made up of first and second sub-voltage supply device 1603 and 1605, and wherein display panel 3201 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 3200 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 14 example embodiment only shows the parts relevant with the present invention.
Display panel 3201 comprises multi-strip scanning line G1 and G2 (only showing 2 sweep traces conveniently to do explanation), many cardinal principles and sweep trace G1 and vertically disposed data line D1 of G2 and D2 (only showing 2 data lines conveniently to do explanation), and a plurality of pixel P that are positioned at the viewing area AA of display panel 3201 11, P 12, P 21With P 22(only showing 4 pixels) conveniently to do explanation.
Pixel P 11, P 12, P 21With P 22Can electrically connect with corresponding data line and sweep trace respectively, and arrange with matrix-style.For instance, pixel P 11Electrically connect with data line D1 and sweep trace G1 respectively; Pixel P 12Electrically connect with data line D2 and sweep trace G1 respectively; Pixel P 21Electrically connect with data line D1 and sweep trace G2 respectively; And pixel P 22Electrically connect with data line D2 and sweep trace G2 respectively.In addition, pixel P 11Be expressed as the 1st pixel in the 1st row pixel in the display panel 3201; Pixel P 12Be expressed as the 2nd pixel in the 1st row pixel in the display panel 3201; Pixel P 21Be expressed as the 1st pixel in the 2nd row pixel in the display panel 3201; And pixel P 22Be expressed as the 2nd pixel in the 2nd row pixel in the display panel 3201.
Each pixel P 11, P 12, P 21With P 22Comprise shared distribution CE 2, auxiliary shared distribution CE 3With compensation distribution CL.Shared distribution CE 2, auxiliary shared distribution CE 3Be positioned at each pixel P for example 11, P 12, P 21With P 22Penetrating region TA in, in order to the burning voltage VS+ and the VS-of reception positive polarity out of the ordinary and negative polarity, each pixel P 11, P 12, P 21With P 22Shared distribution CE 2, auxiliary shared distribution CE 3That transmit is the burning voltage VS+ and the VS-of positive polarity and negative polarity.Compensation distribution CL is positioned at each pixel P for example 11, P 12, P 21With P 22Echo area RA in, in order to receive burning voltage VS1～VS4 accordingly.In addition, each pixel P 11, P 12, P 21With P 22More comprise pixel transistor T, the first liquid crystal capacitance C LC1, the first storage capacitors C ST1, the second storage capacitors C ST2, first capacitor C 1, the second liquid crystal capacitance C LC2, and second capacitor C 2Because all pixel P 11, P 12, P 21With P 22Circuit structure with to couple relation all similar, so below only describe with single pixel.
With pixel P 11Be example, the grid of pixel transistor T couples sweep trace G1, and the source electrode of pixel transistor T then is coupled to data line D1.Generally speaking, the pixel electrode (pixel electrode) that electrically connects with the drain electrode of pixel transistor T with in order to receive the common electrode CE of common voltage Vcom 1Between can form the first liquid crystal capacitance C LC1, with shared distribution CE 2Between can form storage capacitors C ST1, and with auxiliary shared distribution CE 3Between can form storage capacitors C ST2
The first liquid crystal capacitance C LC1First end couple the drain electrode of pixel transistor T, and the first liquid crystal capacitance C LC1Second end then be coupled to common electrode CE.The first storage capacitors C ST1First end couple the drain electrode of pixel transistor T, and the first storage capacitors C ST1Second end then be coupled to shared distribution CE 2The second storage capacitors C ST2First end couple the drain electrode of pixel transistor T, and the second storage capacitors C ST2Second end then be coupled to auxiliary shared distribution CE 3Wherein, pixel transistor T, the first liquid crystal capacitance C LC1, the first storage capacitors C ST1And the second storage capacitors C ST2Be positioned at pixel P 11Penetrating region TA in.
In addition, first capacitor C 1First end couple the drain electrode of pixel transistor T.The second liquid crystal capacitance C LC2First end couple first capacitor C 1Second end, and the second liquid crystal capacitance C LC2Second end then be coupled to common electrode CE 1Second capacitor C 2First end couple first capacitor C 1Second end, and second capacitor C 2Second end then be coupled to compensation distribution CL.Wherein, first capacitor C 1, the second liquid crystal capacitance C LC2And second capacitor C 2Be positioned at pixel P 11Echo area RA in.
In the 14 example embodiment, voltage feeding unit 1603_1,1603_2,1605_1 are identical with the 7th example embodiment with the circuit structure of 1605_2, so at this and no longer give unnecessary details it.
Know that based on above-mentioned the different place of the 14 example embodiment and the 8th example embodiment only is each pixel P of the display panel 3201 of the 14 example embodiment 11, P 12, P 21With P 22In penetrating region TA in have two storage capacitors C ST1With C ST2, and storage capacitors C ST1With C ST2Second end can receive the burning voltage VS+ and the VS-of positive polarity and negative polarity respectively, and all the other are all identical with the 8th example embodiment.Therefore, can learn after please merging the content that is disclosed with reference to the 7th and the 8th example embodiment about the detailed operation principle of the 14 example embodiment, so also no longer give unnecessary details it at this.
[the 15 example embodiment]
Figure 33 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 3300 of the single bug hole spacing of the present invention's the 15 example embodiment.Please with reference to Figure 33; The semitransparent and half-reflective liquid crystal display 3300 of single bug hole spacing comprises display panel 3101 and the voltage supply device that is made up of first and second sub-voltage supply device 2103 and 2105, and wherein display panel 3101 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 3300 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 15 example embodiment only shows the parts relevant with the present invention.
In the 15 example embodiment, the structure of display panel 3101 is identical with the 13 example embodiment, so also no longer give unnecessary details it at this.In addition, the circuit structure of voltage feeding unit 2103_1,2103_2,2105_1 and 2105_2 is identical with the 9th example embodiment, so also no longer give unnecessary details it at this.
Know that based on above-mentioned the different place of the 15 example embodiment and the 9th example embodiment only is each pixel P of the display panel 3101 of the 15 example embodiment 21, P 22, P 31With P 32In penetrating region TA in have two storage capacitors C ST1With C ST2, and storage capacitors C ST1With C ST2Second end can receive the burning voltage VS+ and the VS-of positive polarity and negative polarity respectively, and all the other are all identical with the 9th example embodiment.Therefore, can learn after please merging the content that is disclosed with reference to the 9th example embodiment about the detailed operation principle of the 15 example embodiment, so at this and no longer give unnecessary details it.
[the 16 example embodiment]
Figure 34 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 3400 of the single bug hole spacing of the present invention's the 16 example embodiment.Please with reference to Figure 34; The semitransparent and half-reflective liquid crystal display 3400 of single bug hole spacing comprises display panel 3201 and the voltage supply device that is made up of first and second sub-voltage supply device 2103 and 2105, and wherein display panel 3201 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 3400 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 16 example embodiment only shows the parts relevant with the present invention.
In the 16 example embodiment, the structure of display panel 3201 is identical with the 14 example embodiment, so also no longer give unnecessary details it at this.In addition, the circuit structure of voltage feeding unit 2103_1,2103_2,2105_1 and 2105_2 is identical with the 9th example embodiment, so also no longer give unnecessary details it at this.
Know that based on above-mentioned the different place of the 16 example embodiment and the tenth example embodiment only is each pixel P of the display panel 3201 of the 16 example embodiment 11, P 12, P 21With P 22In penetrating region TA in have two storage capacitors C ST1With C ST2, and storage capacitors C ST1With C ST2Second end can receive the burning voltage VS+ and the VS-of positive polarity and negative polarity respectively, and all the other are all identical with the tenth example embodiment.Therefore, can learn after please merging the content that is disclosed with reference to the 9th and the tenth example embodiment about the detailed operation principle of the 16 example embodiment, so also no longer give unnecessary details it at this.
[the 17 example embodiment]
Figure 35 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 3500 of the single bug hole spacing of the present invention's the 17 example embodiment.Please with reference to Figure 35; The semitransparent and half-reflective liquid crystal display 3500 of single bug hole spacing comprises display panel 3101 and the voltage supply device that is made up of first and second sub-voltage supply device 2603 and 2605, and wherein display panel 3101 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 3500 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 17 example embodiment only shows the parts relevant with the present invention.
In the 17 example embodiment, the structure of display panel 3101 is identical with the 13 example embodiment, so also no longer give unnecessary details it at this.In addition, voltage feeding unit 2603_1,2603_2,2605_1 are identical with the 11 example embodiment with the circuit structure of 2605_2, so also no longer give unnecessary details at this.
Know that based on above-mentioned the different place of the 17 example embodiment and the 11 example embodiment only is each pixel P of the display panel 3101 of the 17 example embodiment 21, P 22, P 31With P 32In penetrating region TA in have two storage capacitors C ST1With C ST2, and storage capacitors C ST1With C ST2Second end can receive the burning voltage VS+ and the VS-of positive polarity and negative polarity respectively, and all the other are all identical with the 11 example embodiment.Therefore, can learn after please merging the content that is disclosed with reference to the 11 example embodiment about the detailed operation principle of the 17 example embodiment, so at this and no longer give unnecessary details it.
[the 18 example embodiment]
Figure 36 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 3600 of the single bug hole spacing of the present invention's the 18 example embodiment.Please with reference to Figure 36; The semitransparent and half-reflective liquid crystal display 3600 of single bug hole spacing comprises display panel 3201 and the voltage supply device that is made up of first and second sub-voltage supply device 2603 and 2605, and wherein display panel 3201 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 3600 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 18 example embodiment only shows the parts relevant with the present invention.
In the 18 example embodiment, the structure of display panel 3201 is identical with the 14 example embodiment, so also no longer give unnecessary details it at this.In addition, voltage feeding unit 2603_1,2603_2,2605_1 are identical with the 11 example embodiment with the circuit structure of 2605_2, so also no longer give unnecessary details it at this.
Know that based on above-mentioned the different place of the 18 example embodiment and the 12 example embodiment only is each pixel P of the display panel 3201 of the 18 example embodiment 11, P 12, P 21With P 22In penetrating region TA in have two storage capacitors C ST1With C ST2, and storage capacitors C ST1With C ST2Second end can receive the burning voltage VS+ and the VS-of positive polarity and negative polarity respectively, and all the other are all identical with the 12 example embodiment.Therefore, can learn after please merging the content that is disclosed with reference to the 11 and the 12 example embodiment about the detailed operation principle of the 18 example embodiment, so also no longer give unnecessary details it at this.
[the 19 example embodiment]
Figure 37 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 3700 of the single bug hole spacing of the present invention's the 19 example embodiment.Please with reference to Figure 37; The semitransparent and half-reflective liquid crystal display 3700 of single bug hole spacing comprises display panel 3701 and the voltage supply device that is made up of first and second sub-voltage supply device 1603 and 1605, and wherein display panel 3701 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 3700 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 19 example embodiment only shows the parts relevant with the present invention.
Display panel 3701 comprises multi-strip scanning line G2 and G3 (only showing 2 sweep traces conveniently to do explanation), many cardinal principles and sweep trace G2 and vertically disposed data line D1 of G3 and D2 (only showing 2 data lines conveniently to do explanation), and a plurality of pixel P that are positioned at the viewing area AA of display panel 3701 21, P 22P 22, P 31With P 32(only showing 4 pixels) conveniently to do explanation.
Pixel P 21, P 22, P 31With P 32Can electrically connect with corresponding data line and sweep trace respectively, and arrange with matrix-style.For instance, pixel P 21Electrically connect with data line D1 and sweep trace G2 respectively; Pixel P 22Electrically connect with data line D2 and sweep trace G2 respectively; Pixel P 31Electrically connect with data line D1 and sweep trace G3 respectively; And pixel P 32Electrically connect with data line D2 and sweep trace G3 respectively.In addition, pixel P 21Be expressed as the 1st pixel in the 2nd row pixel in the display panel 3701; Pixel P 22Be expressed as the 2nd pixel in the 2nd row pixel in the display panel 3701; Pixel P 31Be expressed as the 1st pixel in the 3rd row pixel in the display panel 3701; And pixel P 32Be expressed as the 2nd pixel in the 3rd row pixel in the display panel 3701.
Each pixel P 21P 21, P 22, P 31With P 32Comprise shared distribution CE 2With compensation distribution CL.Shared distribution CE 2Be positioned at each pixel P for example 21, P 22, P 31With P 32Penetrating region TA in, in order to receive common voltage Vcom.Compensation distribution CL is positioned at each pixel P for example 21, P 22, P 31With P 32Echo area RA in, in order to receive burning voltage VS1～VS4 accordingly.In addition, each pixel P 21, P 22, P 31With P 32More comprise pixel transistor T, the first liquid crystal capacitance C LC1, storage capacitors C ST, first capacitor C 1, the second liquid crystal capacitance C LC2, and second capacitor C 2Because all pixel P 21, P 22, P 31With P 32Circuit structure with to couple relation all similar, so below only describe with single pixel.
With pixel P 21Be example, the grid of pixel transistor T couples sweep trace G2, and the source electrode of pixel transistor T then is coupled to data line D1.Generally speaking, the pixel electrode (pixel electrode) that electrically connects with the drain electrode of pixel transistor T with in order to receive the common electrode CE of common voltage Vcom 1Between can form the first liquid crystal capacitance C LC1, and with shared distribution CE 2Between can form storage capacitors C ST
The first liquid crystal capacitance C LC1First end couple the drain electrode of pixel transistor T, and the first liquid crystal capacitance C LC1Second end then be coupled to common electrode CE 1Storage capacitors C STFirst end couple the drain electrode of pixel transistor T, and storage capacitors C STSecond end then be coupled to shared distribution CE 2Wherein, pixel transistor T, the first liquid crystal capacitance C LC1And storage capacitors C STBe positioned at pixel P 21Penetrating region TA in.
In addition, first capacitor C 1First end couple the drain electrode of pixel transistor T.The second liquid crystal capacitance C LC2First end couple first capacitor C 1Second end, and the second liquid crystal capacitance C LC2Second end then be coupled to common electrode CE 1Second capacitor C 2First end couple first capacitor C 1Second end, and second capacitor C 2Second end then be coupled to compensation distribution CL.Wherein, first capacitor C 1, the second liquid crystal capacitance C LC2And second capacitor C 2Be positioned at pixel P 21Echo area RA in.
In the 19 example embodiment, the first sub-voltage supply device 1603 couples the strange pixel P in the 2nd row pixel 21With the dual pixel P in the 3rd row pixel 32Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to pixel P 21With P 32Compensation distribution CL.In addition, the second sub-voltage supply device 1605 couples the dual pixel P in the 2nd row pixel 22With the strange pixel P in the 3rd row pixel 31Compensation distribution CL, in order to continue and to supply burning voltage VS3 and VS4 accordingly to pixel P 22With P 31Compensation distribution CL.
Clearer, the first sub-voltage supply device 1603 has a plurality of voltage feeding unit 1603_1 and 1603_2.When the type of drive that adopts some counter-rotating (dot inversion) drives display panel 3701; Then the 1st voltage feeding unit 1603_1 can (for example be produced by time schedule controller according to first and second clock signal CK and the XCK of the 1st sweep signal SS1 (generally being produced by gate drivers) and phase differential 180 degree; But be not restricted to this), the burning voltage VS1 (that is VS+) of positive polarity gives the strange pixel P in the 2nd row pixel and for example provide 21Compensation distribution CL.
In addition, the 2nd voltage feeding unit 1603_2 can be according to first and second clock signal CK and the XCK of the 2nd sweep signal SS2 and phase differential 180 degree, and the burning voltage VS2 (that is VS+) of positive polarity gives the dual pixel P in the 3rd row pixel and for example provide 32Compensation distribution CL.Wherein, the work period of first and second clock signal CK and XCK (duty cycle) is essentially (frame period) during the picture of semitransparent and half-reflective liquid crystal display 3700 of single bug hole spacing.
In addition, the second sub-voltage supply device 1605 has a plurality of voltage feeding unit 1605_1 and 1605_2.When the type of drive that adopts some counter-rotating (dot inversion) drives display panel 3701; Then the 1st voltage feeding unit 1605_1 can be according to first and second clock signal CK and the XCK of the 1st sweep signal SS1 and phase differential 180 degree, and the burning voltage VS3 (that is VS-) of negative polarity gives the dual pixel P in the 2nd row pixel and for example provide 22Compensation distribution CL.In addition, the 2nd voltage feeding unit 1605_2 can be according to first and second clock signal CK and the XCK of the 2nd sweep signal SS2 and phase differential 180 degree, and the burning voltage VS4 (that is VS-) of negative polarity gives the strange pixel P in the 3rd row pixel and for example provide 31Compensation distribution CL.
In the 19 example embodiment, voltage feeding unit 1603_1,1603_2,1605_1 are identical with the 7th example embodiment with the circuit structure of 1605_2, so at this and no longer give unnecessary details it.
In addition, Figure 38 A illustrates the time sequential routine figure of the voltage feeding unit 1603_1 and the 1603_2 that are the 19 example embodiment.Please merge with reference to Figure 17 A, Figure 17 B, Figure 37 and Figure 38 A, from Figure 38 A, can know and find out, when sweep signal SS1 activation, the N transistor npn npn N in the voltage feeding unit 1603_1 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK was in the state of activation, and the second clock signal XCK is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 1603_1 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 1603_1 promptly can provide the burning voltage VS1 (that is VS+) of positive polarity to give the strange pixel P in the 2nd row pixel by FP during a picture 21Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the N transistor npn npn N in the voltage feeding unit 1603_2 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK still was in the state of activation, and the second clock signal XCK still is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 1603_2 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 1603_2 promptly can provide the burning voltage VS2 (that is VS+) of positive polarity to give the dual pixel P in the 3rd row pixel by FP during same picture 32Compensation distribution CL.
Figure 38 B illustrates the time sequential routine figure of the voltage feeding unit 1605_1 and the 1605_2 that are the 19 example embodiment.Please merge with reference to Figure 17 C, Figure 17 D, Figure 37 and Figure 38 B, from Figure 38 B, can know and find out, when sweep signal SS1 activation, the N transistor npn npn N in the voltage feeding unit 1605_1 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK was in the state of activation, and the second clock signal XCK is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 1605_1 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 1605_1 promptly can provide the burning voltage VS3 (that is VS-) of negative polarity to give the dual pixel P in the 2nd row pixel by FP during same picture 22Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the N transistor npn npn N in the voltage feeding unit 1605_2 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK still was in the state of activation, and the second clock signal XCK still is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 1605_2 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 1605_2 promptly can provide the burning voltage VS4 (that is VS-) of negative polarity to give the strange pixel P in the 3rd row pixel by FP during same picture 31Compensation distribution CL.
Know based on above-mentioned, because the voltage supply device that first and second sub-voltage supply device 1603 and 1605 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 21, P 22, P 31With P 32Compensation distribution CL, so as to changing each pixel P 21, P 22, P 31With P 32The voltage folder of echo area RA poor, and then adjust each pixel P 21, P 22, P 31With P 32The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 3700 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because the voltage supply device that first and second sub-voltage supply device 1603 and 1605 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 21, P 22, P 31With P 32Compensation distribution CL.Therefore, each pixel P 21, P 22, P 31With P 32Echo area RA in the current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 3700 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[the 20 example embodiment]
Figure 39 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 3900 of the single bug hole spacing of the present invention's the 20 example embodiment.Please with reference to Figure 39; The semitransparent and half-reflective liquid crystal display 3900 of single bug hole spacing comprises display panel 3901 and the voltage supply device that is made up of first and second sub-voltage supply device 1603 and 1605, and wherein display panel 3901 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 3900 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 20 example embodiment only shows the parts relevant with the present invention.
Display panel 3901 comprises multi-strip scanning line G1 and G2 (only showing 2 sweep traces conveniently to do explanation), many cardinal principles and sweep trace G1 and vertically disposed data line D1 of G2 and D2 (only showing 2 data lines conveniently to do explanation), and a plurality of pixel P that are positioned at the viewing area AA of display panel 3901 11, P 12, P 21With P 22(only showing 4 pixels) conveniently to do explanation.
Pixel P 11, P 12, P 21With P 22Can electrically connect with corresponding data line and sweep trace respectively, and arrange with matrix-style.For instance, pixel P 11Electrically connect with data line D1 and sweep trace G1 respectively; Pixel P 12Electrically connect with data line D2 and sweep trace G1 respectively; Pixel P 21Electrically connect with data line D1 and sweep trace G2 respectively; And pixel P 22Electrically connect with data line D2 and sweep trace G2 respectively.In addition, pixel P 11Be expressed as the 1st pixel in the 1st row pixel in the display panel 3901; Pixel P 12Be expressed as the 2nd pixel in the 1st row pixel in the display panel 3901; Pixel P 21Be expressed as the 1st pixel in the 2nd row pixel in the display panel 3901; And pixel P 22Be expressed as the 2nd pixel in the 2nd row pixel in the display panel 3901.
Each pixel P 11, P 12, P 21With P 22Comprise shared distribution CE 2With compensation distribution CL.Shared distribution CE 2Be positioned at each pixel P for example 11, P 12, P 21With P 22Penetrating region TA in, in order to transmit common voltage Vcom.Compensation distribution CL is positioned at each pixel P for example 11, P 12, P 21With P 22Echo area RA in, in order to transmit burning voltage VS1～VS4 accordingly.In addition, each pixel P 11, P 12, P 21With P 22More comprise pixel transistor T, the first liquid crystal capacitance C LC1, storage capacitors C ST, first capacitor C 1, the second liquid crystal capacitance C LC2, and second capacitor C 2Because all pixel P 11, P 12, P 21With P 22Circuit structure with to couple relation all similar, so below only describe with single pixel.
With pixel P 11Be example, the grid of pixel transistor T couples sweep trace G1, and the source electrode of pixel transistor T then is coupled to data line D1.Generally speaking, the pixel electrode (pixel electrode) that electrically connects with the drain electrode of pixel transistor T with in order to receive the common electrode CE of common voltage Vcom 1Between can form the first liquid crystal capacitance C LC1, and with shared distribution CE 2Between can form storage capacitors C ST
The first liquid crystal capacitance C LC1First end couple the drain electrode of pixel transistor T, and the first liquid crystal capacitance C LC1Second end then be coupled to common electrode CE 1Storage capacitors C STFirst end couple the drain electrode of pixel transistor T, and storage capacitors C STSecond end then be coupled to shared distribution CE 2Wherein, pixel transistor T, the first liquid crystal capacitance C LC1And storage capacitors C STBe positioned at pixel P 11Penetrating region TA in.
In addition, first capacitor C 1First end couple the drain electrode of pixel transistor T.The second liquid crystal capacitance C LC2First end couple first capacitor C 1Second end, and the second liquid crystal capacitance C LC2Second end then be coupled to common electrode CE 1Second capacitor C 2First end couple first capacitor C 1Second end, and second capacitor C 2Or the like second end then be coupled to compensation distribution CL.Wherein, first capacitor C 1, the second liquid crystal capacitance C LC2And second capacitor C 2Be positioned at pixel P 11Echo area RA in.
In the 20 example embodiment, the first sub-voltage supply device 1603 couples the strange pixel P in the 1st row pixel 11With the dual pixel P in the 2nd row pixel 22Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to pixel P 11With P 22Compensation distribution CL.In addition, the second sub-voltage supply device 1605 couples the dual pixel P in the 1st row pixel 12With the strange pixel P in the 2nd row pixel 21Compensation distribution CL, in order to continue and to supply burning voltage VS3 and VS4 accordingly to pixel P 12With P 21Compensation distribution CL.
Clearer, the first sub-voltage supply device 1603 has a plurality of voltage feeding unit 1603_1 and 1603_2.When the type of drive that adopts some counter-rotating (dot inversion) drives display panel 3901; Then the 1st voltage feeding unit 1603_1 can (for example be produced by time schedule controller according to first and second clock signal CK and the XCK of the 1st sweep signal SS1 (generally being produced by gate drivers) and phase differential 180 degree; But be not restricted to this), the burning voltage VS1 (that is VS+) of positive polarity gives the strange pixel P in the 1st row pixel and for example provide 11Compensation distribution CL.
In addition, the 2nd voltage feeding unit 1603_2 can be according to first and second clock signal CK and the XCK of the 2nd sweep signal SS2 and phase differential 180 degree, and the burning voltage VS2 (that is VS+) of positive polarity gives the dual pixel P in the 2nd row pixel and for example provide 22Compensation distribution CL.Wherein, the work period of first and second clock signal CK and XCK (duty cycle) is essentially during the picture of semitransparent and half-reflective liquid crystal display 3900 of single bug hole spacing.
In addition, the second sub-voltage supply device 1605 has a plurality of voltage feeding unit 1605_1 and 1605_2.When the type of drive that adopts some counter-rotating (dot inversion) drives display panel 3901; Then the 1st voltage feeding unit 1605_1 can be according to first and second clock signal CK and the XCK of the 1st sweep signal SS1 and phase differential 180 degree, and the burning voltage VS3 (that is VS-) of negative polarity gives the dual pixel P in the 1st row pixel and for example provide 12Compensation distribution CL.In addition, the 2nd voltage feeding unit 1605_2 can be according to first and second clock signal CK and the XCK of the 2nd sweep signal SS2 and phase differential 180 degree, and the burning voltage VS4 (that is VS-) of negative polarity gives the strange pixel P in the 2nd row pixel and for example provide 21Compensation distribution CL.
In the 20 example embodiment, voltage feeding unit 1603_1,1603_2,1605_1 are identical with the 7th example embodiment with the circuit structure of 1605_2, so at this and no longer give unnecessary details it.
In addition, Figure 40 A illustrates the time sequential routine figure of the voltage feeding unit 1603_1 and the 1603_2 that are the 20 example embodiment.Please merge with reference to Figure 17 A, Figure 17 B, Figure 39 and Figure 40 A, from Figure 40 A, can know and find out, when sweep signal SS1 activation, the N transistor npn npn N in the voltage feeding unit 1603_1 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK was in the state of activation, and the second clock signal XCK is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 1603_1 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 1603_1 promptly can provide the burning voltage VS1 (that is VS+) of positive polarity to give the strange pixel P in the 1st row pixel by FP during a picture 11Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the N transistor npn npn N in the voltage feeding unit 1603_2 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK still was in the state of activation, and the second clock signal XCK still is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 1603_2 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 1603_2 promptly can provide the burning voltage VS2 (that is VS+) of positive polarity to give the dual pixel P in the 2nd row pixel by FP during same picture 22Compensation distribution CL.
Figure 40 B illustrates the time sequential routine figure of the voltage feeding unit 1605_1 and the 1605_2 that are the 20 example embodiment.Please merge with reference to Figure 17 C, Figure 17 D, Figure 39 and Figure 40 B, from Figure 40 B, can know and find out, when sweep signal SS1 activation, the N transistor npn npn N in the voltage feeding unit 1605_1 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK was in the state of activation, and the second clock signal XCK is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 1605_1 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 1605_1 promptly can provide the burning voltage VS3 (that is VS-) of negative polarity to give the dual pixel P in the 1st row pixel by FP during same picture 12Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the N transistor npn npn N in the voltage feeding unit 1605_2 1With the 3rd N transistor npn npn N 3Can be switched on.Because this moment, the first clock signal CK still was in the state of activation, and the second clock signal XCK still is in the state of forbidden energy.Therefore, the 2nd N transistor npn npn N in the voltage feeding unit 1605_2 2Can be switched on, and the 4th N transistor npn npn N 4Can be ended.Thus, voltage feeding unit 1605_2 promptly can provide the burning voltage VS4 (that is VS-) of negative polarity to give the strange pixel P in the 2nd row pixel by FP during same picture 21Compensation distribution CL.
Know based on above-mentioned, because the voltage supply device that first and second sub-voltage supply device 1603 and 1605 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 11, P 12, P 21With P 22Compensation distribution CL, so as to changing each pixel P 11, P 12, P 21With P 22The voltage folder of echo area RA poor, and then adjust each pixel P 11, P 12, P 21With P 22The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 3900 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because the voltage supply device that first and second sub-voltage supply device 1603 and 1605 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 11, P 12, P 21With P 22Compensation distribution CL.Therefore, each pixel P 11, P 12, P 21With P 22The current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 3900 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[the 21 example embodiment]
Figure 41 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 4100 of the single bug hole spacing of the present invention's the 21 example embodiment.Please with reference to Figure 41; The semitransparent and half-reflective liquid crystal display 4100 of single bug hole spacing comprises display panel 3701 and the voltage supply device that is made up of first and second sub-voltage supply device 2103 and 2105, and wherein display panel 3701 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 4100 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 21 example embodiment only shows the parts relevant with the present invention.
In the 21 example embodiment, the structure of display panel 3701 is identical with the 19 example embodiment, so also no longer give unnecessary details it at this.In addition, the first sub-voltage supply device 2103 couples the strange pixel P in the 2nd row pixel 21With the dual pixel P in the 3rd row pixel 32Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to pixel P 21With P 32Compensation distribution CL.In addition, the second sub-voltage supply device 2105 couples the dual pixel P in the 2nd row pixel 22With the strange pixel P in the 3rd row pixel 31Compensation distribution CL, in order to continue and to supply burning voltage VS3 and VS4 accordingly to pixel P 22With P 31Compensation distribution CL.
Clearer, the first sub-voltage supply device 2103 has a plurality of voltage feeding unit 2103_1 and 2103_2.When the type of drive that adopts the some counter-rotating drives display panel 3701; Then the 1st voltage feeding unit 2103_1 can (for example be produced by time schedule controller according to the 1st sweep signal SS1 (generally being produced by gate drivers) and first and second clock signal CK1 and CK2; But be not restricted to this), the burning voltage VS1 (that is VS-) of negative polarity gives the strange pixel P in the 2nd row pixel and for example provide 21Compensation distribution CL.
In addition, the 2nd voltage feeding unit 2103_2 can be according to the 2nd sweep signal SS2 and first and second clock signal CK1 and CK2, and the burning voltage VS2 (that is VS-) of negative polarity gives the dual pixel P in the 3rd row pixel and for example provide 32Compensation distribution CL.Wherein, the work period of the first clock signal CK1 is essentially during the picture of semitransparent and half-reflective liquid crystal display 4100 of single bug hole spacing, and the second clock signal CK2 then continues to maintain the state of activation.
In addition, the second sub-voltage supply device 2105 has a plurality of voltage feeding unit 2105_1 and 2105_2.When the type of drive that adopts the some counter-rotating drives display panel 3701; Then the 1st voltage feeding unit 2105_1 can be according to the 1st sweep signal SS1 and first and second clock signal CK1 and CK2, and the burning voltage VS3 (that is VS+) of positive polarity gives the dual pixel P in the 2nd row pixel and for example provide 22Compensation distribution CL.In addition, the 2nd voltage feeding unit 2105_2 can be according to the 2nd sweep signal SS2 and first and second clock signal CK1 and CK2, and the burning voltage VS4 (that is VS+) of positive polarity gives the strange pixel P in the 3rd row pixel and for example provide 31Compensation distribution CL.
In the 21 example embodiment, the circuit structure of voltage feeding unit 2103_1,2103_2,2105_1 and 2105_2 is identical with the 9th example embodiment, so also no longer give unnecessary details it at this.
In addition, Figure 42 A illustrates the time sequential routine figure of the voltage feeding unit 2103_1 and the 2103_2 that are the 21 example embodiment.Please merge with reference to Figure 22 A, Figure 22 B, Figure 41 and Figure 42 A, from Figure 42 A, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2103_1 3Can be switched on.Because this moment, the first clock signal CK1 was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2103_1 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2103_1 promptly can provide the burning voltage VS1 (that is VS-) of negative polarity to give the strange pixel P in the 2nd row pixel by FP during a picture 21Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2103_2 3Can be switched on.Because this moment, the first clock signal CK1 still was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2103_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2103_2 promptly can provide the burning voltage VS2 (that is VS-) of negative polarity to give the dual pixel P in the 3rd row pixel by FP during same picture 32Compensation distribution CL.
In addition, Figure 42 B illustrates the time sequential routine figure of the voltage feeding unit 2105_1 and the 2105_2 that are the 21 example embodiment.Please merge with reference to Figure 22 C, Figure 22 D, Figure 41 and Figure 42 B, from Figure 42 B, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2105_1 3Can be switched on.Because this moment, the first clock signal CK1 was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2105_1 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2105_1 promptly can provide the burning voltage VS3 (that is VS+) of positive polarity to give the dual pixel P in the 2nd row pixel by FP during same picture 22Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2105_2 3Can be switched on.Because this moment, the first clock signal CK1 still was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2105_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2105_2 promptly can provide the burning voltage VS4 (that is VS+) of positive polarity to give the strange pixel P in the 3rd row pixel by FP during same picture 31Compensation distribution CL.
Know based on above-mentioned, because the voltage supply device that first and second sub-voltage supply device 2103 and 2105 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 21, P 22, P 31With P 32Compensation distribution CL, so as to changing each pixel P 21, P 22, P 31With P 32The voltage folder of echo area RA poor, and then adjust each pixel P 21, P 22, P 31With P 32The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 4100 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because the voltage supply device that first and second sub-voltage supply device 2103 and 2105 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 21, P 22, P 31With P 32Compensation distribution CL.Therefore, each pixel P 21, P 22, P 31With P 32The current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 4100 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[the 22 example embodiment]
Figure 43 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 4300 of the single bug hole spacing of the present invention's the 22 example embodiment.Please with reference to Figure 43; The semitransparent and half-reflective liquid crystal display 4300 of single bug hole spacing comprises display panel 3901 and the voltage supply device that is made up of first and second sub-voltage supply device 2103 and 2105, and wherein display panel 3901 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 4300 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 22 example embodiment only shows the parts relevant with the present invention.
In the 22 example embodiment, the structure of display panel 3901 is identical with the 20 example embodiment, so also no longer give unnecessary details it at this.In addition, the first sub-voltage supply device 2103 couples the strange pixel P in the 1st row pixel 11With the dual pixel P in the 2nd row pixel 22Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to pixel P 11With P 22Compensation distribution CL.In addition, the second sub-voltage supply device 2105 couples the dual pixel P in the 1st row pixel 12With the strange pixel P in the 2nd row pixel 21Compensation distribution CL, in order to continue and to supply burning voltage VS3 and VS4 accordingly to pixel P 12With P 21Compensation distribution CL.
Clearer, the first sub-voltage supply device 2103 has a plurality of voltage feeding unit 2103_1 and 2103_2.When the type of drive that adopts the some counter-rotating drives display panel 3901; Then the 1st voltage feeding unit 2103_1 can (for example be produced by time schedule controller according to the 1st sweep signal SS1 (generally being produced by gate drivers) and first and second clock signal CK1 and CK2; But be not restricted to this), the burning voltage VS1 (that is VS+) of positive polarity gives the strange pixel P in the 1st row pixel and for example provide 11Compensation distribution CL.
In addition, the 2nd voltage feeding unit 2103_2 can be according to the 2nd sweep signal SS2 and first and second clock signal CK1 and CK2, and the burning voltage VS2 (that is VS+) of positive polarity gives the dual pixel P in the 2nd row pixel and for example provide 22Compensation distribution CL.Wherein, the work period of the first clock signal CK1 is essentially during the picture of semitransparent and half-reflective liquid crystal display 4300 of single bug hole spacing, and the second clock signal CK2 then continues to maintain the state of activation.
In addition, the second sub-voltage supply device 2105 has a plurality of voltage feeding unit 2105_1 and 2105_2.When the type of drive that adopts the some counter-rotating drives display panel 3901; Then the 1st voltage feeding unit 2105_1 can be according to the 1st sweep signal SS1 and first and second clock signal CK1 and CK2, and the burning voltage VS3 (that is VS-) of negative polarity gives the dual pixel P in the 1st row pixel and for example provide 12Compensation distribution CL.In addition, the 2nd voltage feeding unit 2105_2 can be according to the 2nd sweep signal SS2 and first and second clock signal CK1 and CK2, and the burning voltage VS4 (that is VS-) of negative polarity gives the strange pixel P in the 2nd row pixel and for example provide 21Compensation distribution CL.
In the 22 example embodiment, the circuit structure of voltage feeding unit 2103_1,2103_2,2105_1 and 2105_2 is identical with the 9th example embodiment, so also no longer give unnecessary details it at this.
In addition, Figure 44 A illustrates the time sequential routine figure of the voltage feeding unit 2103_1 and the 2103_2 that are the 22 example embodiment.Please merge with reference to Figure 22 A, Figure 22 B, Figure 43 and Figure 44 A, from Figure 44 A, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2103_1 3Can be switched on.Because this moment, the first clock signal CK1 was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2103_1 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2103_1 promptly can provide the burning voltage VS1 (that is VS+) of positive polarity to give the strange pixel P in the 1st row pixel by FP during a picture 11Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2103_2 3Can be switched on.Because this moment, the first clock signal CK1 still was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2103_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2103_2 promptly can provide the burning voltage VS2 (that is VS+) of positive polarity to give the dual pixel P in the 2nd row pixel by FP during same picture 22Compensation distribution CL.
In addition, Figure 44 B illustrates the time sequential routine figure of the voltage feeding unit 2503-1 and the 2503-2 that are the 22 example embodiment.Please merge with reference to Figure 22 C, Figure 22 D, Figure 43 and Figure 44 B, from Figure 44 B, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2105_1 3Can be switched on.Because this moment, the first clock signal CK1 was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2105_1 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2105_1 promptly can provide the burning voltage VS3 (that is VS-) of negative polarity to give the dual pixel P in the 1st row pixel by FP during same picture 12Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2105_2 3Can be switched on.Because this moment, the first clock signal CK1 still was in the state of activation, and the second clock signal CK2 continues to maintain the state of activation.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2105_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2105_2 promptly can provide the burning voltage VS4 (that is VS-) of negative polarity to give the strange pixel P in the 2nd row pixel by FP during same picture 21Compensation distribution CL.
Know based on above-mentioned, because the voltage supply device that first and second sub-voltage supply device 2103 and 2105 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 11, P 12, P 21With P 22Compensation distribution CL, so as to changing each pixel P 11, P 12, P 21With P 22The voltage folder of echo area RA poor, and then adjust each pixel P 11, P 12, P 21With P 22The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 4300 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because the voltage supply device that first and second sub-voltage supply device 2103 and 2105 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 11, P 12, P 21With P 22Compensation distribution CL.Therefore, each pixel P 11, P 12, P 21With P 22The current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 4300 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[the 23 example embodiment]
Figure 45 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 4500 of the single bug hole spacing of the present invention's the 23 example embodiment.Please with reference to Figure 45; The semitransparent and half-reflective liquid crystal display 4500 of single bug hole spacing comprises display panel 3701 and the voltage supply device that is made up of first and second sub-voltage supply device 2603 and 2605, and wherein display panel 3701 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 4500 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 23 example embodiment only shows the parts relevant with the present invention.
In the 23 example embodiment, the structure of display panel 3701 is identical with the 19 example embodiment, so also no longer give unnecessary details it at this.In addition, the first sub-voltage supply device 2603 couples the strange pixel P in the 2nd row pixel 21With the dual pixel P in the 3rd row pixel 32Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to pixel P 21With P 32Compensation distribution CL.The second sub-voltage supply device 2605 couples the dual pixel P in the 2nd row pixel 22With the strange pixel P in the 3rd row pixel 31Compensation distribution CL, in order to continue and to supply burning voltage VS3 and VS4 accordingly to pixel P 22With P 31Compensation distribution CL.
Clearer, the first sub-voltage supply device 2603 has a plurality of voltage feeding unit 2603_1 and 2603_2.When the type of drive that adopts some counter-rotating (dot inversion) drives display panel 3701; Then the 1st voltage feeding unit 2603_1 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 1st sweep signal SS1 (generally being produced by gate drivers), the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS1 (that is VS-) of negative polarity gives the strange pixel P in the 2nd row pixel and for example provide 21Compensation distribution CL.
In addition; The 2nd voltage feeding unit 2603_2 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 2nd sweep signal SS2, the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS2 (that is VS-) of negative polarity gives the dual pixel P in the 3rd row pixel and for example provide 32Compensation distribution CL.Wherein, The work period of the first clock signal CK1 is essentially during the picture of semitransparent and half-reflective liquid crystal display 4500 of single bug hole spacing, and second be essentially (identical during the activation of sweep signal SS1 and SS2 usually) during the activation of sweep signal SS1 or SS2 with the work period of the 3rd clock signal CK2 and XCK2.
In addition, the second sub-voltage supply device 2605 has a plurality of voltage feeding unit 2605_1 and 2605_2.When the type of drive that adopts some counter-rotating (dot inversion) drives display panel 3701; Then the 1st voltage feeding unit 2605_1 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 1st sweep signal SS1, the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS3 (that is VS+) of positive polarity gives the dual pixel P in the 2nd row pixel and for example provide 22Compensation distribution CL.In addition; The 2nd voltage feeding unit 2605_2 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 2nd sweep signal SS2, the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS4 (that is VS+) of positive polarity gives the strange pixel P in the 3rd row pixel and for example provide 31Compensation distribution CL.
In the 23 example embodiment, voltage feeding unit 2603_1,2603_2,2605_1 are identical with the 11 example embodiment with the circuit structure of 2605_2, so at this and no longer give unnecessary details it.
Figure 46 A illustrates the time sequential routine figure of the voltage feeding unit 2603_1 and the 2603_2 that are the 23 example embodiment.Please merge with reference to Figure 27 A, Figure 27 B, Figure 45 and Figure 46 A, from Figure 28 A, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N3 in the voltage feeding unit 2603_1 can be switched on.Because this moment, the first and the 3rd clock signal CK1 and XCK2 were in the state of activation, and the second clock signal CK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2603_1 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2N 2Can be ended.Thus, voltage feeding unit 2603_1 promptly can provide the burning voltage VS1 (that is VS-) of negative polarity to give the strange pixel P in the 2nd row pixel by FP during a picture 21P 21Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2603_2 3Can be switched on.Because this moment, first and second clock signal CK1 and CK2 were in the state of activation, and the 3rd clock signal XCK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2603_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2603_2 promptly can provide the burning voltage VS2 (that is VS-) of negative polarity to give the dual pixel P in the 3rd row pixel by FP during same picture 32Compensation distribution CL.
In addition, Figure 46 B illustrates the time sequential routine figure of the voltage feeding unit 2605_1 and the 2605_2 that are the 23 example embodiment.Please merge with reference to Figure 27 C, Figure 27 D, Figure 45 and Figure 46 B, from Figure 46 B, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2605_1 3Can be switched on.Because this moment, the first and the 3rd clock signal CK1 and XCK2 were in the state of activation, and the second clock signal CK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2605_1 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2605_1 promptly can provide the burning voltage VS3 (that is VS+) of positive polarity to give the dual pixel P in the 2nd row pixel by FP during same picture 22Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2605_2 3Can be switched on.Because this moment, first and second clock signal CK1 and CK2 were in the state of activation, and the 3rd clock signal XCK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2605_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2605_2 promptly can provide the burning voltage VS4 (that is VS+) of positive polarity to give the strange pixel P in the 3rd row pixel by FP during same picture 31Compensation distribution CL.
Know based on above-mentioned, because the voltage supply device that first and second sub-voltage supply device 2603 and 2605 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 21, P 22, P 31With P 32Compensation distribution CL, so as to changing each pixel P 21, P 22, P 31With P 32The voltage folder of echo area RA poor, and then adjust each pixel P 21, P 22, P 31With P 32The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, the semitransparent and half-reflective liquid crystal display 4500 of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because the voltage supply device that first and second sub-voltage supply device 2603 and 2605 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 21, P 22, P 31With P 32Compensation distribution CL.Therefore, each pixel P 21, P 22, P 31With P 32The current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 4500 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[the 24 example embodiment]
Figure 47 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 4700 of the single bug hole spacing of the present invention's the 24 example embodiment.Please with reference to Figure 47; The semitransparent and half-reflective liquid crystal display 4700 of single bug hole spacing comprises display panel 3901 and the voltage supply device that is made up of first and second sub-voltage supply device 2603 and 2605, and wherein display panel 3901 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 4700 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 24 example embodiment only shows the parts relevant with the present invention.
In the 24 example embodiment, the structure of display panel 3901 is identical with the 20 example embodiment, so also no longer give unnecessary details it at this.In addition, the first sub-voltage supply device 2603 couples the strange pixel P in the 1st row pixel 11With the dual pixel P in the 2nd row pixel 22Compensation distribution CL, in order to continue and to supply burning voltage VS1 and VS2 accordingly to pixel P 11With P 22Compensation distribution CL.In addition, the second sub-voltage supply device 2605 couples the dual pixel P in the 1st row pixel 12With all take on strange pixel P in the 2nd row pixel 21Compensation distribution CL, in order to continue and to supply burning voltage VS3 and VS4 accordingly to pixel P 12With P 21Compensation distribution CL.
Clearer, the first sub-voltage supply device 2603 has a plurality of voltage feeding unit 2603_1 and 2603_2.When the type of drive that adopts some counter-rotating (dot inversion) drives display panel 3901; Then the 1st voltage feeding unit 2603_1 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 1st sweep signal SS1 (generally being produced by gate drivers), the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS1 (that is VS-) of negative polarity gives the strange pixel P in the 1st row pixel and for example provide 11Compensation distribution CL.
In addition; The 2nd voltage feeding unit 2603_2 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 2nd sweep signal SS2, the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS2 (that is VS-) of negative polarity gives the strange pixel P in the 2nd row pixel and for example provide 21Compensation distribution CL.Wherein, The work period of the first clock signal CK1 is essentially during the picture of semitransparent and half-reflective liquid crystal display 4700 of single bug hole spacing, and second be essentially (identical during the activation of sweep signal SS1 and SS2 usually) during the activation of sweep signal SS1 or SS2 with the work period of the 3rd clock signal CK2 and XCK2.
In addition, the second sub-voltage supply device 2605 has a plurality of voltage feeding unit 2605_1 and 2605_2.When the type of drive that adopts some counter-rotating (dot inversion) drives display panel 3901; Then the 1st voltage feeding unit 2605_1 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 1st sweep signal SS1, the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS3 (that is VS+) of positive polarity gives the dual pixel P in the 1st row pixel and for example provide 12Compensation distribution CL.In addition; The 2nd voltage feeding unit 2605_2 can be according to the second and the 3rd clock signal CK2 and XCK2 of the 2nd sweep signal SS2, the first clock signal CK1 and phase differential 180 degree, and the burning voltage VS4 (that is VS+) of positive polarity gives the strange pixel P in the 2nd row pixel and for example provide 21Compensation distribution CL.
In the 24 example embodiment, voltage feeding unit 2603_1,2603_2,2605_1 are identical with the 11 example embodiment with the circuit structure of 2605_2, so at this and no longer give unnecessary details it.
Figure 48 A illustrates the time sequential routine figure of the voltage feeding unit 2603_1 and the 2603_2 that are the 24 example embodiment.Please merge with reference to Figure 27 A, Figure 27 B, Figure 47 and Figure 48 A, from Figure 48 A, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2603_1 3Can be switched on.Because this moment, first and second clock signal CK1 and CK2 were in the state of activation, and the 3rd clock signal XCK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2603_1 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2603_1 promptly can provide the burning voltage VS1 (that is VS-) of negative polarity to give the strange pixel P in the 1st row pixel by FP during a picture 11Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2603_2 3Can be switched on.Because this moment, the first and the 3rd clock signal CK1 and XCK2 were in the state of activation, and the second clock signal CK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2603_2 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2603_2 promptly can provide the burning voltage VS2 (that is VS-) of negative polarity to give the dual pixel P in the 2nd row pixel by FP during same picture 22Compensation distribution CL.
In addition, Figure 48 B illustrates the time sequential routine figure of the voltage feeding unit 2605_1 and the 2605_2 that are the 24 example embodiment.Please merge with reference to Figure 27 C, Figure 27 D, Figure 47 and Figure 48 B, from Figure 48 B, can know and find out, when sweep signal SS1 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2605_1 3Can be switched on.Because this moment, first and second clock signal CK1 and CK2 were in the state of activation, and the 3rd clock signal XCK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2605_1 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2N 2Can be ended.Thus, voltage feeding unit 2605_1 promptly can provide the burning voltage VS3 (that is VS+) of positive polarity to give the dual pixel P in the 1st row pixel by FP during same picture 12Compensation distribution CL.
Similarly, when sweep signal SS2 activation, the 3rd N transistor npn npn N in the voltage feeding unit 2605_2 3Can be switched on.Because this moment, the first and the 3rd clock signal CK1 and XCK2 were in the state of activation, and the second clock signal CK2 is in the state of forbidden energy.Therefore, the 4th and the 5th N transistor npn npn N in the voltage feeding unit 2605_2 4N 4With N 5Can be switched on, and the 2nd N transistor npn npn N 2Can be ended.Thus, voltage feeding unit 2605_2 promptly can provide the burning voltage VS4 (that is VS+) of positive polarity to give the strange pixel P in the 2nd row pixel by FP during same picture 21Compensation distribution CL.
Know based on above-mentioned, because the voltage supply device that first and second sub-voltage supply device 2603 and 2605 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 11, P 12, P 21With P 22Compensation distribution CL, so as to changing each pixel P 11, P 12, P 21With P 22The voltage folder of echo area RA poor, and then adjust each pixel P 11, P 12, P 21With P 22The reflection gamma curve of echo area RA, and make it with penetrating region TA penetrate the gamma curve coupling.Thus, can make single bug hole spacing semitransparent and half-reflective liquid crystal display 4700 penetrate display effect with the reflection display effect can reach optimization simultaneously.
In addition, because the voltage supply device that first and second sub-voltage supply device 2603 and 2605 is constituted can continue and provide accordingly/apply a burning voltage VS1～VS4 to being positioned at each pixel P 11, P 12, P 21With P 22Compensation distribution CL.Therefore, each pixel P 11, P 12, P 21With P 22The current potential of compensation distribution CL just can not receive the influence of the signal of being imported on data line D1 and the D2 because of coupling effect; Thereby make the whole cross-talk phenomenons of semitransparent and half-reflective liquid crystal display 4700 of single bug hole spacing can be suppressed to below the formulation specification of shipment product (for example below 2%, but be not restricted to this).
[the 25 example embodiment]
Figure 49 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 4900 of the single bug hole spacing of the present invention's the 25 example embodiment.Please with reference to Figure 49; The semitransparent and half-reflective liquid crystal display 4900 of single bug hole spacing comprises display panel 4901 and the voltage supply device that is made up of first and second sub-voltage supply device 1603 and 1605, and wherein display panel 4901 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 4900 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 25 example embodiment only shows the parts relevant with the present invention.
Display panel 4901 comprises multi-strip scanning line G2 and G3 (only showing 2 sweep traces conveniently to do explanation), many cardinal principles and sweep trace G2 and vertically disposed data line D1 of G3 and D2 (only showing 2 data lines conveniently to do explanation), and a plurality of pixel P that are positioned at the viewing area AA of display panel 4901 21, P 22, P 31With P 32(only showing 4 pixels) conveniently to do explanation.
Pixel P 21, P 22, P 31With P 32Can electrically connect with corresponding data line and sweep trace respectively, and arrange with matrix-style.For instance, pixel P 21Electrically connect with data line D1 and sweep trace G2 respectively; Pixel P 22Electrically connect with data line D2 and sweep trace G2 respectively; Pixel P 31Electrically connect with data line D1 and sweep trace G3 respectively; And pixel P 32Electrically connect with data line D2 and sweep trace G3 respectively.In addition, pixel P 21Be expressed as the 1st pixel in the 2nd row pixel in the display panel 4901; Pixel P 22Be expressed as the 2nd pixel in the 2nd row pixel in the display panel 4901; Pixel P 31Be expressed as the 1st pixel in the 3rd row pixel in the display panel 4901; And pixel P 32Be expressed as the 2nd pixel in the 3rd row pixel in the display panel 4901.
Each pixel P 21, P 22, P 31With P 32Comprise shared distribution CE 2, auxiliary shared distribution CE 3With compensation distribution CL.Shared distribution CE 2, auxiliary shared distribution CE 3Be positioned at each pixel P for example 21, P 22, P 31With P 32Penetrating region TA in, in order to the burning voltage VS+ and the VS-of reception positive polarity out of the ordinary and negative polarity.Compensation distribution CL is positioned at each pixel P for example 21, P 22, P 31With P 32Echo area RA in, in order to receive burning voltage VS1～VS4 accordingly.In addition, each pixel P 21, P 22, P 31With P 32More comprise pixel transistor T, the first liquid crystal capacitance C LC1, the first storage capacitors C ST1, the second storage capacitors C ST2, first capacitor C 1, the second liquid crystal capacitance C LC2, and second capacitor C 2Because all pixel P 21, P 22, P 31With P 32Circuit structure with to couple relation all similar, so below only describe with single pixel.
With pixel P 21Be example, the grid of pixel transistor T couples sweep trace G2, and the source electrode of pixel transistor T then is coupled to data line D1.Generally speaking, the pixel electrode (pixel electrode) that electrically connects with the drain electrode of pixel transistor T with in order to receive the common electrode CE of common voltage Vcom 1Between can form the first liquid crystal capacitance C LC1, with shared distribution CE 2Between can form storage capacitors C ST1, and with auxiliary shared distribution CE 3Between can form storage capacitors C ST2
The first liquid crystal capacitance C LC1First end couple the drain electrode of pixel transistor T, and the first liquid crystal capacitance C LC1Second end then be coupled to common electrode CE.The first storage capacitors C ST1First end couple the drain electrode of pixel transistor T, and the first storage capacitors C ST1Second end then be coupled to shared distribution CE 2The second storage capacitors C ST2First end couple the drain electrode of pixel transistor T, and the second storage capacitors C ST2Second end then be coupled to auxiliary shared distribution CE 3Wherein, pixel transistor T, the first liquid crystal capacitance C LC1, the first storage capacitors C ST1And the second storage capacitors C ST2Be positioned at pixel P 21Penetrating region TA in.
In addition, first capacitor C 1First end couple the drain electrode of pixel transistor T.The second liquid crystal capacitance C LC2First end couple first capacitor C 1Second end, and the second liquid crystal capacitance C LC2Second end then be coupled to common electrode CE 1Second capacitor C 2First end couple first capacitor C 1Second end, and second capacitor C 2Second end then be coupled to compensation distribution CL.Wherein, first capacitor C 1, the second liquid crystal capacitance C LC2And second capacitor C 2Be positioned at pixel P 21Echo area RA in.
In the 25 example embodiment, voltage feeding unit 1603_1,1603_2,1605_1 are identical with the 7th example embodiment with the circuit structure of 1605_2, so at this and no longer give unnecessary details it.
Know that based on above-mentioned the different place of the 25 example embodiment and the 19 example embodiment only is each pixel P of the display panel 4901 of the 25 example embodiment 21, P 22, P 31With P 32In penetrating region TA in have two storage capacitors C ST1With C ST2, and its second end meeting burning voltage VS+ and VS-that receives positive polarity and negative polarity out of the ordinary, and all the other are all identical with the 19 example embodiment.Therefore, can learn after the content that is please disclosed with reference to the 7th and the 19 example embodiment about the detailed operation principle of the 25 example embodiment, so at this and no longer give unnecessary details it.
[the 26 example embodiment]
Figure 50 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 5000 of the single bug hole spacing of the present invention's the 26 example embodiment.Please with reference to Figure 50, the semitransparent and half-reflective liquid crystal display 5000 of single bug hole spacing comprises display panel 5001 and the voltage supply device that is made up of first and second sub-voltage supply device 1603 and 1605.Certainly; The semitransparent and half-reflective liquid crystal display 5000 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 26 example embodiment only shows the parts relevant with the present invention.
Display panel 5001 comprises multi-strip scanning line G1 and G2 (only showing 2 sweep traces conveniently to do explanation), many cardinal principles and sweep trace G1 and vertically disposed data line D1 of G2 and D2 (only showing 2 data lines conveniently to do explanation), and a plurality of pixel P that are positioned at the viewing area AA of display panel 5001 11, P 12, P 21With P 22(only showing 4 pixels) conveniently to do explanation.
Pixel P 11, P 12, P 21With P 22Can electrically connect with corresponding data line and sweep trace respectively, and arrange with matrix-style.For instance, pixel P 11Electrically connect with data line D1 and sweep trace G1 respectively; Pixel P 12Electrically connect with data line D2 and sweep trace G1 respectively; Pixel P 21Electrically connect with data line D1 and sweep trace G2 respectively; And pixel P 22Electrically connect with data line D2 and sweep trace G2 respectively.In addition, pixel P 11Be expressed as the 1st pixel in the 1st row pixel in the display panel 5001; Pixel P 12Be expressed as the 2nd pixel in the 1st row pixel in the display panel 5001; Pixel P 21Be expressed as the 1st pixel in the 2nd row pixel in the display panel 5001; And pixel P 22Be expressed as the 2nd pixel in the 2nd row pixel in the display panel 5001.
Each pixel P 11, P 12, P 21With P 22Comprise shared distribution CE 2, auxiliary shared distribution CE 3With compensation distribution CL.Shared distribution CE 2, auxiliary shared distribution CE 3Be positioned at each pixel P for example 11, P 12, P 21With P 22Penetrating region TA in, in order to the burning voltage VS+ and the VS-of reception positive polarity out of the ordinary and negative polarity.Compensation distribution CL is positioned at each pixel P 11, P 12, P 21With P 22Echo area RA in, in order to receive burning voltage VS1～VS4 accordingly.In addition, each pixel P 11, P 12, P 21With P 22More comprise pixel transistor T, the first liquid crystal capacitance C LC1, the first storage capacitors C ST1, the second storage capacitors C ST2, first capacitor C 1, the second liquid crystal capacitance C LC2, and second capacitor C 2Because all pixel P 11, P 12, P 21With P 22Circuit structure with to couple relation all similar, so below only describe with single pixel.
With pixel P 11Be example, the grid of pixel transistor T couples sweep trace G1, and the source electrode of pixel transistor T then is coupled to data line D1.Generally speaking, the pixel electrode (pixel electrode) that electrically connects with the drain electrode of pixel transistor T with in order to receive the common electrode CE of common voltage Vcom 1Between can form the first liquid crystal capacitance C LC1, with the first shared distribution CE 2Between can form storage capacitors C ST1, and with auxiliary shared distribution CE 3Between can form storage capacitors C ST2
The first liquid crystal capacitance C LC1First end couple the drain electrode of pixel transistor T, and the first liquid crystal capacitance C LC1Second end then be coupled to common electrode CE.The first storage capacitors C ST1First end couple the drain electrode of pixel transistor T, and the first storage capacitors C ST1Second end then be coupled to shared distribution CE 2The second storage capacitors C ST2First end couple the drain electrode of pixel transistor T, and the second storage capacitors C ST2Second end then be coupled to auxiliary shared distribution CE 3Wherein, pixel transistor T, the first liquid crystal capacitance C LC1, the first storage capacitors C ST1And the second storage capacitors C ST2Be positioned at pixel P 11Penetrating region TA in.
In addition, first capacitor C 1First end couple the drain electrode of pixel transistor T.The second liquid crystal capacitance C LC2First end couple first capacitor C 1Second end, and the second liquid crystal capacitance C LC2Second end then be coupled to common electrode CE 1Second capacitor C 2First end couple first capacitor C 1Second end, and second capacitor C 2Second end then be coupled to compensation distribution CL.Wherein, first capacitor C 1, the second liquid crystal capacitance C LC2And second capacitor C 2Be positioned at pixel P 11Echo area RA in.
In the 26 example embodiment, voltage feeding unit 1603_1,1603_2,1605_1 are identical with the 7th example embodiment with the circuit structure of 1605_2, so at this and no longer give unnecessary details it.
Know that based on above-mentioned the different place of the 26 example embodiment and the 20 example embodiment only is each pixel P of the display panel 5001 of the 26 example embodiment 11, P 12, P 21With P 22In penetrating region TA in have two storage capacitors C ST1With C ST2, and its second end meeting burning voltage VS+ and VS-that receives positive polarity and negative polarity out of the ordinary, and all the other are all identical with the 20 example embodiment.Therefore, can learn after please merging the content that is disclosed with reference to the 7th and 20 example embodiment about the detailed operation principle of the 26 example embodiment, so at this and no longer give unnecessary details it.
[the 27 example embodiment]
Figure 51 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 5100 of the single bug hole spacing of the present invention's the 27 example embodiment.Please with reference to Figure 51; The semitransparent and half-reflective liquid crystal display 5100 of single bug hole spacing comprises display panel 4901 and the voltage supply device that is made up of first and second sub-voltage supply device 2103 and 2105, and wherein display panel 4901 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 5100 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 27 example embodiment only shows the parts relevant with the present invention.
In the 27 example embodiment, the structure of display panel 4901 is identical with the 25 example embodiment, so also no longer give unnecessary details it at this.In addition, the circuit structure of voltage feeding unit 2103_1,2103_2,2105_1 and 2105_2 is identical with the 9th example embodiment, so also no longer give unnecessary details it at this.
Know that based on above-mentioned the different place of the 27 example embodiment and the 21 example embodiment only is each pixel P of the display panel 4901 of the 27 example embodiment 21, P 22, P 31With P 32In penetrating region TA in have two storage capacitors C ST1With C ST2, and its second end meeting burning voltage VS+ and VS-that receives positive polarity and negative polarity out of the ordinary, and all the other are all identical with the 21 example embodiment.Therefore, can learn after please merging the content that is disclosed with reference to the 9th and the 21 example embodiment about the detailed operation principle of the 27 example embodiment, so also no longer give unnecessary details it at this.
[the 28 example embodiment]
Figure 52 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 5200 of the single bug hole spacing of the present invention's the 28 example embodiment.Please with reference to Figure 52; The semitransparent and half-reflective liquid crystal display 5200 of single bug hole spacing comprises display panel 5001 and the voltage supply device that is made up of first and second sub-voltage supply device 2103 and 2105, and wherein display panel 5001 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 5200 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 28 example embodiment only shows the parts relevant with the present invention.
In the 28 example embodiment, the structure of display panel 5001 is identical with the 26 example embodiment, so also no longer give unnecessary details it at this.In addition, the circuit structure of voltage feeding unit 2103_1,2103_2,2105_1 and 2105_2 is identical with the 9th example embodiment, so also no longer give unnecessary details it at this.
Know that based on above-mentioned the different place of the 28 example embodiment and the 22 example embodiment only is each pixel P of the display panel 5001 of the 28 example embodiment 11, P 12, P 21With P 22In penetrating region TA in have two storage capacitors C ST1With C ST2, and its second end meeting burning voltage VS+ and VS-that receives positive polarity and negative polarity out of the ordinary, and all the other are all identical with the 22 example embodiment.Therefore, can learn after please merging the content that is disclosed with reference to the 9th, the tenth and the 22 example embodiment about the detailed operation principle of the 28 example embodiment, so also no longer give unnecessary details it at this.
[the 29 example embodiment]
Figure 53 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 5300 of the single bug hole spacing of the present invention's the 29 example embodiment.Please with reference to Figure 53; The semitransparent and half-reflective liquid crystal display 5300 of single bug hole spacing comprises display panel 4901 and the voltage supply device that is made up of first and second sub-voltage supply device 2603 and 2605, and wherein display panel 4901 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 5300 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 29 example embodiment only shows the parts relevant with the present invention.
In the 29 example embodiment, the structure of display panel 4901 is identical with the 25 example embodiment, so also no longer give unnecessary details it at this.In addition, voltage feeding unit 2603_1,2603_2,2605_1 are identical with the 11 example embodiment with the circuit structure of 2605_2, so also no longer give unnecessary details it at this.
Know that based on above-mentioned the different place of the 29 example embodiment and the 23 example embodiment only is each pixel P of the display panel 4901 of the 29 example embodiment 21, P 22, P 31With P 32In penetrating region TA in have two storage capacitors C ST1With C ST2, and its second end meeting burning voltage VS+ and VS-that receives positive polarity and negative polarity out of the ordinary, and all the other are all identical with the 23 example embodiment.Therefore, can learn after please merging the content that is disclosed with reference to the 11 and the 23 example embodiment about the detailed operation principle of the 29 example embodiment, so also no longer give unnecessary details it at this.
[the 30 example embodiment]
Figure 54 illustrates the partial schematic diagram into the semitransparent and half-reflective liquid crystal display 5400 of the single bug hole spacing of the present invention's the 30 example embodiment.Please with reference to Figure 54; The semitransparent and half-reflective liquid crystal display 5400 of single bug hole spacing comprises display panel 5001 and the voltage supply device that is made up of first and second sub-voltage supply device 2603 and 2605, and wherein display panel 5001 is single bug hole spacing display panels.Certainly; The semitransparent and half-reflective liquid crystal display 5400 of single bug hole spacing more comprises miscellaneous part; For example gate drivers, source electrode driver, time schedule controller and backlight module etc. describe but the 30 example embodiment only shows the parts relevant with the present invention.
In the 30 example embodiment, the structure of display panel 5001 is identical with the 26 example embodiment, so also no longer give unnecessary details it at this.In addition, voltage feeding unit 2603_1,2603_2,2605_1 are identical with the 11 example embodiment with the circuit structure of 2605_2, so also no longer give unnecessary details it at this.
Know that based on above-mentioned the different place of the 30 example embodiment and the 24 example embodiment only is each pixel P of the display panel 5001 of the 30 example embodiment 11, P 12, P 21With P 22In penetrating region TA in have two storage capacitors C ST1With C ST2, and its second end meeting burning voltage VS+ and VS-that receives positive polarity and negative polarity out of the ordinary, and all the other are all identical with the 24 example embodiment.Therefore, can learn after please merging the content that is disclosed with reference to the 11, the 12 and the 24 example embodiment about the detailed operation principle of the 30 example embodiment, so also no longer give unnecessary details it at this.
In view of the above; Above-mentioned each example embodiment is that example is done explanation with the picture element matrix of 2*2 all; But after the content via above-mentioned each example embodiment institute teaching; Those skilled in the art should analogize/deduce out the above embodiment of picture element matrix of 2*2 easily, so also no longer give unnecessary details it at this.
In addition; Though the voltage feeding unit of above-mentioned each example embodiment is that example is done explanation with the N transistor npn npn all, do not limit to, so long as under the condition that the processing procedure factor allows; P transistor npn npn also capable of using is implemented; Optionally and assistant is drawn acknowledge(ment) signal to adjust its corresponding grid control signal and source, reaching function and the effect that the voltage feeding unit is desired to provide, and the example embodiment of these distortion also belongs to one of category of institute of the present invention desire protection.
Moreover; Though the voltage feeding unit of above-mentioned each example embodiment is that example is done explanation with the semitransparent and half-reflective liquid crystal display that is applied in single bug hole spacing; But it also can be applicable to the LCD of other types, and the example embodiment of these distortion also belongs to one of category of institute of the present invention desire protection.
In sum; The present invention sees through voltage supply device, and to continue to supply/apply the voltage folder of the echo area that mode that a burning voltage (or being referred to as fixed voltage) gives the compensation distribution that is positioned at each pixel changes each pixel poor; Adjust the reflection gamma curve of the echo area of each pixel whereby, and make it to mate with the gamma curve that penetrates of penetrating region.Thus, the semitransparent and half-reflective liquid crystal display of single bug hole spacing penetrate display effect with the reflection display effect promptly can reach optimization simultaneously.
In addition, because can continuing and supply accordingly/apply a burning voltage, voltage supply device gives the compensation distribution that is positioned at each pixel.Therefore; The current potential of the compensation distribution of each pixel is with regard to the influence of the signal that can not receive on the data line being imported because of coupling effect, thereby makes the whole cross-talk phenomenon of semitransparent and half-reflective liquid crystal display of single bug hole spacing can be suppressed to below the formulation specification of shipment product.Though in various embodiments of the present invention; With the semitransparent and half-reflective liquid crystal display is example; Yet do not limit to, main element configuration of the present invention can be applicable to penetrating LCD or reflective liquid-crystal display, in order to improve color offset phenomenon (color washout).(integrate and form, and more can have the advantage of preferable space availability ratio by a plurality of elements in the gate on array, the viewing area AA of manufacturing method thereof GOA) and display panel 101 in array for other gate drivers capable of using of voltage supply device.
Certainly; The present invention also can have other various embodiments; Under the situation that does not deviate from spirit of the present invention and essence thereof; Those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.

Claims (24)

1. a LCD is characterized in that, comprising:
One display panel comprises:
The multi-strip scanning line;
Many data lines are provided with said sweep trace is vertical substantially;
A plurality of pixels electrically connect with corresponding data line and sweep trace respectively, and said pixel is arranged with matrix-style, and each pixel comprises:
One shared distribution is used voltage altogether in order to receive; And
One compensation distribution is in order to receive a burning voltage; And
One voltage supply device couples this compensation distribution of each pixel, in order to continue and to supply this compensation distribution that this burning voltage is given each pixel accordingly;
This voltage supply device has a plurality of voltage feeding units; And i voltage feeding unit is according to the sweep signal of a correspondence and one first and one second clock signal of phase differential 180 degree; And this burning voltage that positive polarity or negative polarity be provided is to this compensation distribution of each pixel in i row or (i+1) row pixel
Wherein, this is first with during the work period of this second clock signal is essentially the activation of this corresponding sweep signal;
Wherein, each pixel in the i row pixel more comprises:
One pixel transistor, its grid couples i bar sweep trace, and its source electrode then is coupled to i bar data line, and wherein i is a positive integer;
One first liquid crystal capacitance, its first end couples the drain electrode of this pixel transistor, and its second end then is coupled to uses electrode altogether; And
One storage capacitors, its first end couples the drain electrode of this pixel transistor, and its second end then is coupled to this shared distribution,
Wherein, this pixel transistor, this first liquid crystal capacitance and this storage capacitors are positioned at a penetrating region;
One first electric capacity, its first end couples the drain electrode of this pixel transistor;
One second liquid crystal capacitance, its first end couples second end of this first electric capacity, and its second end then is coupled to this common electrode; And
One second electric capacity, its first end couples second end of this first electric capacity, and its second end then is coupled to this compensation distribution,
Wherein, this first electric capacity, this second liquid crystal capacitance and this second electric capacity are positioned at an echo area.
2. LCD according to claim 1 is characterized in that, i voltage feeding unit comprises:
One the one N transistor npn npn, its grid couple i bar sweep trace receiving this corresponding sweep signal, and its source electrode is in order to receive this first clock signal;
One the 3rd electric capacity, its first end couples the drain electrode of a N transistor npn npn, and its second end then is coupled to this shared distribution;
One the 2nd N transistor npn npn, its grid couples the drain electrode of a N transistor npn npn, and its source electrode is in order to receive this burning voltage of positive polarity, and its drain electrode then is coupled to this compensation distribution of each pixel in i row or (i+1) row pixel;
One the 3rd N transistor npn npn, its grid couple i bar sweep trace to receive this corresponding sweep signal, and its source electrode is then in order to receive this second clock signal;
One the 4th electric capacity, its first end couples the drain electrode of the 3rd N transistor npn npn, and its second end then is coupled to this shared distribution; And
One the 4th N transistor npn npn, its grid couples the drain electrode of the 3rd N transistor npn npn, and its source electrode is in order to receive this burning voltage of negative polarity, and its drain electrode then is coupled to this compensation distribution of each pixel in i row or (i+1) row pixel.
3. LCD according to claim 1 is characterized in that, this display panel is the half-penetration half-reflection liquid crystal display panel of a single bug hole spacing.
4. a LCD is characterized in that, comprising:
One display panel comprises:
The multi-strip scanning line;
Many data lines are provided with said sweep trace is vertical substantially;
A plurality of pixels electrically connect with corresponding data line and sweep trace respectively, and said pixel is arranged with matrix-style, and each pixel comprises:
One shared distribution is used voltage altogether in order to receive; And
One compensation distribution is in order to receive a burning voltage; And
One voltage supply device couples this compensation distribution of each pixel, in order to continue and to supply this compensation distribution that this burning voltage is given each pixel accordingly;
Each pixel in the i row pixel more comprises:
One pixel transistor, its grid couples i bar sweep trace, and its source electrode then is coupled to i bar data line, and wherein i is a positive integer;
One first liquid crystal capacitance, its first end couples the drain electrode of this pixel transistor, and its second end then is coupled to uses electrode altogether; And
One storage capacitors, its first end couples the drain electrode of this pixel transistor, and its second end then is coupled to this shared distribution,
Wherein, this pixel transistor, this first liquid crystal capacitance and this storage capacitors are positioned at a penetrating region;
One first electric capacity, its first end couples the drain electrode of this pixel transistor;
One second liquid crystal capacitance, its first end couples second end of this first electric capacity, and its second end then is coupled to this common electrode; And
One second electric capacity, its first end couples second end of this first electric capacity, and its second end then is coupled to this compensation distribution,
Wherein, this first electric capacity, this second liquid crystal capacitance and this second electric capacity are positioned at an echo area;
This voltage supply device has a plurality of voltage feeding units; And sweep signal, one first clock signal and one second clock signal of i voltage feeding unit foundation one correspondence, and this burning voltage of positive polarity or negative polarity this compensation distribution to each pixel in i row or (i+1) row pixel is provided.
5. LCD according to claim 4 is characterized in that, the work period of this first clock signal is essentially during the activation of this corresponding sweep signal, and this second clock signal then continues to maintain the state of activation.
6. LCD according to claim 4 is characterized in that, i voltage feeding unit comprises:
One the one N transistor npn npn, its grid is coupled in its source electrode, to receive this second clock signal;
One the 2nd N transistor npn npn, its grid couples the drain electrode of a N transistor npn npn, and its source electrode is in order to receive this burning voltage of positive polarity, and its drain electrode then is coupled to this compensation distribution of each pixel in i row or (i+1) row pixel;
One the 3rd N transistor npn npn, its grid couple i bar sweep trace to receive this corresponding sweep signal, and its source electrode is then in order to receive this first clock signal;
One the 3rd electric capacity, its first end couples the drain electrode of the 3rd N transistor npn npn, and its second end then is coupled to this shared distribution;
One the 4th N transistor npn npn, its grid couples the drain electrode of the 3rd N transistor npn npn, and its source electrode is in order to receive this burning voltage of negative polarity, and its drain electrode then is coupled to the grid of the 2nd N transistor npn npn; And
One the 5th N transistor npn npn; Its grid couples the drain electrode of the 3rd N transistor npn npn; Its source electrode is in order to receive this burning voltage of negative polarity; Its drain electrode then is coupled to this compensation distribution of each pixel in i row or (i+1) row pixel; Wherein i voltage feeding unit be more according to this second and 1 the 3rd clock signals of this corresponding sweep signal, this first clock signal and phase differential 180 degree, and provide this burning voltage of positive polarity or negative polarity to be listed as to i or (i+1) row pixel in this compensation distribution of each pixel.
7. a LCD is characterized in that, comprising:
One display panel comprises:
The multi-strip scanning line;
Many data lines are provided with said sweep trace is vertical substantially;
A plurality of pixels electrically connect with corresponding data line and sweep trace respectively, and said pixel is arranged with matrix-style, and each pixel comprises:
One shared distribution is used voltage altogether in order to receive; And
One compensation distribution is in order to receive a burning voltage; And
One voltage supply device couples this compensation distribution of each pixel, in order to continue and to supply this compensation distribution that this burning voltage is given each pixel accordingly;
Each pixel in the i row pixel more comprises:
One pixel transistor, its grid couples i bar sweep trace, and its source electrode then is coupled to i bar data line, and wherein i is a positive integer;
One first liquid crystal capacitance, its first end couples the drain electrode of this pixel transistor, and its second end then is coupled to uses electrode altogether; And
One storage capacitors, its first end couples the drain electrode of this pixel transistor, and its second end then is coupled to this shared distribution,
Wherein, this pixel transistor, this first liquid crystal capacitance and this storage capacitors are positioned at a penetrating region;
One first electric capacity, its first end couples the drain electrode of this pixel transistor;
One second liquid crystal capacitance, its first end couples second end of this first electric capacity, and its second end then is coupled to this common electrode; And
One second electric capacity, its first end couples second end of this first electric capacity, and its second end then is coupled to this compensation distribution,
Wherein, this first electric capacity, this second liquid crystal capacitance and this second electric capacity are positioned at an echo area;
This voltage supply device comprises:
One first sub-voltage supply device; Have a plurality of first voltage feeding units; Wherein i the first voltage feeding unit is according to a corresponding sweep signal and one first and one second clock signal of phase differential 180 degree, and provide this burning voltage of positive polarity to be listed as to i or (i+1) row pixel in this compensation distribution of odd pixel; And
One second sub-voltage supply device; Have a plurality of second voltage feeding units; Wherein i the second voltage feeding unit according to this corresponding sweep signal and phase differential 180 degree this first with this second clock signal; And this burning voltage that negative polarity is provided is to this compensation distribution of all dual pixels in i row or (i+1) row pixel
Wherein, this first is essentially during the picture of this LCD with work period of this second clock signal.
8. LCD according to claim 7 is characterized in that, i the first voltage feeding unit comprises:
One the one N transistor npn npn, its grid couple i bar sweep trace receiving this corresponding sweep signal, and its source electrode is in order to receive this first clock signal;
One the 3rd electric capacity, its first end couples the drain electrode of a N transistor npn npn, and its second end then is coupled to this common electrode;
One the 2nd N transistor npn npn, its grid couples the drain electrode of a N transistor npn npn, its source electrode is in order to receiving this burning voltage of positive polarity, its drain electrode then be coupled in i row or (i+1) row pixel this compensation distribution of odd pixel;
One the 3rd N transistor npn npn, its grid couple i bar sweep trace to receive this corresponding sweep signal, and its source electrode is then in order to receive this second clock signal;
One the 4th electric capacity, its first end couples the drain electrode of the 3rd N transistor npn npn, and its second end then is coupled to this shared distribution; And
One the 4th N transistor npn npn, its grid couples the drain electrode of the 3rd N transistor npn npn, its source electrode is in order to receiving this burning voltage of negative polarity, its drain electrode then be coupled in i row or (i+1) row pixel this compensation distribution of odd pixel.
9. LCD according to claim 7 is characterized in that, i the second voltage feeding unit comprises:
One the one N transistor npn npn, its grid couple i bar sweep trace to receive this corresponding sweep signal, and its source electrode is then in order to receive this first clock signal;
One the 3rd electric capacity, its first end couples the drain electrode of a N transistor npn npn, and its second end then is coupled to this shared distribution;
One the 2nd N transistor npn npn, its grid couples the drain electrode of a N transistor npn npn, and its source electrode is in order to receive this burning voltage of negative polarity, and its drain electrode then is coupled to this compensation distribution of all dual pixels in i row or (i+1) row pixel;
One the 3rd N transistor npn npn, its grid couple i bar sweep trace to receive this corresponding sweep signal, and its source electrode is then in order to receive this second clock signal;
One the 4th electric capacity, its first end couples the drain electrode of the 3rd N transistor npn npn, and its second end then is coupled to this shared distribution; And
One the 4th N transistor npn npn, its grid couples the drain electrode of the 3rd N transistor npn npn, and its source electrode is in order to receive this burning voltage of positive polarity, and its drain electrode then is coupled to this compensation distribution of all dual pixels in i row or (i+1) row pixel.
10. a LCD is characterized in that, comprising:
One display panel comprises:
The multi-strip scanning line;
Many data lines are provided with said sweep trace is vertical substantially;
A plurality of pixels electrically connect with corresponding data line and sweep trace respectively, and said pixel is arranged with matrix-style, and each pixel comprises:
One shared distribution is used voltage altogether in order to receive; And
One compensation distribution is in order to receive a burning voltage; And
One voltage supply device couples this compensation distribution of each pixel, in order to continue and to supply this compensation distribution that this burning voltage is given each pixel accordingly;
Each pixel in the i row pixel more comprises:
One pixel transistor, its grid couples i bar sweep trace, and its source electrode then is coupled to i bar data line, and wherein i is a positive integer;
One first liquid crystal capacitance, its first end couples the drain electrode of this pixel transistor, and its second end then is coupled to uses electrode altogether; And
One storage capacitors, its first end couples the drain electrode of this pixel transistor, and its second end then is coupled to this shared distribution,
Wherein, this pixel transistor, this first liquid crystal capacitance and this storage capacitors are positioned at a penetrating region;
One first electric capacity, its first end couples the drain electrode of this pixel transistor;
One second liquid crystal capacitance, its first end couples second end of this first electric capacity, and its second end then is coupled to this common electrode; And
One second electric capacity, its first end couples second end of this first electric capacity, and its second end then is coupled to this compensation distribution,
Wherein, this first electric capacity, this second liquid crystal capacitance and this second electric capacity are positioned at an echo area;
This voltage supply device comprises:
One first sub-voltage supply device; Have a plurality of first voltage feeding units; Wherein i the first voltage feeding unit is according to corresponding sweep signal, one first clock signal and one second clock signal, and this burning voltage that positive polarity is provided in i row or (i+1) row pixel this compensation distribution of odd pixel; And
One second sub-voltage supply device; Have a plurality of second voltage feeding units; Wherein i the second voltage feeding unit is according to this corresponding sweep signal, this first clock signal and this second clock signal, and this burning voltage of negative polarity this compensation distribution to all dual pixels in i row or (i+1) row pixel is provided.
11. LCD according to claim 10 is characterized in that, the work period of this first clock signal is essentially during the picture of this LCD, and this second clock signal then continues to maintain the state of activation.
12. LCD according to claim 10 is characterized in that, i the first voltage feeding unit comprises:
One the one N transistor npn npn, its grid is coupled in its source electrode, to receive this second clock signal;
One the 2nd N transistor npn npn, its grid couples the drain electrode of a N transistor npn npn, its source electrode is in order to receiving this burning voltage of positive polarity, its drain electrode then be coupled in i row or (i+1) row pixel this compensation distribution of odd pixel;
One the 3rd N transistor npn npn, its grid couple i bar sweep trace to receive this corresponding sweep signal, and its source electrode is then in order to receive this first clock signal;
One the 3rd electric capacity, its first end couples the drain electrode of the 3rd N transistor npn npn, and its second end then is coupled to this shared distribution;
One the 4th N transistor npn npn, its grid couples the drain electrode of the 3rd N transistor npn npn, and its source electrode is in order to receive this burning voltage of negative polarity, and its drain electrode then is coupled to the grid of the 2nd N transistor npn npn; And
One the 5th N transistor npn npn; Its grid couples the drain electrode of the 3rd N transistor npn npn; Its source electrode is in order to receive this burning voltage of negative polarity; Its drain electrode then be coupled in i row or (i+1) row pixel this compensation distribution of odd pixel; Wherein i the first voltage feeding unit is more according to this second and 1 the 3rd clock signals of this corresponding sweep signal, this first clock signal and phase differential 180 degree, and provide this burning voltage of positive polarity to be listed as to i or (i+1) row pixel in this compensation distribution of odd pixel.
13. LCD according to claim 10 is characterized in that, i the second voltage feeding unit comprises:
One the one N transistor npn npn, its grid is coupled in its source electrode, to receive this second clock signal;
One the 2nd N transistor npn npn, its grid couples the drain electrode of a N transistor npn npn, and its source electrode is in order to receive this burning voltage of negative polarity, and its drain electrode then is coupled to this compensation distribution of all dual pixels in i row or (i+1) row pixel;
One the 3rd N transistor npn npn, its grid couple i bar sweep trace to receive this corresponding sweep signal, and its source electrode is then in order to receive this first clock signal;
One the 3rd electric capacity, its first end couples the drain electrode of the 3rd N transistor npn npn, and its second end then is coupled to this shared distribution;
One the 4th N transistor npn npn, its grid couples the drain electrode of the 3rd N transistor npn npn, and its source electrode is in order to receive this burning voltage of negative polarity, and its drain electrode then is coupled to the grid of the 2nd N transistor npn npn;
One the 5th N transistor npn npn; Its grid couples the drain electrode of the 3rd N transistor npn npn; Its source electrode is in order to receive this burning voltage of positive polarity; Its drain electrode then is coupled to this compensation distribution of all dual pixels in i row or (i+1) row pixel; Wherein i the second voltage feeding unit is more according to this second and 1 the 3rd clock signals of this corresponding sweep signal, this first clock signal and phase differential 180 degree, and provide this burning voltage of negative polarity to be listed as to i or (i+1) row pixel in this compensation distributions of all dual pixels, wherein this is second with during the work period of the 3rd clock signal is essentially the activation of this corresponding sweep signal; And
One the 6th N transistor npn npn, its grid is coupled in to receive the 3rd clock signal with its source electrode, and its drain electrode then is coupled to the drain electrode of a N transistor npn npn.
14. a LCD is characterized in that, comprising:
One display panel comprises:
The multi-strip scanning line;
Many data lines are provided with said sweep trace is vertical substantially;
A plurality of pixels electrically connect with corresponding data line and sweep trace respectively, and said pixel is arranged with matrix-style, and each pixel comprises:
One shared distribution is used voltage altogether in order to receive; And
One compensation distribution is in order to receive a burning voltage; And
One voltage supply device couples this compensation distribution of each pixel, in order to continue and to supply this compensation distribution that this burning voltage is given each pixel accordingly;
Each pixel in the i row pixel more comprises:
One pixel transistor, its grid couples i bar sweep trace, and its source electrode then is coupled to i bar data line, and wherein i is a positive integer;
One first liquid crystal capacitance, its first end couples the drain electrode of this pixel transistor, and its second end then is coupled to uses electrode altogether; And
One storage capacitors, its first end couples the drain electrode of this pixel transistor, and its second end then is coupled to this shared distribution,
Wherein, this pixel transistor, this first liquid crystal capacitance and this storage capacitors are positioned at a penetrating region;
One first electric capacity, its first end couples the drain electrode of this pixel transistor;
One second liquid crystal capacitance, its first end couples second end of this first electric capacity, and its second end then is coupled to this common electrode; And
One second electric capacity, its first end couples second end of this first electric capacity, and its second end then is coupled to this compensation distribution,
Wherein, this first electric capacity, this second liquid crystal capacitance and this second electric capacity are positioned at an echo area;
This voltage supply device comprises:
One first sub-voltage supply device has a plurality of first voltage feeding units, wherein:
I the first voltage feeding unit is according to a corresponding sweep signal and one first and one second clock signal of phase differential 180 degree, and provide this burning voltage of positive polarity to be listed as to i or (i+1) row pixel in this compensation distribution of odd pixel; And
(i+1) individual first voltage feeding unit according to another corresponding sweep signal and phase differential 180 degree this first with this second clock signal, and this burning voltage of positive polarity this compensation distribution to all dual pixels in (i+1) row or (i+2) row pixel is provided; And
One second sub-voltage supply device has a plurality of second voltage feeding units, wherein:
I the second voltage feeding unit according to this corresponding sweep signal and phase differential 180 degree this first with this second clock signal, and this burning voltage of negative polarity this compensation distribution to all dual pixels in i row or (i+1) row pixel is provided; And
(i+1) individual second voltage feeding unit according to said another corresponding sweep signal and phase differential 180 degree this first with this second clock signal; And this burning voltage that negative polarity is provided in (i+1) row or (i+2) row pixel this compensation distribution of odd pixel
Wherein, this first is essentially during the picture of this LCD with work period of this second clock signal.
15. LCD according to claim 14 is characterized in that, i the first voltage feeding unit comprises:
One the one N transistor npn npn, its grid couple i bar sweep trace to receive this corresponding sweep signal, and its source electrode is then in order to receive this first clock signal;
One the 3rd electric capacity, its first end couples the drain electrode of a N transistor npn npn, and its second end then is coupled to this shared distribution;
One the 2nd N transistor npn npn, its grid couples the drain electrode of a N transistor npn npn, its source electrode is in order to receiving this burning voltage of positive polarity, its drain electrode then be coupled in i row or (i+1) row pixel this compensation distribution of odd pixel;
One the 3rd N transistor npn npn, its grid couple i bar sweep trace to receive this corresponding sweep signal, and its source electrode is then in order to receive this second clock signal;
One the 4th electric capacity, its first end couples the drain electrode of the 3rd N transistor npn npn, and its second end then is coupled to this shared distribution; And
One the 4th N transistor npn npn, its grid couples the drain electrode of the 3rd N transistor npn npn, its source electrode is in order to receiving this burning voltage of negative polarity, its drain electrode then be coupled in i row or (i+1) row pixel this compensation distribution of odd pixel.
16. LCD according to claim 14 is characterized in that, (i+1) individual first voltage feeding unit comprises:
One the one N transistor npn npn, its grid couple (i+1) bar sweep trace to receive said another corresponding sweep signal, and its source electrode is then in order to receive this first clock signal;
One the 3rd electric capacity, its first end couples the drain electrode of a N transistor npn npn, and its second end then is coupled to this shared distribution;
One the 2nd N transistor npn npn, its grid couples the drain electrode of a N transistor npn npn, and its source electrode is in order to receive this burning voltage of positive polarity, and its drain electrode then is coupled to this compensation distribution of all dual pixels in (i+1) row or (i+2) row pixel;
One the 3rd N transistor npn npn, its grid couple (i+1) bar sweep trace to receive said another corresponding sweep signal, and its source electrode is then in order to receive this second clock signal;
One the 4th electric capacity, its first end couples the drain electrode of the 3rd N transistor npn npn, and its second end then is coupled to this shared distribution; And
One the 4th N transistor npn npn, its grid couples the drain electrode of the 3rd N transistor npn npn, and its source electrode is in order to receive this burning voltage of negative polarity, and its drain electrode then is coupled to this compensation distribution of all dual pixels in (i+1) row or (i+2) row pixel.
17. LCD according to claim 14 is characterized in that, i the second voltage feeding unit comprises:
One the one N transistor npn npn, its grid couple i bar sweep trace to receive this corresponding sweep signal, and its source electrode is then in order to receive this first clock signal;
One the 3rd electric capacity, its first end couples the drain electrode of a N transistor npn npn, and its second end then is coupled to this shared distribution;
One the 2nd N transistor npn npn, its grid couples the drain electrode of a N transistor npn npn, and its source electrode is in order to receive this burning voltage of negative polarity, and its drain electrode then is coupled to this compensation distribution of all dual pixels in i row or (i+1) row pixel;
One the 3rd N transistor npn npn, its grid couple i bar sweep trace to receive this corresponding sweep signal, and its source electrode is then in order to receive this second clock signal;
One the 4th electric capacity, its first end couples the drain electrode of the 3rd N transistor npn npn, and its second end then is coupled to this shared distribution; And
One the 4th N transistor npn npn, its grid couples the drain electrode of the 3rd N transistor npn npn, and its source electrode is in order to receive this burning voltage of positive polarity, and its drain electrode then is coupled to this compensation distribution of all dual pixels in i row or (i+1) row pixel.
18. LCD according to claim 14 is characterized in that, (i+1) individual second voltage feeding unit comprises:
One the one N transistor npn npn, its grid couple (i+1) bar sweep trace to receive said another corresponding sweep signal, and its source electrode is then in order to receive this first clock signal;
One the 3rd electric capacity, its first end couples the drain electrode of a N transistor npn npn, and its second end then is coupled to this shared distribution;
One the 2nd N transistor npn npn, its grid couples the drain electrode of a N transistor npn npn, its source electrode is in order to receiving this burning voltage of negative polarity, its drain electrode then be coupled in (i+1) row or (i+2) row pixel this compensation distribution of odd pixel;
One the 3rd N transistor npn npn, its grid couple (i+1) bar sweep trace to receive said another corresponding sweep signal, and its source electrode is then in order to receive this second clock signal;
One the 4th electric capacity, its first end couples the drain electrode of the 3rd N transistor npn npn, and its second end then is coupled to this shared distribution; And
One the 4th N transistor npn npn, its grid couples the drain electrode of the 3rd N transistor npn npn, its source electrode is in order to receiving this burning voltage of positive polarity, its drain electrode then be coupled in (i+1) row or (i+2) row pixel this compensation distribution of odd pixel.
19. a LCD is characterized in that, comprising:
One display panel comprises:
The multi-strip scanning line;
Many data lines are provided with said sweep trace is vertical substantially;
A plurality of pixels electrically connect with corresponding data line and sweep trace respectively, and said pixel is arranged with matrix-style, and each pixel comprises:
One shared distribution is used voltage altogether in order to receive; And
One compensation distribution is in order to receive a burning voltage; And
One voltage supply device couples this compensation distribution of each pixel, in order to continue and to supply this compensation distribution that this burning voltage is given each pixel accordingly;
Each pixel in the i row pixel more comprises:
One pixel transistor, its grid couples i bar sweep trace, and its source electrode then is coupled to i bar data line, and wherein i is a positive integer;
One first liquid crystal capacitance, its first end couples the drain electrode of this pixel transistor, and its second end then is coupled to uses electrode altogether; And
One storage capacitors, its first end couples the drain electrode of this pixel transistor, and its second end then is coupled to this shared distribution,
Wherein, this pixel transistor, this first liquid crystal capacitance and this storage capacitors are positioned at a penetrating region;
One first electric capacity, its first end couples the drain electrode of this pixel transistor;
One second liquid crystal capacitance, its first end couples second end of this first electric capacity, and its second end then is coupled to this common electrode; And
One second electric capacity, its first end couples second end of this first electric capacity, and its second end then is coupled to this compensation distribution,
Wherein, this first electric capacity, this second liquid crystal capacitance and this second electric capacity are positioned at an echo area;
This voltage supply device comprises:
One first sub-voltage supply device has a plurality of first voltage feeding units, wherein:
I the first voltage feeding unit is according to corresponding sweep signal, one first clock signal and one second clock signal, and this burning voltage that positive polarity is provided in i row or (i+1) row pixel this compensation distribution of odd pixel; And
(i+1) individual first voltage feeding unit is according to another corresponding sweep signal, this first clock signal and this second clock signal, and this burning voltage of positive polarity this compensation distribution to all dual pixels in (i+1) row or (i+2) row pixel is provided; And
One second sub-voltage supply device has a plurality of second voltage feeding units, wherein:
I the second voltage feeding unit is according to this first clock signal of this corresponding sweep signal and this second clock signal, and this burning voltage of negative polarity this compensation distribution to all dual pixels in i row or (i+1) row pixel is provided; And
(i+1) individual second voltage feeding unit is according to said this first clock signal of another corresponding sweep signal and this second clock signal, and this burning voltage that negative polarity is provided in (i+1) row or (i+2) row pixel this compensation distribution of odd pixel.
20. LCD according to claim 19 is characterized in that, the work period of this first clock signal is essentially during the picture of this LCD, and this second clock signal then continues to maintain the state of activation.
21. LCD according to claim 19 is characterized in that, i the first voltage feeding unit comprises:
One the one N transistor npn npn, its grid is coupled in its source electrode, to receive this second clock signal;
One the 2nd N transistor npn npn, its grid couples the drain electrode of a N transistor npn npn, its source electrode is in order to receiving this burning voltage of positive polarity, its drain electrode then be coupled in i row or (i+1) row pixel this compensation distribution of odd pixel;
One the 3rd N transistor npn npn, its grid couple i bar sweep trace to receive this corresponding sweep signal, and its source electrode is then in order to receive this first clock signal;
One the 3rd electric capacity, its first end couples the drain electrode of the 3rd N transistor npn npn, and its second end then is coupled to this shared distribution;
One the 4th N transistor npn npn, its grid couples the drain electrode of the 3rd N transistor npn npn, and its source electrode is in order to receive this burning voltage of negative polarity, and its drain electrode then is coupled to the grid of the 2nd N transistor npn npn;
One the 5th N transistor npn npn; Its grid couples the drain electrode of the 3rd N transistor npn npn; Its source electrode is in order to receive this burning voltage of negative polarity; Its drain electrode then be coupled in i row or (i+1) row pixel this compensation distribution of odd pixel; Wherein i the first voltage feeding unit is more according to this second and 1 the 3rd clock signals of this corresponding sweep signal, this first clock signal and phase differential 180 degree, and provide this burning voltage of positive polarity to be listed as to i or (i+1) row pixel in this compensation distribution of odd pixel, wherein this is second with during the work period of the 3rd clock signal is essentially the activation of this corresponding sweep signal; And
One the 6th N transistor npn npn, its grid is coupled in to receive the 3rd clock signal with its source electrode, and its drain electrode then is coupled to the drain electrode of a N transistor npn npn.
22. LCD according to claim 19 is characterized in that, (i+1) individual first voltage feeding unit comprises:
One the one N transistor npn npn, its grid is coupled in its source electrode, to receive this second clock signal;
One the 2nd N transistor npn npn, its grid couples the drain electrode of a N transistor npn npn, and its source electrode is in order to receive this burning voltage of positive polarity, and its drain electrode then is coupled to this compensation distribution of all dual pixels in (i+1) row or (i+2) row pixel;
One the 3rd N transistor npn npn, its grid couple (i+1) bar sweep trace to receive said another corresponding sweep signal, and its source electrode is then in order to receive this first clock signal;
One the 3rd electric capacity, its first end couples the drain electrode of the 3rd N transistor npn npn, and its second end then is coupled to this shared distribution;
One the 4th N transistor npn npn, its grid couples the drain electrode of the 3rd N transistor npn npn, and its source electrode is in order to receive this burning voltage of negative polarity, and its drain electrode then is coupled to the grid of the 2nd N transistor npn npn;
One the 5th N transistor npn npn; Its grid couples the drain electrode of the 3rd N transistor npn npn; Its source electrode is in order to receive this burning voltage of negative polarity; Its drain electrode then is coupled to this compensation distribution of all dual pixels in (i+1) row or (i+2) row pixel; Wherein (i+1) individual first voltage feeding unit is more according to this second and 1 the 3rd clock signals of said another corresponding sweep signal, this first clock signal and phase differential 180 degree; And this burning voltage that positive polarity is provided is to this compensation distribution of all dual pixels in (i+1) row or (i+2) row pixel, and wherein, this is second with during the work period of the 3rd clock signal is essentially the activation of this corresponding sweep signal; And
One the 6th N transistor npn npn, its grid is coupled in to receive the 3rd clock signal with its source electrode, and its drain electrode then is coupled to the drain electrode of a N transistor npn npn.
23. LCD according to claim 19 is characterized in that, i the second voltage feeding unit comprises:
One the one N transistor npn npn, its grid is coupled in its source electrode, to receive this second clock signal;
One the 2nd N transistor npn npn, its grid couples the drain electrode of a N transistor npn npn, and its source electrode is in order to receive this burning voltage of negative polarity, and its drain electrode then is coupled to this compensation distribution of all dual pixels in i row or (i+1) row pixel;
One the 3rd N transistor npn npn, its grid couple i bar sweep trace to receive this corresponding sweep signal, and its source electrode is then in order to receive this first clock signal;
One the 3rd electric capacity, its first end couples the drain electrode of the 3rd N transistor npn npn, and its second end then is coupled to this shared distribution;
One the 4th N transistor npn npn, its grid couples the drain electrode of the 3rd N transistor npn npn, and its source electrode is in order to receive this burning voltage of negative polarity, and its drain electrode then is coupled to the grid of the 2nd N transistor npn npn;
One the 5th N transistor npn npn; Its grid couples the drain electrode of the 3rd N transistor npn npn; Its source electrode is in order to receive this burning voltage of positive polarity; Its drain electrode then is coupled to this compensation distribution of all dual pixels in i row or (i+1) row pixel; Wherein i the second voltage feeding unit is more according to this second and 1 the 3rd clock signals of this corresponding sweep signal, this first clock signal and phase differential 180 degree, and provide this burning voltage of negative polarity to be listed as to i or (i+1) row pixel in this compensation distributions of all dual pixels, wherein this is second with during the work period of the 3rd clock signal is essentially the activation of this corresponding sweep signal; And
One the 6th N transistor npn npn, its grid is coupled in to receive the 3rd clock signal with its source electrode, and its drain electrode then is coupled to the drain electrode of a N transistor npn npn.
24. LCD according to claim 19 is characterized in that, (i+1) individual second voltage feeding unit comprises:
One the one N transistor npn npn, its grid is coupled in its source electrode, to receive this second clock signal;
One the 2nd N transistor npn npn, its grid couples the drain electrode of a N transistor npn npn, its source electrode is in order to receiving this burning voltage of negative polarity, its drain electrode then be coupled in (i+1) row or (i+2) row pixel this compensation distribution of odd pixel;
One the 3rd N transistor npn npn, its grid couple (i+1) bar sweep trace to receive said another corresponding sweep signal, and its source electrode is then in order to receive this first clock signal;
One the 3rd electric capacity, its first end couples the drain electrode of the 3rd N transistor npn npn, and its second end then is coupled to this shared distribution;
One the 4th N transistor npn npn, its grid couples the drain electrode of the 3rd N transistor npn npn, and its source electrode is in order to receive this burning voltage of negative polarity, and its drain electrode then is coupled to the grid of the 2nd N transistor npn npn;
One the 5th N transistor npn npn; Its grid couples the drain electrode of the 3rd N transistor npn npn; Its source electrode is in order to receive this burning voltage of positive polarity; Its drain electrode then be coupled in (i+1) row or (i+2) row pixel this compensation distribution of odd pixel; Wherein (i+1) individual second voltage feeding unit is more according to this second and 1 the 3rd clock signals of said another corresponding sweep signal, this first clock signal and phase differential 180 degree; And this burning voltage that negative polarity is provided in (i+1) row or (i+2) row pixel this compensation distribution of odd pixel, wherein this is second with during the work period of the 3rd clock signal is essentially the activation of this corresponding sweep signal; And
One the 6th N transistor npn npn, its grid is coupled in to receive the 3rd clock signal with its source electrode, and its drain electrode then is coupled to the drain electrode of a N transistor npn npn.
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