CN101539698B - Display array substrate - Google Patents
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- CN101539698B CN101539698B CN2008101024811A CN200810102481A CN101539698B CN 101539698 B CN101539698 B CN 101539698B CN 2008101024811 A CN2008101024811 A CN 2008101024811A CN 200810102481 A CN200810102481 A CN 200810102481A CN 101539698 B CN101539698 B CN 101539698B
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Abstract
The invention discloses a display array substrate. A switching device is arranged on the substrate and between two rows of adjacently scanned grid lines along the scanning sequence of the grid lines, the switching device is used for turning on and off between the grid lines later scanned in the two rows of the adjacently scanned grid lines and a common electrode component, and the control end component of the switching device is in electric contact with the grid lines first scanned in the two rows of the adjacently scanned grid lines. By using the invention, the charging capacities of the sub-pixels at the far ends of the grid lines can be enhanced, therefore, the uniformity of the charging rate of the entire row of the sub-pixels on the array substrate is enhanced, the difficulty of sufficient charging is lowered, meanwhile, the charging time of the sub-pixels on each row of the grid lines can be reduced, the charging time of the entire display is further reduced, and the charging demands of the high-resolution display can be met.
Description
Technical field
The present invention relates to the substrate design field of display, relate in particular to and a kind ofly can realize the precharge display array substrate of grid.
Background technology
At present, adopt the display of active matrix scanning display technique to reach its maturity, wherein typical representative has Thin Film Transistor-LCD (TFT-LCD) and thin film transistor (TFT) organic light emitting display (TFT-OLED) etc.The characteristics of active matrix progressive display are: adopt the array base palte with the sub-pix matrix structure that is divided into by multirow grid line and multi-column data line, scan mode can be to line by line scan or staggered scanning, wherein each matrix dot is exactly a sub-pix, i.e. a basic unit of display; Each inferior pixel comes down to a display unit that can charge, by the control of charging of an active component, this active component can be three end active components or two end active components, commonly used is three end active components at present, therefore the general TFT that adopts is called the TFT display again to the display that adopts TFT to carry out active control usually.
For the active matrix type scanner, the circuit framework of array base palte is similar basically, is that example describes below with TFT-LCD.
Fig. 1 is the circuit framework exemplary plot of present TFT-LCD array base palte.Array base-plate structure comprises grid line and the data line that is formed on the substrate, forms pixel electrode in the pixel region that grid line and data line limit, and forms thin film transistor (TFT) at infall, and thin film transistor (TFT) comprises gate electrode and source, drain electrode.Referring to Fig. 1, this array base palte has the sub-pix matrix structure that is divided into by multirow grid line and multi-column data line.Described V
Gn, V
Gn+1, V
Gn+2Be respectively n, the n+1 of this array base palte, the voltage of n+2 bar grid line, V
ComVoltage for the public electrode of this array base palte lead-in wire.In a sub-pix 100, described C
LcBe the liquid crystal capacitance that forms between pixel electrode on the TFT substrate and the public electrode on the color membrane substrates, be used to utilize the corresponding data line charging, make the liquid crystal deflecting element of sub-pix, make inferior pixel demonstrate corresponding gray scale, C
StBe memory capacitance, be used to keep the charging voltage of sub-pix, so that the show state of sub-pix lasts till charging next time.Described TFT 101 is equivalent to a switching device, in the actual substrate structure is to be made of grid member, source electrode member and drain components.As shown in Figure 1, by Control of Voltage drain components D on the TFT 101 grid member G and the turn-on and turn-off between the source electrode member S, when grid line causes voltage on the grid member G greater than then conducting drain components of threshold value D and source electrode member S to electricity, data drive circuit can apply voltage data signal so that described liquid crystal capacitance is charged to data line, voltage on grid member G then turn-offs drain components D and source electrode member S less than threshold value, but owing to store voltage in the memory capacitance, interelectrode liquid crystal layer molecule continues to have the effect of voltage applied field, thereby liquid crystal layer can stably be worked up to charging next time.
TFT-LCD is shown as the display mode that a kind of voltage keeps, and when showing each frame picture, the voltage that fills on each sub-pix need be stablized and remains to the next frame picture.Referring to Fig. 1, if TFT-LCD is the charging modes of lining by line scan, the grid line driving circuit is input waveform grid line signal voltage (V in as Fig. 1 on each row grid line left end successively
Gn, V
Gn+1, V
Gn+2Shown in), the TFT that will be connected with each row grid line opens in regular turn, allows whole row's data line simultaneously the sub-pix of a full line is charged to required separately voltage well, shows different GTGs.When delegation was charged, the voltage on this row grid line was closed, and the voltage of next line grid line is opened then, was charged by the sub-pix of identical row's data line to next line again.So go down in regular turn, when the sub-pix of the last column of having substituted the bad for the good, just again back from the beginning since the charging again of first row.If interlace mode, waveform grid line signal voltage is imported in the interlacing of grid line driving circuit on described grid line, and for example general odd-numbered line of scanning earlier scans even number line again after having scanned odd-numbered line, and the displaying principle of inferior pixel is the same with lining by line scan.
But there is following defective in above-mentioned existing display array substrate:
The resistance of grid line and electric capacity can produce the grid line signal and postpone, and cause the charge rate (being equivalent to charging ability) of the sub-pix far away more apart from the grid line signal input part low more, and the charge rate homogeneity of each sub-pix is relatively poor on the whole piece grid line, and pixel voltage charges into confusion.
Fig. 2 is the structural representation of the grid line signal delay of existing array base palte.This Fig. 2 is an equivalent circuit diagram from the angle of signal delay.Referring to Fig. 2, left upper end is grid line voltage V
gSignal input part, so the charging direction for from left to right, along charging direction, each inferior pixel can be regarded as the combination of resistance and electric capacity, for example for one of them sub-pix 100, comprises resistance 201 and electric capacity 202.Along described charging direction, different resistance values and capacitance are arranged in each position.Along with the increase of the distance of signal input part, therefore the increase that the resistance of grid line and electric capacity all can direct ratios causes the distance signal input end far away more, the signal delay of grid line is big more.Fig. 3 is the effect synoptic diagram of the grid line signal delay of existing array base palte.Referring to Fig. 3, horizontal ordinate is the time, ordinate is a voltage, rectangle swash 301 wherein is the square-wave voltage of the signal input part input of grid line, each bar curve of left side is the rising edge track near to each sub-pix TFT grid voltage far away apart from the grid line signal input part, each bar curve of right side is the negative edge track near to each sub-pix TFT grid voltage far away apart from the grid line signal input part, and described solid line 302 is for making the grid voltage line of TFT conducting.The area that the rising edge track of described sub-pix TFT grid voltage, negative edge track and described square-wave voltage line 301 and turn-on grid electrode pressure-wire 302 are surrounded has embodied the charging ability of this sub-pix memory capacitance, and the big more charging ability of area is strong more.From Fig. 3, can find out significantly, sub-pix distance signal input end is far away more, its corresponding TFT grid voltage postpones big more, the duration of charging of the memory capacitance of this sub-pix is short more, charging ability is weak more, thereby cause the charge rate homogeneity of each sub-pix of full line grid line relatively poor, pixel voltage charges into the comparison confusion.
In order to prevent the confusion that charges into of pixel voltage, improve the homogeneity of charge rate, the normally artificial delayed data line signal of present improvement project is promptly given the electricity time electricity time lag given of the data-signal on the data line in grid line.Yet, also reduced duration of charging of pixel electrode in the time of delayed data line signal, cause the reduction of charging ability, increased the difficulty of abundant charging.On the other hand, under certain process capability,, can only realize problems such as this can cause residually resembling, brightness reduction by increasing the TFT size if improve the charging ability of TFT.
Summary of the invention
In view of this, technical matters to be solved by this invention is to provide a kind of display array substrate, to improve the homogeneity of the charge rate of full line sub-pix on the array base palte.
In order to realize the foregoing invention purpose, main technical schemes of the present invention is:
A kind of display array substrate, array base-plate structure comprises grid line and the data line that is formed on the substrate, form pixel electrode in the pixel region that grid line and data line limit, and at infall formation thin film transistor (TFT), thin film transistor (TFT) comprises gate electrode and source, drain electrode, scanning sequency along grid line, be provided with switching device between the two row grid lines of adjacent scanning, the grid line that at first scans in the two row grid lines of the control end member of this switching device and described adjacent scanning electrically contacts, when grid line is opened, this control end member is controlled described switching device, conducting between the grid line that makes back scanning in the two row grid lines of described adjacent scanning and the public electrode member, this switching device also are used for realizing grid line that two row grid lines backs of described adjacent scanning are scanned and the shutoff between the public electrode member.
Preferably, the scanning sequency of described display array substrate is for lining by line scan, and two row grid lines of described adjacent scanning are grid line adjacent line by line on physical space.
Preferably, the scanning sequency of described display array substrate is staggered scanning, and two row grid lines of described adjacent scanning are the adjacent grid line of interlacing on physical space.
Preferably, the switching device between two of the described adjacent scanning row grid lines is arranged on the signal input end of two row grid lines of described adjacent scanning.
Preferably, switching device between the two row grid lines of described adjacent scanning is for constituting the construction of switch of thin film transistor (TFT), constitute wherein in the two row grid lines of the member of this film crystal tube grid and described adjacent scanning at first that the grid line of scanning electrically contacts, the member that constitutes these other the two poles of the earth of thin film transistor (TFT) respectively with two row grid lines of described adjacent scanning in the grid line and the public electrode member of back scanning electrically contact.
Preferably, described public electrode member is the public electrode lead-in wire on the array base palte.
Preferably, described public electrode member provides the lead-in wire of common electric voltage for the array base palte periphery for color membrane substrates.
Preferably, described display array substrate is a thin-film transistor LCD device array substrate.
Preferably, described display array substrate is the organic light emitting display array base palte.
Among the present invention, along scanning sequency, be provided with switching device between the two row grid lines of adjacent scanning, this switching device is used to realize the grid line of back scanning and the turn-on and turn-off between the public electrode member, and the control end member of this switching device electrically contacts with the grid line of at first scanning, when certain delegation's grid line is opened, utilize described switching device conducting, the grid line of next line scanning is poured common electric voltage, thereby can improve the charging ability of the sub-pix far away effectively, improve the charge rate homogeneity of full line sub-pix on the array base palte apart from the grid line signal input part.Simultaneously, owing to adopt array structure of the present invention just can improve the homogeneity of full line sub-pix, thus can avoid artificial delayed data line signal, further guaranteed the charging ability of sub-pix, reduced the difficulty of abundant charging.
In addition, for line by line or the display of staggered scanning charging, the duration of charging of sub-pix can reduce along with the raising of substrate line number.Full HD resolution with 60Hz is example, and the duration of charging of pixel is in 15 microseconds.And adopt array structure of the present invention, owing to can on the full line grid line, charge into common electric voltage in advance, therefore the duration of charging of sub-pix on each row grid line can be reduced, and then the duration of charging of reducing whole display, the charging demand of high resolution display can be satisfied.
Description of drawings
Fig. 1 is the circuit framework exemplary plot of present TFT-LCD array base palte;
Fig. 2 is the structural representation of the grid line signal delay of existing array base palte;
Fig. 3 is the effect synoptic diagram of the grid line signal delay of existing array base palte;
Fig. 4 is the circuit framework exemplary plot of a kind of TFT-LCD array base palte of lining by line scan of the present invention;
Fig. 5 is the line by line scan circuit framework exemplary plot of TFT-LCD array base palte of another kind of the present invention;
Fig. 6 is the circuit framework exemplary plot of a kind of staggered scanning TFT-LCD array base palte of the present invention.
Fig. 7 is the effect synoptic diagram of the grid line signal delay of array base palte of the present invention.
Embodiment
Below by specific embodiments and the drawings the present invention is described in further details.
Display array substrate of the present invention goes for the display that any employing active matrix scanning charging modes shows, for example TFT-LCD, and organic light emitting display (OLED) etc.These displays all comprise similar basic array structure, promptly comprise the sub-pix matrix structure that is divided into by multirow grid line and multi-column data line.
In following examples, be that the present invention will be described for example with the TFT-LCD array base palte.
The scan mode of display array substrate of the present invention can also can be staggered scanning, explanation respectively below for lining by line scan.
Fig. 4 is the circuit framework exemplary plot of a kind of TFT-LCD array base palte of lining by line scan of the present invention.Array base-plate structure comprises grid line and the data line that is formed on the substrate, forms pixel electrode in the pixel region that grid line and data line limit, and forms thin film transistor (TFT) at infall, and thin film transistor (TFT) comprises gate electrode and source, drain electrode.Referring to Fig. 4, this array base palte has the sub-pix matrix structure that is divided into by multirow grid line and multi-column data line, described V
Gn, V
Gn+1, V
Gn+2Be respectively n, the n+1 of this array base palte, the voltage of n+2 bar grid line, V
ComVoltage for the public electrode of this array base palte lead-in wire.In a sub-pix 100, described C
LcBe liquid crystal capacitance, be used to utilize the corresponding data line charging, make the liquid crystal deflecting element of sub-pix, make inferior pixel demonstrate corresponding gray scale, C
StBe memory capacitance, be used to keep the charging voltage of sub-pix, so that the show state of sub-pix lasts till charging next time.Just equivalent circuit diagram shown in Figure 4 in the board structure of reality, can be formed described C by concrete base plate structure
LcAnd C
StFor example in a kind of concrete structure, described C
LcMainly be by pixel electrode, be formed on public electrode on the color membrane substrates, and between the two folded liquid crystal constitute; Described C
StMainly be by pixel electrode, be formed on the TFT substrate public electrode and between the two folded insulation course and passivation layer constitute.Described TFT 101 is equivalent to a switch, in the actual substrate structure is to be made of grid member, source electrode member and drain components.As shown in Figure 4, in each sub-pix 100, grid member G and the grid line of TFT 101 electrically contact, and drain components D and data line electrically contact, and source electrode member S and pixel electrode 102 electrically contact; Voltage on the grid line is controlled conducting or shutoff between described source electrode member S and the drain components D by TFT grid member G.
Among this Fig. 4, described memory capacitance C
StBe to utilize the member and the pixel electrode that electrically contact with public electrode to constitute, this capacitor structure is called the memory capacitance (being Cs on common) based on public electrode.Certainly, in another kind of embodiment, as shown in Figure 5, described memory capacitance C
StAlso can utilize the member and the one's own profession pixel electrode 102 that electrically contact with the next line grid line to constitute, thereby form another kind of capacitor structure, be called memory capacitance (being Cs on gate) based on grid line.
Among Fig. 4 and the embodiment shown in Figure 5, along the order of lining by line scan, all be provided with derailing switch between every adjacent two row grid lines on the physical space, be used for realizing the grid line of described adjacent two row grid line back scannings and the turn-on and turn-off between the public electrode member, the grid line that at first scans in the conducting control end member of this switching device and the adjacent two row grid lines electrically contacts.
Switching device between the described adjacent two row grid lines is for constituting the construction of switch of thin film transistor (TFT), specific to Fig. 4 and the described circuit of Fig. 5, this switching device is TFT, and in other embodiments, described switching device also can be other transistor that can realize switching function.Referring to Fig. 4 and Fig. 5, the left side is the input end of grid line signal voltage, and TFT is arranged on the right end of described adjacent two row grid lines.TFT is connected the adjacent grid line of per two row.Wherein for n bar grid line and n+1 bar grid line, and TFT 421 and public electrode member between them have following architectural feature: the right end of n bar grid line and the grid member of described TFT 421 electrically contact, the right end of n+1 bar grid line and the source electrode member of described TFT 421 electrically contact, and the drain components of public electrode member and described TFT 421 electrically contacts; Perhaps, the right end of described n+1 bar grid line and the drain components of described TFT 421 electrically contact, and the source electrode member of public electrode member and described TFT 421 electrically contacts.In the structure of Cs on common, described public electrode member is the public electrode lead-in wire on the array base palte; In the structure of Cs on gate, described public electrode member provides the lead-in wire of common electric voltage for the array base palte periphery for color membrane substrates.
In array base palte of the present invention, when the capable grid line of n begins to scan, when being opening, the TFT between capable grid line of n and the capable grid line of n+1 also can open, and public electrode can reach the current potential of public electrode for the capable grid line charging of n+1 from the signal input far-end of the capable grid line of n+1.Yet the signal input part of the capable grid line of n+1 still has the input of low-voltage, and therefore the current potential of the capable grid line of n+1 can present linear variation.When the capable grid line signal input part of n+1 cut-in voltage, the far-end current potential of distance signal input end has been in high relatively position, thereby the signal delay of remote location can effectively be improved.
Fig. 6 is the circuit framework exemplary plot of a kind of staggered scanning TFT-LCD array base palte of the present invention.Referring to Fig. 6, along the staggered scanning order, on the physical space between the adjacent two row grid lines of interlacing (being between the adjacent odd-numbered line and between the adjacent even number line) all be provided with derailing switch, be TFT herein, be used for realizing the grid line of the two row grid lines back scannings that described interlacing is adjacent and the turn-on and turn-off between the public electrode member, the grid line that at first scans in the adjacent two row grid lines with interlacing of the conducting control end member of this switching device electrically contacts.For example be provided with TFT 601 between capable grid line of n and the capable grid line of n+2, be provided with TFT 602 between n+1 row grid line and the capable grid line of n+3, be provided with TFT 603 between n+2 and the capable grid line of n+4, and described each TFT is arranged on the right end of the adjacent two row grid lines of described interlacing.
Below with n bar grid line and n+2 bar grid line, and the architectural feature that has of TFT 601 between them and public electrode member be that example describes: the right end of n bar grid line and the grid member of described TFT601 electrically contact, the right end of n+2 bar grid line and the source electrode member of described TFT 601 electrically contact, and the drain components of public electrode member and described TFT 601 electrically contacts; Perhaps, the right end of described n+2 bar grid line and the drain components of described TFT 601 electrically contact, and the source electrode member of public electrode member and described TFT 601 electrically contacts.In the structure of Cs on common, described public electrode member is the public electrode lead-in wire on the array base palte; In the structure of Cs on gate, described public electrode member provides the lead-in wire of common electric voltage for the array base palte periphery for color membrane substrates.
In this interleaved embodiment, when the capable grid line of n is opening, TFT 601 between capable grid line of n and the capable grid line of n+2 also can open, and public electrode can reach the current potential of public electrode for the capable grid line charging of n+2 from the signal input far-end of the capable grid line of n+2.Yet the signal input part of the capable grid line of n+2 still has the input of low-voltage, and therefore the current potential of the capable grid line of n+2 can present linear variation.When the capable grid line signal input part of n+2 cut-in voltage, the far-end current potential of distance signal input end has been in high relatively position, thereby the signal delay of remote location can effectively be improved.
Fig. 7 is the effect synoptic diagram of the grid line signal delay of array base palte of the present invention.Referring to Fig. 7, horizontal ordinate is the time, ordinate is a voltage, rectangle swash 701 wherein is the square-wave voltage of the signal input part input of grid line, each bar curve of left side is the rising edge track near to each sub-pix TFT grid voltage far away apart from the grid line signal input part, each bar curve of right side is the negative edge track near to each sub-pix TFT grid voltage far away apart from the grid line signal input part, and described solid line 702 is for making the grid voltage of TFT conducting, and described dotted line 703 is a common electric voltage.From Fig. 7, can find out significantly, describedly increase to common electric voltage from closely beginning linearity from minimum voltage to the starting point of each sub-pix TFT grid voltage rising edge track far away apart from the grid line signal input part, that is to say before the one's own profession grid line is opened charging, the grid line far-end current potential of distance signal input end has been in high relatively position, thereby the signal delay of remote location can effectively be improved.The area that the rising edge track of described sub-pix TFT grid voltage, negative edge track and described square-wave voltage line 701 and turn-on grid electrode pressure-wire 702 are surrounded has embodied the charging ability of this sub-pix memory capacitance, the big more charging ability of area is strong more, compare with existing array base palte grid line signal delay effect shown in Figure 3, at distance grid line signal input part sub-pix far away, the area that embodies charging ability among Fig. 7 is significantly greater than the area of the embodiment charging ability of corresponding sub-pix among Fig. 3.Therefore, among the present invention, the sub-pix that the distance signal input end is far away more, the improvement of its charging ability is obvious more, thereby can improve the charge rate homogeneity of each sub-pix of full line grid line, prevents the confusion that pixel voltage charges into.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with the people of this technology in the disclosed technical scope of the present invention; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.
Claims (9)
1. display array substrate, array base-plate structure comprises grid line and the data line that is formed on the substrate, form pixel electrode in the pixel region that grid line and data line limit, and at infall formation thin film transistor (TFT), thin film transistor (TFT) comprises gate electrode and source, drain electrode, it is characterized in that, scanning sequency along grid line, be provided with switching device between the two row grid lines of adjacent scanning, the grid line that at first scans in the two row grid lines of the control end member of this switching device and described adjacent scanning electrically contacts, when grid line is opened, this control end member is controlled described switching device, conducting between the grid line that makes back scanning in the two row grid lines of described adjacent scanning and the public electrode member, this switching device also are used for realizing grid line that two row grid lines backs of described adjacent scanning are scanned and the shutoff between the public electrode member.
2. display array substrate according to claim 1 is characterized in that, the scanning sequency of described display array substrate is for lining by line scan, and two row grid lines of described adjacent scanning are grid line adjacent line by line on physical space.
3. display array substrate according to claim 1 is characterized in that, the scanning sequency of described display array substrate is staggered scanning, and two row grid lines of described adjacent scanning are the adjacent grid line of interlacing on physical space.
4. according to claim 1 or 2 or 3 described display array substrates, it is characterized in that the switching device between the two row grid lines of described adjacent scanning is arranged on the signal input end of two row grid lines of described adjacent scanning.
5. according to claim 1 or 2 or 3 described display array substrates, it is characterized in that, switching device between the two row grid lines of described adjacent scanning is for constituting the construction of switch of thin film transistor (TFT), constitute wherein in the two row grid lines of the member of this film crystal tube grid and described adjacent scanning at first that the grid line of scanning electrically contacts, the member that constitutes these other the two poles of the earth of thin film transistor (TFT) respectively with two row grid lines of described adjacent scanning in the grid line and the public electrode member of back scanning electrically contact.
6. display array substrate according to claim 5 is characterized in that, described public electrode member is the public electrode lead-in wire on the array base palte.
7. display array substrate according to claim 5 is characterized in that, described public electrode member provides the lead-in wire of common electric voltage for the array base palte periphery for color membrane substrates.
8. display array substrate according to claim 1 is characterized in that, described display array substrate is a thin-film transistor LCD device array substrate.
9. display array substrate according to claim 1 is characterized in that, described display array substrate is the organic light emitting display array base palte.
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| CN103489406B (en) * | 2013-10-08 | 2015-11-25 | 京东方科技集团股份有限公司 | A kind of pixel drive unit and driving method, image element circuit |
| CN104361855B (en) * | 2014-12-10 | 2017-06-09 | 上海天马微电子有限公司 | A kind of display panel and electronic equipment |
| CN106410931B (en) * | 2016-08-25 | 2019-04-05 | 京东方科技集团股份有限公司 | A kind of control method of capacitance module, control device and display device |
| CN107608153A (en) | 2017-09-28 | 2018-01-19 | 京东方科技集团股份有限公司 | Array base palte, liquid crystal display, display panel and its driving method |
| CN113257134B (en) * | 2021-05-28 | 2022-06-10 | 武汉华星光电技术有限公司 | Display panel and display device |
| CN115586667B (en) * | 2022-12-12 | 2023-03-28 | 合肥芯视界集成电路设计有限公司 | Charge sharing method of display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1550854A (en) * | 2003-04-30 | 2004-12-01 | 瀚宇彩晶股份有限公司 | Liquid crystal display panel,liquid crystal displayer and method for driving liquid crystal display |
| CN1564962A (en) * | 2001-10-02 | 2005-01-12 | 富士通显示技术株式会社 | Liquid crystal display device and method of fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1564962A (en) * | 2001-10-02 | 2005-01-12 | 富士通显示技术株式会社 | Liquid crystal display device and method of fabricating the same |
| CN1550854A (en) * | 2003-04-30 | 2004-12-01 | 瀚宇彩晶股份有限公司 | Liquid crystal display panel,liquid crystal displayer and method for driving liquid crystal display |
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