CN101526897B - High speed associate processor interface of embedded processor - Google Patents
High speed associate processor interface of embedded processor Download PDFInfo
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- CN101526897B CN101526897B CN2009100957835A CN200910095783A CN101526897B CN 101526897 B CN101526897 B CN 101526897B CN 2009100957835 A CN2009100957835 A CN 2009100957835A CN 200910095783 A CN200910095783 A CN 200910095783A CN 101526897 B CN101526897 B CN 101526897B
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Abstract
The invention provides a high speed associate processor interface of an embedded processor, comprising a first grade pipeline, a second grade pipeline and a third grade pipeline which are connected in sequence; wherein the first grade pipeline comprises a processor preserving stack and a command buffer, two associate processor commands are cached at most when the associate processor interface and the data of an external associate processor are in an interchange state, and current executable associate processor command is selected from the preserving stack and the command buffer to be transmitted to the next grade pipeline; the second grade pipeline comprises the functions of controlling logic, generating relevant associate processor to select and read/write signals, communicating data and transmitting the result to the next grade pipeline when the data read/write operation of the associate processor is finished; the third grade pipeline comprises the functions of sending data write back request to the embedded processor and feeding the result back to the embedded processor by an universal data bus. The invention increases the data transmission speed between the CPU and the associate processor and improves the performance of the processor.
Description
Technical field
The present invention relates to a kind of coprocessor interface of flush bonding processor.
Background technology
Coprocessor is for designing with the CPU collaborative work, and this processing unit makes with CPU and is used for bearing the computing of being carried out by the latter usually.Usually, coprocessor functions realizes in hardware to substitute several software instructions.By reducing multiple code command is single instruction, and the mode that directly realizes instruction in hardware, thereby code is quickened.Data communication between coprocessor and the CPU becomes a key factor that influences embedded system performance.The three kinds of basic forms that are connected with of coprocessor and CPU: be connected with cpu bus, be connected with I/O be connected (Instruction Pipeline Connection) with instruction pipelining.In addition, the mixed form that also has some these forms.The visit coprocessor needs special coprocessor instruction usually, in order to the read-write and the arithmetic operation of control coprocessor.Because the common arithmetic speed of coprocessor is slow than CPU, then the execution of coprocessor instruction can have influence on the continuity of CPU streamline, causes pipeline stall; The asynchronous speed that also can influence the coprocessor instruction execution of coprocessor and cpu clock; When a plurality of coprocessor of carry, the coordination strategy of a plurality of equipment rooms and switching mode also affect the continuity that cpu instruction is carried out.These all become the key factor that the design coprocessor interface requires careful consideration.
Summary of the invention
Slow for the data rate of the coprocessor interface that overcomes existing flush bonding processor, as to have weakened performance of processors deficiency the invention provides data rate between a kind of CPU of raising and the coprocessor, has promoted the high speed associate processor interface of embedded processor of performance of processors.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of high speed associate processor interface of embedded processor, comprise the first order streamline, second level streamline and the third level streamline that connect successively, first order streamline comprises that coprocessor keeps stack and instruction buffer, buffer memory two coprocessor instructions at the most when coprocessor interface and external coprocessor data interaction state are chosen current executable coprocessor instruction and are sent to the next stage streamline from keep stack and instruction buffer; Second level streamline comprises steering logic, produces corresponding coprocessor and selects and read-write, and the row data communication of going forward side by side after the data read-write operation of coprocessor is finished, is sent to the next stage streamline with the result who obtains; Third level streamline is initiated the request of data write-back to flush bonding processor, and the result is returned to flush bonding processor by the conventional data bus, described high speed coprocessor interface also comprises: the clocked logic module is used for carrying out the work of synchronous working pattern when described coprocessor interface and external coprocessor have identical high-frequency clock; When described coprocessor interface is asynchronous with the external coprocessor clock frequency, carry out the work of asynchronous working pattern, the data sync transmission between clock synchronization module control coprocessor and the CPU.
As preferred a kind of scheme: described high speed coprocessor interface also comprises the coprocessor instruction definition unit, is used to define coprocessor selection instruction, the instruction of coprocessor read data and the instruction of coprocessor write data; Wherein, the coprocessor selection instruction is chosen one of them from a plurality of coprocessors, coprocessor read data instruction reading of data and being written in the CPU general-purpose register of appointment from the coprocessor register of appointment, the instruction of coprocessor write data writes both given data to the coprocessor of choosing, and the wait coprocessor is handled these data.
Further, set coprocessor register control corresponding position and select obstruction and two kinds of instructions of unblock executive mode, wherein, the instruction blocking model is carried out coprocessor instruction by order, the second level streamline that the coprocessor instruction of submitting to is sent to coprocessor interface instructs executions, does not have the instruction of submission can be blocked on the first order streamline of coprocessor interface; Instruction unblock pattern allows the out of order execution of coprocessor instruction, and all coprocessor instructions are sent to the second level streamline of coprocessor interface and carry out.
Further, the coprocessor in elected occurs when unusual in the process of implementation, and exception vector returns to embedded microprocessor by coprocessor interface, and embedded microprocessor enters corresponding unusual service routine according to the exception vector that returns.
The support of described high speed coprocessor interface is 16 different coprocessors at the most, choose corresponding coprocessor by deciphering described coprocessor selection instruction, and the operation of the coprocessor reading and writing data instruction of back is to carry out alternately with current selected coprocessor.
Described high speed coprocessor interface also comprises: dynamic low power consumption control logic module is used for closing module clock when not having new coprocessor instruction and coprocessor interface to be in idle condition.
Technical conceive of the present invention is: adopt The pipeline design and special instruction, in conjunction with Clock Synchronization Technology, dynamic handoff technique and Low-power Technology, realized the high-speed data communication between coprocessor and the embedded microprocessor.
Beneficial effect of the present invention mainly shows: the 1) coprocessor interface of three class pipeline design, will carry out time delay distribution in three class pipeline, and realized the data high-speed transmission between CPU and the coprocessor;
2) three kinds of coprocessor special instructions, the simple and effective control that has realized coprocessor;
3), enlarged the scope of application of processor to the compatibility of sync cap and two kinds of mode of operations of asynchronous interface;
4) streamline executive mode and dynamically handoff technique have realized the executed in parallel between each coprocessor, have effectively improved performance of processors.
Description of drawings
Fig. 1 is a high speed coprocessor interface three class pipeline structural representation.
Fig. 2 is the synoptic diagram of the connected mode between high speed coprocessor interface and each coprocessor.
Embodiment
Below in conjunction with accompanying drawing the present invention is further described.
See figures.1.and.2, a kind of high speed associate processor interface of embedded processor, comprise the first order streamline, second level streamline and the third level streamline that connect successively, first order streamline comprises that coprocessor keeps stack and instruction buffer, buffer memory two coprocessor instructions at the most when coprocessor interface and external coprocessor data interaction state are chosen current executable coprocessor instruction and are sent to the next stage streamline from keep stack and instruction buffer; Second level streamline comprises steering logic, produces corresponding coprocessor and selects and read-write, and the row data communication of going forward side by side after the data read-write operation of coprocessor is finished, is sent to the next stage streamline with the result who obtains; Third level streamline is initiated the request of data write-back to flush bonding processor, and by the conventional data bus result is returned to flush bonding processor; Described high speed coprocessor interface also comprises: the clocked logic module is used for carrying out the work of synchronous working pattern when described coprocessor interface and external coprocessor have identical high-frequency clock; When described coprocessor interface is asynchronous with the external coprocessor clock frequency, carry out the work of asynchronous working pattern, the data sync transmission between clock synchronization module control coprocessor and the CPU.。
Described high speed coprocessor interface also comprises the coprocessor instruction definition unit, is used to define coprocessor selection instruction, the instruction of coprocessor read data and the instruction of coprocessor write data; Wherein, the coprocessor selection instruction is chosen one of them from a plurality of coprocessors, coprocessor read data instruction reading of data and being written in the CPU general-purpose register of appointment from the coprocessor register of appointment, the instruction of coprocessor write data writes both given data to the coprocessor of choosing, and the wait coprocessor is handled these data.
Described high speed coprocessor interface also comprises: dynamic low power consumption control logic module is used for closing module clock when not having new coprocessor instruction and coprocessor interface to be in idle condition.
The high speed associate processor interface of embedded processor of present embodiment, design is divided into three class pipeline, as shown in Figure 1.The high speed coprocessor interface is in the subordinate of register stage (RF) in the CPU streamline, promptly with CPU execution level (EX) peer.High speed coprocessor interface streamline is divided into three grades of EX1, EX2, EX3, the EX1 level the is multiplexing reservation stack of processor RF-EX level production line register as coprocessor interface, and be provided with instruction buffer (instruction buffer), be used for the buffer memory coprocessor instruction, this impact damper and can buffer memory when keeping stack and making coprocessor interface be in external coprocessor data interaction state two coprocessor instructions at the most, reduce the pause of the preceding level production line of CPU, promoted the performance of CPU.The steering logic of EX1 pipeline stages is chosen current executable coprocessor instruction and is sent to the next stage streamline from keep stack and instruction buffer.The EX2 streamline produces corresponding coprocessor and selects and read-write, and the row data communication of going forward side by side is in case after the data read-write operation of coprocessor finished, the result that the EX2 level production line will obtain was sent to the next stage streamline; The EX3 level is initiated the request of data write-back to CPU, and by conventional data bus (common data bus) result is returned to CPU, realizes collaborative work between the two.
Dynamically the low power consumption control logic is used for closing module clock when not having new coprocessor instruction and coprocessor interface to be in idle condition, reduces the ineffective power consumption under the off working state.
High speed associate processor interface of embedded processor at the most can 16 different coprocessors of carry, as shown in Figure 2, select the current coprocessor that carries out data interaction with CPU by the coprocessor selection instruction.Concrete executive mode is as follows: the coprocessor selection instruction is sent to the EX2 level, by the steering logic of EX2 level instruction is deciphered, and from choosing one 16 coprocessors at the most, carries out data interaction according to decode results with it.Can realize dynamic switching between coprocessor by different coprocessor selection instructions.
On the basis of original cpu instruction framework, in the idle instruction space, expanded the coprocessor instruction of three special uses, be respectively coprocessor selection instruction, the instruction of coprocessor read data and the instruction of coprocessor write data.The high speed coprocessor interface can be expanded and connect 16 coprocessors, and the coprocessor selection instruction is used for choosing one of them from 16 coprocessors at the most.Coprocessor read data instruction is responsible for from the coprocessor register of appointment reading of data and is written in the CPU general-purpose register of appointment, the instruction of coprocessor write data then is responsible for writing both given data to the coprocessor of choosing, and the wait coprocessor is handled these data.The data communication needs between CPU and the coprocessor had both effectively been satisfied in these three kinds of instructions, had also made full use of the idle instruction space, had promoted the scalability of CPU.
Coprocessor interface both can use the high-frequency clock identical with external coprocessor to carry out work (synchronous working pattern), also can with the nonsynchronous pattern of external coprocessor clock frequency under work, it is the asynchronous working pattern, under this pattern, the high speed coprocessor interface is by the data sync transmission between clock synchronization logic module realization coprocessor and the CPU.
Application program can be set coprocessor register control corresponding position and select obstruction and two kinds of instructions of unblock executive mode, wherein instruct blocking model to pass through order and carry out coprocessor instruction, realized unusual accurate, under this pattern, the back level production line that has only the coprocessor instruction of submission just can be sent to coprocessor interface instructs execution, the instruction that does not have to submit to can be blocked on the EX1 level production line of coprocessor interface, causes pipeline stall; And instruction unblock pattern allows the out of order execution of coprocessor instruction, it is unusual non-accurate model, under this pattern, all coprocessor instructions can be sent to the back level production line of coprocessor interface and carry out, no matter and whether they are submitted, therefore this pattern can not cause the pause of coprocessor interface streamline, has realized the high-speed transfer of data.
Coprocessor in elected occurs when unusual in the process of implementation, and this can in time return to CPU by coprocessor interface unusually, and CPU then enters corresponding unusual service routine according to the exception vector that returns.
Claims (6)
1. high speed associate processor interface of embedded processor, it is characterized in that: described high speed coprocessor interface comprises first order streamline, second level streamline and the third level streamline that connects successively, first order streamline comprises that coprocessor keeps stack and instruction buffer, buffer memory two coprocessor instructions at the most when coprocessor interface and external coprocessor data interaction state are chosen current executable coprocessor instruction and are sent to the next stage streamline from keep stack and instruction buffer;
Second level streamline comprises steering logic, produces corresponding coprocessor and selects and read-write, and the row data communication of going forward side by side after the data read-write operation of coprocessor is finished, is sent to the next stage streamline with the result who obtains;
Third level streamline is initiated the request of data write-back to flush bonding processor, and by the conventional data bus result is returned to flush bonding processor;
Described high speed coprocessor interface also comprises: the clocked logic module is used for carrying out the work of synchronous working pattern when described coprocessor interface and external coprocessor have identical high-frequency clock;
When described coprocessor interface is asynchronous with the external coprocessor clock frequency, carry out the work of asynchronous working pattern, the data sync transmission between clock synchronization module control coprocessor and the CPU.
2. high speed associate processor interface of embedded processor as claimed in claim 1, it is characterized in that: described high speed coprocessor interface also comprises the coprocessor instruction definition unit, is used to define coprocessor selection instruction, the instruction of coprocessor read data and the instruction of coprocessor write data; Wherein, the coprocessor selection instruction is chosen one of them from a plurality of coprocessors, coprocessor read data instruction reading of data and being written in the CPU general-purpose register of appointment from the coprocessor register of appointment, the instruction of coprocessor write data writes both given data to the coprocessor of choosing, and the wait coprocessor is handled these data.
3. high speed associate processor interface of embedded processor as claimed in claim 1 or 2, it is characterized in that: set coprocessor register control corresponding position and select obstruction and two kinds of instructions of unblock executive mode, wherein, the instruction blocking model is carried out coprocessor instruction by order, the second level streamline that the coprocessor instruction of submitting to is sent to coprocessor interface instructs executions, does not have the instruction of submission can be blocked on the first order streamline of coprocessor interface; Instruction unblock pattern allows the out of order execution of coprocessor instruction, and all coprocessor instructions are sent to the second level streamline of coprocessor interface and carry out.
4. high speed associate processor interface of embedded processor as claimed in claim 3, it is characterized in that: the coprocessor in elected occurs when unusual in the process of implementation, exception vector returns to embedded microprocessor by coprocessor interface, and embedded microprocessor enters corresponding unusual service routine according to the exception vector that returns.
5. high speed associate processor interface of embedded processor as claimed in claim 2, it is characterized in that: the support of described high speed coprocessor interface is 16 different coprocessors at the most, choose corresponding coprocessor by deciphering described coprocessor selection instruction, the operation of the coprocessor reading and writing data instruction of back is to carry out alternately with current selected coprocessor.
6. high speed associate processor interface of embedded processor as claimed in claim 2 is characterized in that: described high speed coprocessor interface also comprises:
Dynamically the low power consumption control logic module is used for closing module clock when not having new coprocessor instruction and coprocessor interface to be in idle condition.
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