CN101523734B - Method and apparatus for turbo encoding - Google Patents
Method and apparatus for turbo encoding Download PDFInfo
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- CN101523734B CN101523734B CN2007800375918A CN200780037591A CN101523734B CN 101523734 B CN101523734 B CN 101523734B CN 2007800375918 A CN2007800375918 A CN 2007800375918A CN 200780037591 A CN200780037591 A CN 200780037591A CN 101523734 B CN101523734 B CN 101523734B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
- H03M13/353—Adaptation to the channel
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3994—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using state pinning or decision forcing, i.e. the decoded sequence is forced through a particular trellis state or a particular set of trellis states or a particular decoded symbol
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/618—Shortening and extension of codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/6306—Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
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Abstract
An apparatus for encoding an information bit stream using turbo code is provided. The apparatus includes a temporary bit generator for creating a temporary bit stream, an interleaver for independentlyreceiving the information bit stream and the temporary bit stream, a first constituent encoder for independently receiving the information bit stream and the temporary bit stream and generating a fir st parity bit stream and a second constituent encoder for receiving an output of the interleaver and generating a second parity bit stream. Performance of a turbo code can be enhanced without changinga code rate by making a decoded bit stream longer.
Description
Technical field
The present invention relates to radio communication, and be particularly related to and be used for turbo Methods for Coding and device.
Background technology
In wireless communication system, transmit digital signal through various propagation paths.In addition, from recording medium reproducing digital signal such as CD (CD) or digital versatile disc (DVD).Because be transmitted and noise or distortion when reproducing through various channels, digital signal possibly comprise various error in data.
A kind of technology that is used for error correction is an error correction coding.Error correction coding is added extra-code to data, makes the time marquis who in data, comprises mistake to recover proper data.
Turbo code is a kind of error correction coding.Conventional turbo sign indicating number uses duo-binary recursive systematic convolution code for single input.Different with the conventional turbo sign indicating number of an input of each processing, each nonbinary turbo sign indicating number of handling a plurality of inputs has simultaneously been proposed again.Can be with reference to Proc.Inf.Theory Workshop; Cairns, Australia, sep.2001; Pp.61-63; C.Berrou, M.Jezequel, " the The advantages of non-binaryturbo codes (advantage of nonbinary turbo sign indicating number) " of C.Douillard and S.Kerouedan is as the example of nonbinary turbo sign indicating number.
Because the advantage that had compared with conventional turbo sign indicating number of nonbinary turbo sign indicating number, with the duobinary system turbo sign indicating number of one of nonbinary turbo sign indicating number as the ETSI 301 790 of the return path (DVB-RCS) of DVB-via satellite and the standard of IEEE (IEEE) 802.16-2004 chapter 8.3.3.2.3.In above standard, binary system turbo sign indicating number also is called as convolution turbo sign indicating number.
Code check (code rate) can be defined as the length of the length of information bit stream divided by coding stream.For example, if the length of coding stream be 30 and the length of information bit stream be 10, then code check is 1/3rd.
Information bit stream is long more, and it is long more that coding stream just becomes, and has improved the performance of turbo sign indicating number.If when code check remains unchanged, confirmed the length of information bit stream, then also just confirmed the length of coding stream.Give constant bit rate, limited the performance of improving the turbo sign indicating number.
Therefore, there are such needs, under the situation that does not increase coding stream length, improve the performance of turbo sign indicating number with given code check.
Summary of the invention
Technical problem
The present invention is provided for turbo Methods for Coding and device through using interim position.
Technical scheme
On the one hand, provide use turbo sign indicating number to come the device of coded message bit stream.Said device comprises: be used to produce interim bit stream interim position maker, be used for the independent interleaver that receives information bit stream and interim bit stream, be used for independent receive information bit stream and interim bit stream and generate first of first parity bit stream form encoder and be used to receive the output of interleaver and generate second of second parity bit stream and form encoder.
On the other hand, the method for using the turbo sign indicating number to come the coded message bit stream is provided.Said method comprises: generate the interim bit stream that does not rely on information bit stream, and generate parity bit stream through coded message bit stream and interim bit stream.
Excellent results
Under the situation that does not change code check,, can improve the performance of turbo sign indicating number through making the decoding bit stream longer.In addition, do not generate interim bit stream and allow interim bit stream to influence the generation of turbo coding stream, can improve the reliability of turbo sign indicating number through relying on information bit stream.
Description of drawings
Fig. 1 is the block diagram that communication system is shown.
Fig. 2 illustrates the block diagram of code device according to an embodiment of the invention.
Fig. 3 illustrates the block diagram of code device according to another embodiment of the present invention.
Fig. 4 is the block diagram that illustrates according to the code device of further embodiment of this invention.
Fig. 5 illustrates the block diagram of decoding device according to an embodiment of the invention.
Fig. 6 illustrates the sketch map that embeds the interim bit stream in the systematic bit that receives.
Shown in Figure 7 is the chart of the simulation result of simulation result more of the present invention and routine techniques.
Fig. 8 is the block diagram that illustrates according to the code device of further embodiment of this invention.
Embodiment
Hereinafter, will be described in detail with reference to the attached drawings exemplary embodiment of the present invention.In addition, in the accompanying drawing of the explanation embodiment of the invention, the key element with identical function will use identical Reference numeral and details is represented, will not be repeated thereafter.
Present technique can be used to down link or up link.Down link refers to from the base station (BS) to the communication of mobile radio station (MS), and up link refers to the communication from MS to BS.Usually, BS is corresponding to the fixed station that communicates with MS, and BS can be called as Node B, base station transceiver system (BTS), access point or the like.MS is corresponding to fixed station or mobile radio station, and MS can be called as subscriber equipment (UE), user terminal (UT), subscriber station (subscriberstation), wireless device or the like.
Fig. 1 is the block diagram that wireless communication system is shown.Wireless communication system is disposed in order to various communication services to be provided, such as voice, grouping, data or the like widely.
With reference to figure 1, wireless communication system comprises reflector 100 and receiver 200.In down link, reflector 100 can be the part of BS, and receiver 200 can be the part of MS.In up link, reflector 100 can be the part of MS, and receiver 200 can be the part of BS.BS can comprise a plurality of receivers and reflector.MS can comprise a plurality of receivers and reflector.
120 pairs of inputs of channel encoder data are encoded to form bits of coded.Channel encoder can be carried out the turbo coding.
If detected mistake, receiver 200 can be asked reflector 100 data that retransfer.In response to the request of retransferring, reflector 100 data that retransfer, and receiver 200 reaffirms in the data that retransfer, whether to have detected mistake.This is known as mixed automatic repeat request (HARQ).For HARQ, receiver 200 can further comprise the transmission circuit (not shown), and reflector 100 can further comprise the receiving circuit (not shown).
Hereinafter, description is used to use the turbo sign indicating number to carry out the technology of Code And Decode.Information bit refers to the data that are not encoded, and bits of coded refers to the data that are encoded.
Fig. 2 illustrates the block diagram of code device according to an embodiment of the invention.
With reference to figure 2, code device 300 comprises that interim position maker 310, interleaver 320, first form encoder 330, second and form encoder 340 and multiplexer 350.
Interim position maker 310 generates interim bit stream, and the length of this interim bit stream is identical with the length of information bit stream.Interim position maker 310 does not rely on information bit stream and generates interim bit stream.Interim the two all is known for code device 100 and decoding device (not shown), and the regular or order of the interim position of generation is not limited.For example, an interim maker 310 can repeat to generate the interim position with value ' 0 '.As replacement, interim position maker 310 can repeat to generate the interim position with value ' 1 '.Interim position maker 310 can repeat to generate the interim position with value ' 01 '.
Information bit stream becomes systematic bit X.This systematic bit is the copy of information bit stream.In systematic bit, do not comprise the interim bit stream that generates by interim position maker 310.Because interim bit stream is the bit stream of the previously known between code device 100 and the decoding device, so need not transmit interim bit stream.
Can make ins all sorts of ways makes and not to be included in interim bit stream in the systematic bit.For example, the output of an interim maker 310 can not be connected with the input of multiplexer 350.As replacement, though the output of position maker 310 is connected with the input of multiplexer 350 temporarily, in multiplexer 350, interim bit stream can be deleted cuts (a punctured out).In addition, can between interim position maker 310 and multiplexer 350, additional interim remover (not shown) be installed.
Interleaver 320 interweaves information bit stream and interim bit stream.Interleaver 320 does not rely on information bit stream and receives interim bit stream.Interleaver 320 receives as the information bit stream of first input with as the interim bit stream of second input.
First forms 330 pairs of information bit stream of encoder encodes with interim bit stream, and generates parity bit stream Y1.First forms encoder 330 does not rely on information bit stream and receives interim bit stream.Second forms 340 pairs of paired bit streams from interleaver 320 outputs of encoder encodes, and generates the second parity bit stream Y2.The first composition encoder 330 and second is formed encoder 340 can have identical duo-binary recursive systematic convolution code structure.
Though the first composition encoder 330 and second is formed encoder 340 one first parity bit stream Y1 and one second parity bit stream Y2 are provided respectively; But the quantity of the parity bit stream that the first composition encoder 330 and the second composition encoder 340 are provided is unrestricted, and can generate two or more parity bit stream.
Multiplexer 350 multiplex system bit streams, first parity bit stream and second parity bit stream.Multiplexer 350 receiving system bit stream X, the first parity bit stream Y1 and the second parity bit stream Y2, and at time per unit generation serial code bit stream (turbo coding stream).Multiplexer 350 can be deleted section (puncturing) to first parity bit stream or second parity bit stream according to the code check of expectation.
Interim position maker 310 generates interim bit stream, and the length of this interim bit stream is identical with the length of information bit stream.Information bit stream becomes systematic bit X and is imported into interleaver 320 and first forms encoder 330 in the two.Interim bit stream does not rely on information bit stream and is imported into the interleaver 320 and the first composition encoder 330 in the two.Each of information bit stream and interim bit stream is input to first bit by bit successively and is formed in encoder 330 and the interleaver 320.
First forms encoder 330 receives information bit stream and interim bit stream, and exports the first parity bit stream Y1.Information bit stream is imported into second with interim bit stream via interleaver 320 to be formed in the encoder 340, and second forms the encoder 340 outputs second parity bit stream Y2.Multiplexer 350 receiving system bit stream X, the first parity bit stream Y1 and the second parity bit stream Y2, and output encoder bit stream.
Corresponding information bit of 300, one system bits X of code device according to configuration as stated.The first parity bit stream Y1 distributes a position to an information bit and an interim position, and the second parity bit stream Y2 also distributes a position to an information bit and an interim position.So if the length of hypothesis information bit stream is n, then the length of coding stream is 3n, this coding stream length is the summation of systematic bit X, the first parity bit stream Y1 and the second parity bit stream Y2.Therefore, code check is 1/3rd.
Yet, cut (puncturing) or, can change code check through setting up a plurality of additional parity bit streams through deleting.For example, cut if 350 couples second parity bit stream Y2 of multiplexer delete, then code check becomes half the.Generate two first parity bit stream Y1 and W1 if first forms encoder 330, and second composition encoder two second parity bit stream Y2 of 340 generations and the W2, then code check becomes 1/4th.
Interim bit stream does not rely on information bit stream and is generated and be imported in the interleaver 320 and the first composition encoder 330.Through select effectively interim bit stream based on the interleaving scheme of interleaver 320, can improve the gain that interweaves.In addition, the two is all influential to first parity bit stream and second parity bit stream for interim bit stream.Because channel condition is generally smaller to the influence of interim bit stream, so can improve the reliability of turbo coding stream.
Fig. 3 illustrates the block diagram of code device according to another embodiment of the present invention.
With reference to figure 3, code device 400 comprises interim position maker 410, interleaver 420, the first composition encoder 430 and the second composition encoder 440.Code device 400 realizes that first of Fig. 2 forms encoder 330 and second and forms encoder 340.
Each initial condition that postpones 433a, 433b and 433c is ' 0 '.If information bit stream and interim bit stream are transfused to, then the first modulo 2 adder 436a carries out nodulo-2 addition to the carry-out bit of information bit, interim position, the first delay 433a and the carry-out bit of the 3rd delay 433c, and postpones the result that 433a provides nodulo-2 addition to first.The second modulo 2 adder 436b postpones the carry-out bit of 433a and the nodulo-2 addition of position execution temporarily to first, and postpones the result that 433b provides nodulo-2 addition to second.The 3rd modulo 2 adder 436c postpones the carry-out bit of 433b and the nodulo-2 addition of position execution temporarily to second, and postpones the result that 433c provides nodulo-2 addition to the 3rd.The 4th modulo 2 adder 436d postpones the carry-out bit execution nodulo-2 addition of carry-out bit and the 3rd delay 433c of 433b to the carry-out bit, second of the first modulo 2 adder 436a.The output of the 4th modulo 2 adder becomes first parity check bit.Therefore, the multinomial of first parity check bit is 1+D
2+ D
3
Fig. 4 is the block diagram that illustrates according to the code device of further embodiment of this invention.
With reference to figure 4, code device 500 comprises interim position maker 510, interleaver 520, the first composition encoder 530 and the second composition encoder 540.Code device 500 is different with the code device 400 of Fig. 3, because each of the first composition encoder 530 and the second composition encoder 540 is all exported two parity bit stream.
First forms encoder two first parity bit stream Y1 of 530 outputs and W1.The multinomial of the first bit stream Y1 of first parity bit stream is 1+D
2+ D
3Modulo 2 adder 536e postpones the carry-out bit execution nodulo-2 addition of 533c to the carry-out bit and the 3rd of the first modulo 2 adder 536a.Therefore, the multinomial of the second bit stream W1 of first parity bit stream is 1+D
3
Second forms encoder two second parity bit stream Y2 of 540 outputs and W2.The multinomial of the first bit stream Y2 of second parity bit stream is 1+D
2+ D
3In addition, the multinomial of the second bit stream W2 of second parity bit stream is 1+D
3
Owing to an information bit stream X is generated four parity bit stream, so code check is 1/5th.
Fig. 5 is the block diagram that illustrates according to the decoding device of the embodiment of the invention.
With reference to figure 5, decoding device 600 comprises interim embedding device 610, turbo decoder 630 and interim remover 650.The input of decoding device 600 comprises the system bits that receives, first parity check bit that receives and second parity check bit that receives, and these all are the signals that arrive through demodulate reception and detected.The system bits correspondence that receives is from the system bits of code device 300 outputs.The first parity check bit correspondence that receives is from first parity check bit of code device 300 outputs, and the second parity check bit correspondence that receives is from second parity check bit of code device 300 outputs.
Each value that is input to decoding device 600 is from the soft value (softvalue) of the position that channel receives.The system bits that receives refers to the soft value of the system bits that receives from channel; First parity check bit that receives refers to the soft value of first parity check bit that receives from channel, and second parity check bit that receives refers to the soft value of second parity check bit that receives from channel.
The systematic bit that interim position embedding device 610 receives interim bit stream embedding.The interim bit stream that embeds is with identical by the interim bit stream of the interim position maker generation of code device.The embedding value is the soft value of interim position.Wherein embedding has the bit stream of interim bit stream to be called as the decoding bit stream.
The turbo decoder is the general turbo sign indicating number decoder of operating by repetitive mode.First forms decoder 631 and second forms the decoder 632 first composition encoder and the second composition encoder of corresponding code device respectively.The decoding bit stream of 631 pairs of inputs of the first composition decoder carries out computing with first parity bit stream that receives, and is each data bit generation probability Estimation of 1 or 0.This probability Estimation is imported into second with second parity bit stream that receives and the decoding bit stream that interweaves and forms decoder 632.Repeat this process, until the iteration of accomplishing predetermined quantity or the satisfied predetermined error rate (BER).After accomplishing repetition, the 636 pairs of soft values in hard decision unit are made judgement and carry-out bit data.
Maximum a posteriori probability (MAP) algorithm can be applied to forming decoder 631 and 632.The MAP algorithm is the grid decoding algorithm, like the Viterbi algorithm.If in log-domain, carry out the MAP algorithm, then it is called as logarithm maximum a posteriori probability (log-MAP) algorithm.
Though is 3n from code device to the length of the coding stream of channel transmission, because the interim bit stream of length n is additional, the decoding bit stream length of in decoding device 600, decoding becomes 4n.Under the situation that does not change actual bit rate,, can improve the reliability of turbo sign indicating number through making the decoding bit stream longer.
Fig. 6 illustrates the sketch map that is embedded into the interim bit stream in the systematic bit that receives.
With reference to figure 6, when interim bit stream was embedded into the systematic bit that receives, interim bit stream can have high-reliability.For example, the soft value of interim bit stream can be bigger than the maximum soft value of the systematic bit that receives.Alternatively, the soft value of interim bit stream can be a times or many times of mean value of the systematic bit that receives.
Have the interim bit stream of unified amplitude shown in the figure, but do not limit for this reason.Can change the amplitude of interim bit stream.
Interim bit stream is embedded having high-reliability independently, and therefore, can limit because wrong path and selecteed possibility, and can realize reliable decoding.
Fig. 7 illustrates the chart of the simulation result of simulation result more of the present invention and routine techniques.The length of information bit stream is 480 bits, and in additive white Gaussian noise (AWGN) channel circumstance, uses BPSK modulation, 8 repeat decodings and logarithm maximal posterior probability algorithm.Conventional duobinary system turbo sign indicating number with 1/3rd code checks is used as routine techniques.
With reference to figure 7, its FER (FER) that illustrates among the present invention makes moderate progress than routine techniques.
Fig. 8 is the block diagram that illustrates according to the code device of further embodiment of this invention.
With reference to figure 8, code device 700 comprises that interim position maker 710, interleaver 720, first form encoder 730, second and form encoder 740 and multiplexer 750.Code device 700 is different with the code device 300 of Fig. 2, because be entered as right information bit at every turn.
If supposing the length of information bit stream is 2n, then the length of coding stream becomes 6n, and this coding stream is the summation of systematic bit A and B, the first parity bit stream Y1 and W1 and the second parity bit stream Y2 and W2.Therefore, code check becomes 1/3rd.
As replacement, if forming encoder 740, the first composition encoder 730 and second generates a parity bit stream respectively, then code check becomes half the.
Code device is described to two information bits of parallel receive, but code device can the individual information bit of parallel receive m (m >=1).In addition, the individual interim position of k (k >=1) maker can be set.During this time, form encoder and can have the structure of (m+k) binary system recursive systematic convolutional code.
The example of the code device that is applied to communication system has been described among the above embodiment.Yet code device can be applied to using the other system of turbo sign indicating number.For example, can code device be applied to tape deck, be used for data are recorded in the recording medium such as CD, DVD, tape or the like, or be applied to transcriber, be used for the recording medium reproducing data of record data from it.
Though below described the single output of single input (SISO) system with single transmit antenna and single reception antenna, thought of the present invention also can be applied to having multiple-input and multiple-output (MIMO) system of a plurality of transmitting antennas and a plurality of reception antennas.
The step of the described method of combination embodiment disclosed herein can be made up by hardware, software or its and realize.Can realize hardware by the application-specific integrated circuit (ASIC) that is designed to carry out above function (ASIC), Digital Signal Processing (DSP), programmable logic device (PLD), field programmable gate array (FPGA), processor, controller, microprocessor, other electronic unit or its combination.The module that is used to carry out above function can realize software.This software can be stored in the memory cell, and is carried out by processor.Memory cell or processor can use various device well-known to those skilled in the art.
Because the present invention can implement by some forms under the situation that does not deviate from its spirit or substantive characteristics; So should also be appreciated that; The foregoing description does not receive the restriction of any details described above; But should within defined spirit of claim and scope, broadly explain, except as otherwise noted.Therefore, claim should comprise the replacement that is equal to that drops in the interior all changes of claim scope and modification or this scope.
Claims (4)
1. use the turbo sign indicating number to come the device of coded message bit stream, said device comprises:
Interim position maker is used to generate interim bit stream, and the length of said interim bit stream equals the length of said information bit stream;
Interleaver is used to generate information bit stream that interweaves and the interim bit stream that interweaves, and the said information bit stream that interweaves generates through the said information bit stream that interweaves, and the said interim bit stream that interweaves generates through the said interim bit stream that interweaves;
First forms encoder, is used for generating first parity bit stream according to said information bit stream and said interim bit stream;
Second forms encoder, is used for generating second parity bit stream according to said information bit stream that interweaves and the said interim bit stream that interweaves; And
Multiplexer is used for generating and said information bit stream, said first parity bit stream and the said second parity bit stream system associated bit stream.
2. device according to claim 1, the wherein said first composition encoder and said second is formed encoder and is had identical duo-binary recursive systematic convolution code structure.
3. device according to claim 1, wherein said systematic bit are the copies of said information bit stream.
4. the method for using the turbo sign indicating number to come the coded message bit stream, said method comprises:
Generate interim bit stream, the length of said interim bit stream equals the length of said information bit stream;
Said information bit stream generates the information bit stream that interweaves through interweaving;
Said interim bit stream generates the interim bit stream that interweaves through interweaving;
Generate first parity bit stream according to said information bit stream and said interim bit stream;
Generate second parity bit stream according to said information bit stream that interweaves and the said interim bit stream that interweaves; And
Generate and said information bit stream, said first parity bit stream and the said second parity bit stream system associated bit stream.
Applications Claiming Priority (4)
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|---|---|---|---|
| KR1020060076990 | 2006-08-16 | ||
| KR1020060076990A KR101283862B1 (en) | 2006-08-16 | 2006-08-16 | Apparatus and method for encoding turbo code |
| KR10-2006-0076990 | 2006-08-16 | ||
| PCT/KR2007/003912 WO2008020712A1 (en) | 2006-08-16 | 2007-08-16 | Method and apparatus for turbo encoding |
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| CN101523734A CN101523734A (en) | 2009-09-02 |
| CN101523734B true CN101523734B (en) | 2012-12-26 |
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| CN2007800375918A Expired - Fee Related CN101523734B (en) | 2006-08-16 | 2007-08-16 | Method and apparatus for turbo encoding |
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| EP (1) | EP2055009B1 (en) |
| JP (1) | JP5204775B2 (en) |
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| CN101710850B (en) * | 2008-12-26 | 2013-10-30 | 三星电子株式会社 | Convolution Turbo encoding method and device for realizing encoding method |
| US20110072117A1 (en) * | 2009-09-23 | 2011-03-24 | Rovi Technologies Corporation | Generating a Synthetic Table of Contents for a Volume by Using Statistical Analysis |
| KR20110055410A (en) * | 2009-11-18 | 2011-05-25 | 삼성전자주식회사 | Method and apparatus for transmitting and receiving data in communication system |
| WO2011062424A2 (en) | 2009-11-18 | 2011-05-26 | Samsung Electronics Co., Ltd. | Method and apparatus for transmitting and receiving data in a communication system |
| US8386902B1 (en) * | 2009-12-16 | 2013-02-26 | Raytheon Company | Method and apparatus for rational puncturing of forward error correcting codes |
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| US8938663B2 (en) * | 2012-01-24 | 2015-01-20 | Broadcom Corporation | Modem architecture for joint source channel decoding |
| US9053698B2 (en) | 2012-01-24 | 2015-06-09 | Broadcom Corporation | Jitter buffer enhanced joint source channel decoding |
| KR101907943B1 (en) | 2012-01-31 | 2018-12-19 | 삼성전자주식회사 | Apparatus and method for transmitting/receiving data in a communication system |
| US9130595B1 (en) | 2013-11-07 | 2015-09-08 | The United States Of America As Represented By The Secretary Of The Navy | System and method for acceleration effect correction using turbo-encoded data with cyclic redundancy check |
| CN108111250A (en) * | 2016-11-25 | 2018-06-01 | 晨星半导体股份有限公司 | For the coding/decoding method of convolution code decoding apparatus in communication system and relevant judgment module |
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Also Published As
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| KR20080015547A (en) | 2008-02-20 |
| EP2055009A4 (en) | 2010-06-09 |
| US8214727B2 (en) | 2012-07-03 |
| WO2008020712A1 (en) | 2008-02-21 |
| EP2055009A1 (en) | 2009-05-06 |
| EP2055009B1 (en) | 2013-10-16 |
| KR101283862B1 (en) | 2013-07-08 |
| CN101523734A (en) | 2009-09-02 |
| JP5204775B2 (en) | 2013-06-05 |
| JP2010500841A (en) | 2010-01-07 |
| US20100199145A1 (en) | 2010-08-05 |
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