CN101520769A - Method and system for data processing - Google Patents
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Abstract
The invention relates to the field of electric digital data processing, in particular to a method and a system for data processing, aiming to solve the problems that an additional storage unit is needed to be additionally arranged to carry out data sorting, thereby storage space occupied by FFT calculation is increased, and the power consumption is increased in the prior art. The method comprises the following steps: obtaining a data index value of each data needed to be read or written; carrying out code inversion calculation on the data index value, and obtaining a corresponding storage unit index value; reading the data from the storage unit which corresponds to the storage unit index value when the data are needed to be read, and writing the date into the storage unit which corresponds to the storage unit index value when the data are needed to be written. By adopting the method of the invention embodiment, the storage space can be saved, frequent reading and writing operations are avoided, and the treating efficiency of the FFT calculation is enhanced.
Description
Technical field
The present invention relates to electric digital data processing field, particularly a kind of system and method for data processing.
Background technology
Fast fourier transform (Fast Fourier Transform Algorithm, FFT) computing is computing most crucial in the signal processing, it for spectrum analysis, convolution with relevant, Design of Digital Filter and work such as realization, power spectrum calculate, transport function modeling and image processing quick operational method is provided.Under the prior art, the FFT computing comprises two kinds: first kind of elder generation carries out butterfly computation to the input data, butterfly computation output result reordered again; And second kind of elder generation reorders to the input data, and the counterweight ranking results is carried out butterfly computation again.
Be that example describes with first kind of FFT computing below.
Consult shown in Figure 1A, when carrying out the FFT computing, 16 data that butterfly computation output result comprises are out of order depositing, and need reorder to these 16 data to 16 numbers (N=16) of input, make it deposit order recovery one-tenth order.
Consult shown in Figure 1B, reordering promptly is out of order sequence X (0), X (8), X (4), X (12), X (2) ... X (15) deposits order and is converted to generic sequence X (0), X (1), X (2), X (3), X (4) ... .X (15).
Consult shown in Fig. 1 C, when 8 numbers (N=8) of input are carried out the FFT computing, the input data are: x (0), x (1), x (2), x (3), x (4), x (5), x (6), x (7), the out of order data of exporting behind butterfly computation are: X (0), X (4), X (2), X (6), X (1), X (5), X (3), X (7), the alphabetic data of output is after reordering: X (0), X (1), X (2), X (3), X (4), X (5), X (6), X (7).
By the example shown in Figure 1B as can be seen, when butterfly computation output result is reordered, need open up the data that a new N storage unit is used to deposit order.
Be that example describes with second kind of FFT computing below.
Consult shown in Fig. 1 D, when 8 numbers (N=8) of input are carried out the FFT computing, will reorder to these 8 data earlier, it is deposited be out of order sequence, again each out of order data are carried out butterfly computation, like this, 8 data that butterfly computation output result comprises are that order is deposited; Shown in Fig. 1 D, the input data are: x (0), x (1), x (2), x (3), x (4), x (5), x (6), x (7), the out of order data of output are after reordering: x (0), x (4), x (2), x (6), x (1), x (5), x (3), x (7), the alphabetic data of exporting behind butterfly computation is: X (0), X (1), X (2), X (3), X (4), X (5), X (6), X (7).
Obviously, front/rear at butterfly computation, need the data of storage unit be reordered, and when reordering, need open up a new N storage unit and be used to deposit out of order data.
In sum, use existing method to carry out FFT computing meeting and take a large amount of storage spaces, as, export the result for the N number that obtains importing through the order of FFT computing, need open up 2 * N storage unit; Simultaneously, use existing method to carry out FFT computing meeting and reduce treatment effeciency, as, in the process of reordering, all data all can be read once and write once, thereby have caused the too frequent of data read-write operation, have increased the required time of FFT computing.
Summary of the invention
The embodiment of the invention provides a kind of method and system of data processing, and its purpose is, does not need to increase extra storage unit and carries out data sorting, has reduced the shared storage space of FFT computing, has reduced the power consumption of system.
A kind of data handling system that the embodiment of the invention provides, this system comprises:
Memory storage, the storage unit index value that is used for sending according to address decoding device is preserved data, and wherein said memory storage is made of storage unit, the corresponding respectively corresponding storage unit index value of each storage unit;
Address decoding device is used to receive data index value, and the data index value of described data is carried out a yard bit inversion computing, obtains described storage unit index value, and sends described storage unit index value to described memory storage;
Data processing equipment, be used for when described data are the data that need read, generate read control signal and send to described memory storage, send data index value to described address decoding device simultaneously, when described data are the data that need write, generate write control signal and send to described memory storage, send data index value to described address decoding device simultaneously.
The method of a kind of data processing that the embodiment of the invention provides, this method comprises:
Address decoding device receives the data index value of each data that need read or write, and the data index value is carried out a yard bit inversion computing obtains corresponding storage unit index value;
When described data are the data that need read, read described data in the storage unit of data processing equipment from the memory storage of storage unit index value correspondence, when described data were the data that need write, data processing equipment was with in the storage unit in the memory storage of described data write storage unit index value correspondence;
Wherein said memory storage is made of storage unit, the corresponding respectively corresponding storage unit index value of each storage unit.
Embodiment of the invention memory storage, the storage unit index value that is used for sending according to address decoding device is preserved data, and wherein said memory storage is made of storage unit, the corresponding respectively corresponding storage unit index value of each storage unit; Address decoding device is used to receive data index value, and the data index value of described data is carried out a yard bit inversion computing, obtains described storage unit index value, and sends described storage unit index value to described memory storage; Data processing equipment, be used for when described data are the data that need read, generate read control signal and send to described memory storage, send data index value to described address decoding device simultaneously, when described data are the data that need write, generate write control signal and send to described memory storage, send data index value to described address decoding device simultaneously.Owing in the FFT calculating process, do not need data are sorted, just can accurately find the data that need, thereby save storage space; Simultaneously, avoid frequent read-write operation, and then reduced power consumption.
Description of drawings
Figure 1A is at butterfly computation synoptic diagram in the first kind FFT computing of 16 input data under the prior art of the present invention;
Figure 1B is the schematic flow sheet that reorders in the first kind FFT computing at 16 input data under the prior art of the present invention;
Fig. 1 C is at 8 first kind FFT computing synoptic diagram of importing data under the prior art of the present invention;
Fig. 1 D is at 8 second class FFT computing synoptic diagram of importing data under the prior art of the present invention;
Fig. 2 A is an embodiment of the invention data handling system structural representation;
Fig. 2 B is an address decoding device structural representation in the embodiment of the invention;
Fig. 2 C is an embodiment of the invention address inversion module structural representation;
Fig. 2 D is an embodiment of the invention address integrate module structural representation one;
Fig. 2 E is an embodiment of the invention address integrate module structural representation two;
Fig. 3 is the method flow synoptic diagram of embodiment of the invention data processing;
Fig. 4 is at the data storage synoptic diagram behind the sign indicating number bit inversion of 16 input data in the embodiment of the invention.
Embodiment
The embodiment of the invention is obtained the data index value of each data that need read or write; Described data index value is carried out a yard bit inversion computing, obtain corresponding storage unit index value; When described data are the data that need read, from the storage unit of storage unit index value correspondence, read described data, when described data are the data that need write, in the storage unit with described data write storage unit index value correspondence.Owing in the FFT calculating process, do not need data are sorted, just can accurately find the data that need, thereby save storage space; Simultaneously, avoid frequent read-write operation, and then reduced power consumption.In addition, the present invention also can the compatible multiple FFT that counts, and adapts to different application demands.
In the embodiment of the invention of introducing below, when carrying out the FFT computing at the N number, input data table is shown x (i), the index value of data x (i) is i, i ∈ [0, N-1].Described N is defined as 2 integral number power, i.e. N=2
m, as 8,16,32,64 ....In this N input deposit data N the storage unit of opening up in memory storage, wherein the index value of k storage unit is k, k ∈ [0, N-1].
Below in conjunction with Figure of description the embodiment of the invention is described in further detail.
Shown in Fig. 2 A, embodiment of the invention data handling system comprises: memory storage 10, address decoding device 20 and data processing equipment 30.
Concrete, memory storage 10 is determined corresponding storage area according to chip selection signal, determines corresponding storage unit according to the storage unit index value from storage area again.
Wherein, if read-write control signal is a sense data, then the data in the storage unit of storage unit index value and chip selection signal correspondence are exported to data processing equipment 30;
If read-write control signal for writing data, then will receive from the data storage of data processing equipment 30 in the storage unit of storage unit index value and chip selection signal correspondence.
Wherein, data processing equipment also was used for before obtaining index value, and the number of definite data that need read or write is determined yard bit number of bit inversion needs according to the number of the described data of determining.
In specific implementation process, address decoding device 20 is according to the inversion enable signal from data processing equipment 30, determine whether to carry out a yard bit inversion computing, if do not need, then will be from the data index value of data processing equipment 30 as the storage unit index value, and the storage unit index value that obtains to memory storage 10 outputs.
Wherein, data processing equipment 30 also is used for:
When the data index value of specified data correspondence is inequality with the storage unit index value of the storage unit of this data correspondence of storage (position of storing data is different), triggers 20 pairs of data index values of address decoding device and carry out a yard bit inversion computing (promptly sending sign indicating number bit inversion enable signal is enable).
In specific implementation process, data treating apparatus 30 is redefined for triggering address decoding device 20 the data index value is not carried out a yard bit inversion computing (promptly sending a sign indicating number bit inversion enable signal is disable).
Wherein, data processing equipment 30 also is used for:
When determining to need read data, receive data, and the data that receive are handled from memory storage 10;
When determining to need write data, the data after memory storage 10 sends processing.
In specific implementation process, address decoding device 20 judges whether to carry out a yard bit inversion according to the sign indicating number bit inversion enable signal of receiving, if the sign indicating number bit inversion enable signal that address decoding device 20 is received is disable, does not then carry out a yard bit inversion; If the sign indicating number bit inversion enable signal that address decoding device 20 is received is enable, then carry out a yard bit inversion.
Enumerate several triggering address decoding devices 20 that need below and carry out yard situation of bit inversion computing:
1) data x (0), x (1), x (2), x (3), x (4), x (5), x (6), x (7), x (8), x (9), x (10), x (11), x (12), x (13), x (14), x (15) need be distinguished write storage unit 0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15 o'clock, then trigger address decoding device 20;
2) data x (0), x (8), x (4), x (12), x (2), x (10), x (6), x (14), x (1), x (9), x (5), x (13), x (3), x (11), x (7), x (15) need be distinguished write storage unit 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 o'clock, then trigger address decoding device 20;
3) in the time of need data being read according to above-mentioned relation, then trigger address decoding device 20 from storage unit;
4) in the time of need be according to above-mentioned relation read/write individual data, then trigger address decoding device 20.
The concrete structure of address decoding device 20 can be referring to Fig. 2 B.
Wherein, the address bus among Fig. 2 B is 8, can increase or reduce the quantity of address bus as required, specifically needs how many bar address buss can be with reference to table 0:
| The data sum | Use the bar number of address wire |
| 16 | 4 |
| 32 | 5 |
| 64 | 6 |
| 128 | 7 |
| 256 | 8 |
| ...... | ...... |
Table 0
Wherein, address acquisition module 200 is used to obtain data index value and chip selection signal.
The address leads directly to module 210, and the data index value that is used for address acquisition module 200 is obtained sends to address integrate module 230 as the storage unit index value with said memory cells index value and chip selection signal.
Address inversion module 220, the data index value that is used for address acquisition module 200 is obtained is carried out a yard bit inversion, as the storage unit index value, the storage unit index value after handling is sent to address integrate module 230.
Address integrate module 230, the storage unit index value that the straight-through module 210 in address that is used for receiving is exported and/or the storage unit index value and the chip selection signal of address inversion module 220 outputs are integrated, and output.
Wherein, the inner structure of address inversion module 220 is referring to Fig. 2 C.
Address inversion module 220 can be supported N=8,16,32,64,128,256 etc. situation.
Address wire among Fig. 2 C is 8bits.
The line relation is: B[i]=I[total-1-i],
Total presentation address line sum wherein, 8 altogether of address wires; B[i] expression B i bar address wire; I[i] expression I i bar address wire
That is: I7 connects B0, and I6 connects B1, and I5 connects B2, and I4 connects B3, and I3 connects B4, and I2 connects B5, and I1 connects B6, and I0 connects B7.
Because 8 altogether of address wires can be supported 256 data at most, and if the total N difference of data index value, straight-through module 210 in address and address inversion module 220, and the address wire between the address integrate module 230 also can have any different, and describes respectively below:
If the input data are 256, the address wire characteristics of C are:
Since during N=256,256=2
8, data index value has been used 8 address wires, i.e. I[7,6,5,4,3,2,1,0];
It is B[7,6,5,4,3,2,1,0 that the storage unit index value of exporting after address inversion module 220 is inverted has been used 8 address wires];
Shu Chu storage unit index value has been used 8 address wires, i.e. C[7,6,5,4,3,2,1,0 at last];
At this moment, 8 of C are the result after being inverted, promptly 8 of B;
So: C[7]=and B[7], C[6]=B[6], C[5]=B[5], C[4]=B[4], C[3]=B[3], C[2]=B[2], C[1]=B[1], C[0]=B[0].
If the input data are 16, the address wire characteristics of C:
Since during N=16,16=2
4, data index value has been used 4 address wires, i.e. I[3,2,1,0];
It is B[7,6,5,4 that the storage unit index value of exporting after being inverted after address inversion module 220 is inverted has been used 4 address wires];
Shu Chu storage unit index value has been used 4 address wires, i.e. C[3,2,1,0 at last];
At this moment, low 4 of C are the result after being inverted, the i.e. high position of B.
C[3 so]=B[7], C[2]=B[6], C[1]=B[5], C[0]=B[4].
Address wire is 8bits, and the input data are 2
4In the time of=16, the line graph of address integrate module 230 is referring to 2D.
If the input data are 64, the address wire characteristics of C are:
When N=64,64=2
6, data index value has been used 6 address wires, i.e. I[5,4,3,2,1,0];
It is B[7,6,5,4,3,2 that the storage unit index value of exporting after address inversion module 220 is inverted has been used 4 address wires];
Shu Chu storage unit index value has been used 4 address wires, i.e. C[5,4,3,2,1,0 at last];
At this moment, low 6 of C are the result after being inverted, the i.e. high position of B.
C[5 so]=B[7], C[4]=B[6], C[3]=B[5], C[2]=B[4], C[1]=B[3], C[0]=B[2].
Therefore, address wire is 8bits, and the input data are 2
6In the time of=64, the line graph of address integrate module 230 is referring to 2E.
Be that example describes with 16,64,256 just above, other quantity data and the mode of introducing above are similar, repeat no more.
As can be seen, be not 256 o'clock in the input data from Fig. 2 D and Fig. 2 E, the high address line of C has been received the high address line of A.
In N=64,8 address wires can visit 2
8=256 storage unit.
256 storage unit can be deposited 4 groups of data, 64 every group data (256/64=4).
The 0th group of deposit data is 64 storage unit, and corresponding storage unit index value is 0～63;
The 1st group of deposit data is equivalent in 64 storage unit of adjacent more high address: in 256 storage unit, corresponding storage unit index value is 64～127;
The 2nd group of deposit data is equivalent in 64 storage unit of adjacent more high address: in 256 storage unit, corresponding storage unit index value is 128～191;
The 3rd group of deposit data is equivalent in 64 storage unit of adjacent more high address: in 256 storage unit, corresponding storage unit index value is 192～255;
The bit7 of the address of these 4 groups of data and bit6 are respectively 00,01,10,11.
Can be divided into 4 to these 256 storage unit like this, the bit7 of address wire and bit6 just can be used as chip selection signal.Promptly
When I[7～6]=00 the time, select the 0th;
When I[7～6]=01 the time, select the 1st;
When I[7～6]=10 the time, select the 2nd;
When I[7～6]=11 the time, select the 3rd;
Thus, just can read and write 256 data (64 data/group * 4 group).
When reading and writing the 0th group of data, I[7～6]=00; A[7～6]=00; C[7～6]=00;
When reading and writing the 1st group of data, I[7～6]=01; A[7～6]=01; C[7～6]=01;
When reading and writing the 2nd group of data, I[7～6]=10; A[7～6]=10; C[7～6]=10;
When reading and writing the 3rd group of data, I[7～6]=11; A[7～6]=11; C[7～6]=11;
Therefore, the high address line just can be used for doing chip selection signal.
Situation for N=64:
Low 6 of C are the result after being inverted, the i.e. high position of B; The high position of C is a chip selection signal;
C[7 so]=I[7]=A[7], C[6]=I[6]=A[6], C[5]=B[7], C[4]=B[6], C[3]=B[5], C[2]=B[4], C[1]=B[3], C[0]=B[2].
Thereby make full use of the capacity of storage unit, can not waste the capacity of storage unit because the input data are few.
Need to prove that other input data are 256 less than storing data conditions with storing data, every group of input data are that 64 situation is similar, repeat no more.
As shown in Figure 3, the method for embodiment of the invention data processing comprises the following steps:
The data index value of each data that need read or write sets in advance.
Wherein, memory storage is made of storage unit, the corresponding respectively corresponding storage unit index value of each storage unit
Wherein, can further include before the step 300:
The number of the definite data that need read or write of address decoding device is determined yard bit number of bit inversion needs according to the number of established data.
Wherein, in the step 301, address decoding device carries out a yard bit inversion computing to the data index value of obtaining and can further include:
When the data index value of address decoding device specified data correspondence is inequality with the storage unit index value of the storage unit of this data correspondence of storage (position of storing data is different), the data index value is carried out a yard bit inversion computing.
Wherein, when data were the data that need write, step 302 can further include:
Data processing equipment generates chip selection signal, and sends chip selection signal to address decoding device;
Address decoding device sends chip selection signal to memory storage;
Memory storage is determined corresponding storage area according to chip selection signal, and the storage unit of storage unit index value correspondence in the zone of determining is carried out write operation.
When data were the data that need read, step 302 can further include:
Data processing equipment generates chip selection signal, and sends chip selection signal to address decoding device;
Address decoding device sends chip selection signal to memory storage;
Memory storage is determined corresponding storage area according to chip selection signal, and the storage unit of storage unit index value correspondence in the zone of determining is carried out read operation
With 16 input data instances, the embodiment of the invention is described.
Wherein, the data index value of each data is consulted shown in the table 1 in the step 300, and the data index value of above-mentioned each data is respectively 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15.
In the present embodiment step 301, during to the computing of data index value i actuating code bit inversion, need carry out inverted order to the binary coding of data index value i and arrange, the pairing tens digit of inverted order binary coding that obtains promptly is corresponding storage unit index value j; In the present embodiment, data index value i is as shown in table 1 with the corresponding relation of corresponding storage unit index value j.
| ? i | The order binary coding | The inverted order binary coding | ? |
| 0 | 0000 | 0000 | 0 |
| 1 | 0001 | 1000 | 8 |
| 2 | 0010 | 0100 | 4 |
| 3 | 0011 | 1100 | 12 |
| 4 | 0100 | 0010 | 2 |
| 5 | 0101 | 1010 | 10 |
| 6 | 0110 | 0110 | 6 |
| 7 | 0111 | 1110 | 14 |
| 8 | 1000 | 0001 | 1 |
| 9 | 1001 | 1001 | 9 |
| 10 | 1010 | 0101 | 5 |
| 11 | 1011 | 1101 | 13 |
| 12 | 1100 | 0011 | 3 |
| 13 | 1101 | 1011 | 11 |
| 14 | 1110 | 0111 | 7 |
| 15 | 1111 | 1111 | 15 |
Table 1
I classifies data index value as, promptly 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15, j classifies the storage unit index value after the computing of actuating code bit inversion as, and promptly 0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15.
In the step 302, suppose that the data index value of need handling is 8 data, it is 1 storage unit that actual these data are arranged in the storage unit index value, is that data in 1 the storage unit are handled to the storage unit index value then, specifically referring to Fig. 4.
From the foregoing description as can be seen: embodiment of the invention memory storage, the storage unit index value that is used for sending according to address decoding device is preserved data, wherein said memory storage is made of storage unit, the corresponding respectively corresponding storage unit index value of each storage unit; Address decoding device is used to receive data index value, and the data index value of described data is carried out a yard bit inversion computing, obtains described storage unit index value, and sends described storage unit index value to described memory storage; Data processing equipment, be used for when described data are the data that need read, generate read control signal and send to described memory storage, send data index value to described address decoding device simultaneously, when described data are the data that need write, generate write control signal and send to described memory storage, send data index value to described address decoding device simultaneously.Owing in the FFT calculating process, do not need data are sorted, just can accurately find the data that need, thereby save storage space; Simultaneously, avoid frequent read-write operation, and then reduced power consumption.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (9)
1, a kind of data handling system is characterized in that, this system comprises:
Memory storage, the storage unit index value that is used for sending according to address decoding device is preserved data, and wherein said memory storage is made of storage unit, the corresponding respectively corresponding storage unit index value of each storage unit;
Address decoding device is used to receive data index value, and the data index value of described data is carried out a yard bit inversion computing, obtains described storage unit index value, and sends described storage unit index value to described memory storage;
Data processing equipment, be used for when described data are the data that need read, generate read control signal and send to described memory storage, send data index value to described address decoding device simultaneously, when described data are the data that need write, generate write control signal and send to described memory storage, send data index value to described address decoding device simultaneously.
2, the system as claimed in claim 1 is characterized in that, the data index value of each data that described needs read or write sets in advance.
3, system as claimed in claim 1 or 2 is characterized in that, described address decoding device also is used for:
Before obtaining index value, the number of definite data that need read or write is determined yard bit number of bit inversion needs according to the number of the described data of determining.
4, the system as claimed in claim 1 is characterized in that,
Described data processing equipment also is used for: generate chip selection signal, and send described chip selection signal to described address decoding device;
Described address decoding device also is used for: described chip selection signal is sent to described memory storage;
Described memory storage also is used for: behind described storage unit index value of receiving and described chip selection signal, determine corresponding storage area according to described chip selection signal, the storage unit of storage unit index value correspondence described in the zone of determining is carried out read or write.
5, a kind of method of data processing is characterized in that, this method comprises:
Address decoding device receives the data index value of each data that need read or write, and the data index value is carried out a yard bit inversion computing obtains corresponding storage unit index value;
When described data are the data that need read, read described data in the storage unit of data processing equipment from the memory storage of storage unit index value correspondence, when described data were the data that need write, data processing equipment was with in the storage unit in the memory storage of described data write storage unit index value correspondence;
Wherein said memory storage is made of storage unit, the corresponding respectively corresponding storage unit index value of each storage unit.
6, method as claimed in claim 5 is characterized in that, the data index value of each data that described needs read or write sets in advance.
7, as claim 5 or 6 described methods, it is characterized in that, also comprise before the data index value of each data that described reception need read or write:
Address decoding device determine to read or to write the number of data, determine the bit number of sign indicating number bit inversion needs according to the number of the described data of determining.
8, method as claimed in claim 5 is characterized in that, describedly further comprises read described data from the storage unit of storage unit index value correspondence:
Described data processing equipment generates chip selection signal, and sends described chip selection signal to described address decoding device;
Described address decoding device sends described chip selection signal to described memory storage;
Described memory storage is determined corresponding storage area according to described chip selection signal, and the storage unit of storage unit index value correspondence described in the zone of determining is carried out read operation.
9, method as claimed in claim 5 is characterized in that, described data processing equipment further comprises write described data from the storage unit of storage unit index value correspondence:
Described data processing equipment generates chip selection signal, and sends described chip selection signal to described address decoding device;
Described address decoding device sends described chip selection signal to described memory storage;
Described memory storage is determined corresponding storage area according to described chip selection signal, and the storage unit of storage unit index value correspondence described in the zone of determining is carried out write operation.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102929837A (en) * | 2012-09-18 | 2013-02-13 | 西安电子科技大学 | High-speed fixed point fast fourier transformation (FFT) processor based on field programmable gate array (FPGA) and processing method for high-speed fixed point FFT processor |
| WO2013097235A1 (en) * | 2011-12-31 | 2013-07-04 | 中国科学院自动化研究所 | Parallel bit order reversing device and method |
| CN110008436A (en) * | 2019-03-07 | 2019-07-12 | 中国科学院计算技术研究所 | Fast Fourier Transform (FFT) method, system and storage medium based on data stream architecture |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101330489A (en) * | 2008-07-28 | 2008-12-24 | 中兴通讯股份有限公司 | Processor for FFT / IFFT as well as processing method thereof |
| CN101364215B (en) * | 2008-09-28 | 2010-12-08 | 炬力集成电路设计有限公司 | Data processing apparatus and method for saving memory space |
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| WO2013097235A1 (en) * | 2011-12-31 | 2013-07-04 | 中国科学院自动化研究所 | Parallel bit order reversing device and method |
| US9268744B2 (en) | 2011-12-31 | 2016-02-23 | Institute Of Automation, Chinese Academy Of Sciences | Parallel bit reversal devices and methods |
| CN102929837A (en) * | 2012-09-18 | 2013-02-13 | 西安电子科技大学 | High-speed fixed point fast fourier transformation (FFT) processor based on field programmable gate array (FPGA) and processing method for high-speed fixed point FFT processor |
| CN102929837B (en) * | 2012-09-18 | 2015-06-17 | 西安电子科技大学 | High-speed fixed point fast fourier transformation (FFT) processor based on field programmable gate array (FPGA) and processing method for high-speed fixed point FFT processor |
| CN110008436A (en) * | 2019-03-07 | 2019-07-12 | 中国科学院计算技术研究所 | Fast Fourier Transform (FFT) method, system and storage medium based on data stream architecture |
| CN110008436B (en) * | 2019-03-07 | 2021-03-26 | 中国科学院计算技术研究所 | Fast Fourier transform method, system and storage medium based on data stream architecture |
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