CN101510775B - Digital circuit capable of evolving and evolvement method - Google Patents

Abstract

The invention provides an evolvable digital circuit and an evolution method thereof. The evolvable digital circuit comprises an evolvable combinational circuit, a boundary scanning module used as an interface, and a connecting unit. The output end of the evolvable combinational circuit is connected with the input end of a state register, and the connecting unit is a multiplex selector. One path of the multiplex selector is connected with the boundary scanning module and the other path is connected with the output end of the state register. When the path connected with the boundary scanning module is gated, an excitation vector applied by the boundary scanning module is input into the evolvable combinational circuit. When the path connected with the state register is gated, the output of the state register is fed back to the evolvable combinational circuit. The evolvable digital circuit is provided with a universal test interface to improve the universality of the evolvable digital circuit, and is further compatible with a sequence circuit and a combinational circuit.

Description

The digital circuit of can evolving and evolvement method thereof

Technical field

The present invention relates to a kind of hardware device of evolving, relate in particular to a kind of evolved digital circuit and evolvement method thereof with universal test interface.

Background technology

The research of the hardware technology of can evolving is divided into can the evolve research of hardware research and the inner hardware of can evolving of outside.The research of the outside hardware of can evolving is to utilize the algorithm of software and circuit modeling to simulate the evolutionary process of side circuit, thereby obtains suitable circuit information, and for example the net table is realized the information that finally obtains with hardware circuit.The research of the inner hardware of can evolving is to utilize reconfigurable hardware able to programme as the carrier of circuit rather than modeling in software, thereby can make the real during evolution and environmental interaction influence of circuit, reaches truly practical evolved hardware.Reference paper [1], [2]; In recent years along with the continuing to bring out of various commercial high performance on-site programmable gate arrays (Field Programmable Gate Array) (calling " FPGA " in the following text), be scholar's selection mostly at present by means of the inside of the commercial FPGA platform of the main flow circuit studies method of can evolving.

The inside of the existing platform of the evolving circuit of can evolving is sequential circuit mostly; Any node at circuit all trigger might occur; Also the asynchronous feedback loop possibly occur, these possibilities not only make the circuit evolutionary process slack-off, also possibly make circuit unstable; Increased the difficulty of evaluation circuits fitness, reference paper [2], [3] and [4].

Therefore, need provide a kind of effective circuit framework to avoid above-mentioned these problems.The inner structure of existing commercial FPGA platform is complicated; Usually can not carry out configuration at random, otherwise can cause damage, so generally want to build an initial circuit at chip internal earlier to chip; This circuit is not accomplished the function of expection, but the possibility of accomplishing expectation function is provided.Simultaneously, in the platform that utilizes FPGA as the hardware circuit carrier, usually need the definition interface between digital circuit and the control module of controlling its variation of can evolving, ICAP interface (reference paper [5]) and XHWIF interface (reference paper [6]) are arranged like Xilinx.These interfaces are through the packing of FPGA manufacturer, and the user can only see the DLL that it provides, and receives the restriction on the plurality of applications.Because the concerning security matters character of technology, the control configuration interface of each manufacturer commercial FPGA platform inside is incompatible, and the circuit frame and the algorithm of the circuit of can evolving are not general at each platform.

Therefore, a kind of digital circuit of evolving need be provided, defective such as poor with the versatility that overcomes foregoing circuit, that Application of Interface is dumb.

Reference paper:

[1] Anderson P (1998), the hardware of differentiation (Evolvable Hardware): the artificial differentiation of the hardware circuit in simulation and reality, M.Sc paper, Alhuse, Denmark university.

[2] Hu Linwusi G, Smith S, Te Leier A.; Inherent (Safe intrinsicevolution of Virtex devices), the hardware of differentiation, 2000 of developing of the safety of Virtex equipment.Second NASA/DoD workshop of 13-15 day in July, 2000, the 195-202 page or leaf.

[3] Hu Linwusi G, Smith S, Te Leier A.; The inherence of the virtex equipment through the reconfigurable logic in internet develops (The intrinsic evolution of virtex devices through internet reconfigurablelogic); International conference for the third time is about developing the record of system, in April, 2000.

[4] D.LEVI and S.Guccione, Geneticfpga: the stabilizing circuit that on main flow FPGA equipment, develops (Evolving stable circuits on mainstream fpga devices).In about first NASA/DoD workshop that develops hardware.IEEE ACM, 1999.

[5] B cloth Shandong Ztel; P James-Luo Kesipi, E is triumphant to be reined in, S mcmillan and PSundararajan; " platform model of constructing again automatically " (A Self-reconfiguring Platform); The logic of field programmable and the processing of application, (Springer-Verlag), in September, 2003 the 565-574 page or leaf.

[6] Xilinx company, JBits 2.8SDK are used for Virtex document [M], calendar year 2001.

Summary of the invention

The object of the present invention is to provide a kind of evolved digital circuit and evolvement method thereof, can the evolve versatility of digital circuit of raising, this circuit compatibility sequential circuit and combinational circuit with universal test interface.

The invention provides a kind of digital circuit of evolving, comprising:

Can evolve combinational circuit and as the boundary scan module and the linkage unit of interface; Wherein, The output terminal of said linkage unit is connected with the input end of the combinational circuit of can evolving; Said linkage unit links to each other with said boundary scan module, is input to the said combinational circuit of evolving with the excitation vector that the boundary scan module is applied.

The present invention also provides the evolvement method of the above-mentioned digital circuit of evolving, and this method may further comprise the steps:

Construct the said digital circuit of evolving;

Linkage unit as excitation vector, is input to the input end of the said combinational circuit of evolving with the output of said boundary scan module, and at the next cycle response vector that from said boundary scan module, reads back; Order is imported various possible test vectors, through the relation of input and output, confirms with assessment algorithm whether circuit accomplishes evolution; Do not evolve if accomplish; Through the function of controlling mechanism change circuit, reappraise again, evolve up to thinking that circuit is accomplished.

The present invention provides a kind of digital circuit of evolving again, also comprises status register, wherein,

The output terminal of the said combinational circuit of evolving is connected with the input end of said status register; Said linkage unit is a MUX; A road of said MUX links to each other with said boundary scan module; Another road links to each other with the output terminal of said status register, gating link to each other with said boundary scan module a road time, the excitation vector that the boundary scan module is applied is input to the said combinational circuit of evolving; Gating link to each other with said status register a road time, the output of said status register is fed back in the said combinational circuit of evolving.

The present invention also provides the evolvement method of the above-mentioned digital circuit of evolving, and this method may further comprise the steps:

Construct the said digital circuit of evolving;

Said MUX as excitation vector, is input to the input end of the said combinational circuit of evolving with the output of said boundary scan module, and at the next cycle response vector that from said boundary scan module, reads back; Order is imported various possible test vectors, through the relation of input and output, confirms with assessment algorithm whether circuit accomplishes evolution; Do not evolve if accomplish; Through the function of controlling mechanism change circuit, reappraise again, evolve up to thinking that circuit is accomplished;

The function of MUX is changed, the output of said status register is input in the combinational circuit of can evolving, form feedback.

Wherein, the boundary scan module is made up of the jtag boundary scan chain, and it is formed by connecting each boundary scan cell.The jtag boundary scan chain is a scan chain by the variable-length of FPGA internal programmable resource construction, and compatible IEEE1149.1 standard is used for circuit is tested, and comprises the input of test vector and the retaking of a year or grade of response vector.

Add status register two parts through sequential circuit being decomposed into combinational circuit; Make the part of combinational circuit can use check configuration completely without backfeed loop; Avoided the asynchronous feedback of circuit; Circuit is become can be tested, and promptly can need only the truth table with the corresponding one-tenth of the state table combinational circuit of sequential circuit as testing combinational circuit test sequence circuit.

Jtag boundary scan chain through variable-length is tested circuit; Can on any FPGA, realize the test knot mouth of standard, realize versatility, and because the JTAG scan chain is two parallel shift registers; It is few to take resource, is a kind of test structure efficiently.

Description of drawings

Fig. 1 be can evolve digital circuit circuit structure and with the synoptic diagram that is connected of TAP (Test Access Port) controller;

Fig. 2 is a synoptic diagram of describing the interior details of LUT array.

Embodiment

Below in conjunction with accompanying drawing and embodiment scheme of the present invention is further described.The digital circuit circuit structure of evolving of the present invention mainly is to be used for can the evolve application of hardware of inside, and is as shown in Figure 1.This circuit mainly is divided into three parts, and first is the combinational circuit of can evolving, and is specially LUT (Look Up Table, the look-up table) array that is used to realize various logic functions, and the details of LUT array is as shown in Figure 2, also can be other structure example such as gate array; Second portion is the d type flip flop group as status register; Third part is the boundary scan module as interface; Be specially the jtag boundary scan chain, it is formed by connecting each boundary scan cell, and each unit can be used for applying excitation to circuit; Also can be used for connecting as required from the circuit response of reading back.Wherein the input of first is the output as the MUX of linkage unit, is one 2 output of selecting 1 selector switch in this embodiment.The excitation vector that can select signal source to apply from the output and the jtag boundary scan chain of status register.

Tandem circuit structure of the present invention is constructed in FPGA and can test it through being positioned at the inner TAP controller (being jtag controller) of fpga chip.Because general FPGA supports to utilize JTAG that circuit in the FPGA is reconfigured, comprise all reconfiguring and the part configuration, and generally support self-defining user instruction, can be used for the JTAG chain that access utilizes the FPGA programmable resource to make up.So the circuit structure that utilizes this paper to propose can realize utilizing the evolution experiment of circuit of carrying out evolving of the jtag controller of standard.It is consistent based on the circuit exploitation of FPGA with generally to construct the method for this circuit structure; Can this hardware configuration be described from different levels, for supporting the online FPGA that reconfigures, can be through (the for example online download of JTAG of its means of supporting; Initiatively serial parallel is downloaded; Driven serial parallel is downloaded) hardware is reconfigured, for example use the FPGA of Xilinx company, can utilize its developing instrument.

Whether the process d type flip flop is optional in the output of LUT output array; Because FPGA is a programmable device; Annexation in the SLICE can decide through information different in the bit stream file, and whether the output that some of them fraction bitstream information is used to dispose LUT is transported to the SLICE outside through d type flip flop again.Pass through d type flip flop when the output of LUT and outputed to the SLICE outside again, then formed the sequential circuit structure, otherwise formed the combinational circuit structure.

It is following to utilize circuit among Fig. 1 to carry out the concrete steps that sequential circuit evolves:

(1) circuit structure with Fig. 1 constructs in FPGA.Each node links to each other with the JTAG scan chain in the circuit, and the node of connection comprises input port, output port and other the important nodes that will monitor or control.The function that this moment, circuit was realized not is the function of expection.Progressively obtain the functional circuit of expecting through following flow process.

(2) phase one; MUX is transported to the input port of LUT array among Fig. 1 with the output of JTAG scan chain, as excitation vector, and at the next cycle response vector that from the JTAG scan chain, reads back; Order is imported various possible test vectors; Through the relation of input and output, the fitness of evaluation circuits is promptly with the degree of closeness of target.

(3) pass through assessment algorithm; Obtain the degree of circuit near objective circuit, i.e. fitness, ifs circuit is the same with the objective circuit function; Promptly adapt to fully; Obtain full fitness, otherwise according to assessment algorithm, obtain can evolve the at present fitness value of function and objective function gap of circuit of a mark.The fitness that contrast evolution algorithm institute will reach confirms whether circuit accomplishes evolution, evolves if accomplish, and through the function of JTAG or other controlling mechanisms change circuit, reappraises, up to thinking that circuit accomplished expectation function again.

(4) subordinate phase, the function change with MUX makes it the output of status register and the input of LUT array are coupled together, and forms feedback.

If the circuit of accomplishing is a combinational circuit; As long as when the configuration circuit structure, remove the d type flip flop group among Fig. 1 as status register; And will be that excitation with the JTAG scan chain links to each other with the LUT input and gets final product as the function selecting of the MUX of linkage unit, promptly need only (1) (2) (3) of above-mentioned steps. always

Structure shown in Figure 1 can be assessed circuit effectively; Simultaneously because control circuit is linked to each other with the circuit of can evolving through the JTAG chain; Can evolve only corresponding d type flip flop of each input and output of circuit; The shared resource of interface that can evolve between circuit and the control circuit is minimized, and improve the dirigibility and the versatility of Application of Interface.

It is thus clear that circuit of the present invention can carry out the evolution of digital circuit, and general testing evaluation interface is provided, and it is few to accomplish these the multi-functional additional resources that will use.

Above-mentionedly being merely preferred embodiment of the present invention, is not to be used for limiting protection scope of the present invention.The present invention should be limited accompanying claims.

Claims (4)

1. the digital circuit of can evolving is characterized in that, comprising:

Can evolve combinational circuit, as the boundary scan module and the linkage unit of interface; Wherein, The output terminal of said linkage unit is connected with the input end of the combinational circuit of can evolving; Said linkage unit links to each other with said boundary scan module, is input to the said combinational circuit of evolving with the excitation vector that the boundary scan module is applied; Wherein, the said digital circuit of evolving constructs in FPGA, and the said combinational circuit of evolving is the LUT array that is used to realize various logic functions; The jtag boundary scan chain that said boundary scan module is a variable-length; Said jtag boundary scan chain is formed by connecting each boundary scan cell, and each scanning element is used for applying excitation to circuit, or is used for connecting as required from the circuit response of reading back;

The said digital circuit of evolving also comprises status register, and the output terminal of the combinational circuit of can evolving is connected with the input end of said status register; Said linkage unit is a MUX; A road of this MUX links to each other with said boundary scan module; Another road links to each other with the output terminal of said status register, gating link to each other with said boundary scan module a road time, the excitation vector that the boundary scan module is applied is input to the said combinational circuit of evolving; Gating link to each other with said status register a road time, the output of said status register is fed back in the said combinational circuit of evolving.

2. the digital circuit of evolving as claimed in claim 1 is characterized in that, said status register is the d type flip flop group.

3. evolvement method of digital circuit of can evolving according to claim 1 is characterized in that this method may further comprise the steps:

Construct the said digital circuit of evolving;

Linkage unit as excitation vector, is input to the input end of the said combinational circuit of evolving with the output of said boundary scan module, and at the next cycle response vector that from said boundary scan module, reads back; Order is imported various possible test vectors, through the relation of input and output, confirms with assessment algorithm whether circuit accomplishes evolution; Do not evolve if accomplish; Through the function of controlling mechanism change circuit, reappraise again, evolve up to thinking that circuit is accomplished.

4. evolvement method of digital circuit of can evolving according to claim 1 is characterized in that this method may further comprise the steps:

(1) the said digital circuit circuit structure of evolving is constructed in FPGA, each node links to each other with the JTAG scan chain in the circuit, and the node of connection comprises input port, output port and other the important nodes that will monitor or control;

(2) phase one; MUX is transported to the input port of LUT array with the output of JTAG scan chain, as excitation vector, and at the next cycle response vector that from the JTAG scan chain, reads back; Order is imported various possible test vectors; Through the relation of input and output, the fitness of evaluation circuits is promptly with the degree of closeness of target;

(3) pass through assessment algorithm; Obtain the degree of circuit near objective circuit, i.e. fitness, ifs circuit is the same with the objective circuit function; Promptly adapt to fully; Obtain full fitness, otherwise according to assessment algorithm, obtain can evolve the at present fitness value of function and objective function gap of circuit of a mark; The fitness that contrast evolution algorithm institute will reach confirms whether circuit accomplishes evolution, evolves if accomplish, and through the function of JTAG change circuit, reappraises, up to thinking that circuit accomplished expectation function again;

(4) subordinate phase, the function change with MUX makes it the output of status register and the input of LUT array are coupled together, and forms feedback.

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