CN101510169A - Multiple microprocessor system and monitoring method thereof - Google Patents
Multiple microprocessor system and monitoring method thereof Download PDFInfo
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- CN101510169A CN101510169A CNA2008100809044A CN200810080904A CN101510169A CN 101510169 A CN101510169 A CN 101510169A CN A2008100809044 A CNA2008100809044 A CN A2008100809044A CN 200810080904 A CN200810080904 A CN 200810080904A CN 101510169 A CN101510169 A CN 101510169A
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Abstract
A multi-microprocessor system comprises a first microprocessor and a second microprocessor. The second microprocessor is coupled with the first microprocessor to monitor the first microprocessor; when the first microprocessor is monitored by the second microprocessor, a detection signal is transmitted to the first microprocessor, and the state of the first microprocessor can be judged according to the reflection of the first microprocessor after a preset time.
Description
Technical field
The invention relates to a kind of microprocessor system and method for supervising thereof, and particularly relevant for a kind of multi-micro processor system and method for supervising thereof.
Background technology
Microprocessor (microprocessor) has possessed functions such as computing, logical process and control peripheral circuit.Behind electronic product, make the operation ease of man-computer interface improve microprocessor applications.For instance, the inside of TV, Video Recorder, DVD player promptly disposes microprocessor, with the operation of control total system.
In the evolution of microprocessor, being the 8-bit microprocessor of low order in early days, for example is Intel 8051.Along with scientific and technological evolution, also credit one after the other is right comes out for 16 and 32 s' high-order microprocessor, make the microprocessor applications scope more popular with extensively, toy, household electrical appliances, automobile and consumption electronic products or the like such as all can be spied on a corner of its technology application.
But, under the applied environment of diversification, the technology of microprocessor except need possess usefulness fast, be widely used, microprocessor is still needed to have and is continued and stably work in characteristic under the operating system, can improve the usefulness of system.Therefore, how improving the working stability degree of microprocessor, is one of direction of endeavouring of industry.
Summary of the invention
The present invention by the state of one second microprocessor monitors, one first microprocessor, with the working stability degree of lifting first microprocessor, and promotes system effectiveness about a kind of multi-micro processor system and method for supervising thereof.
The technology aspect one of according to the present invention proposes a kind of multi-micro processor system, comprises a first microprocessor and one second microprocessor.Second microprocessor is coupled to first microprocessor, in order to monitor this first microprocessor.Second microprocessor transmits a detection signal to first microprocessor when monitoring first microprocessor, and after waiting for a schedule time, according to the reaction of first microprocessor, judges the state of first microprocessor.
Another technology aspect according to the present invention proposes a kind of method for supervising of multi-micro processor system.Multi-micro processor system comprises a first microprocessor and one second microprocessor.Second microprocessor system is coupled to first microprocessor.Method for supervising comprises the following steps: to transmit a detection signal to first microprocessor by second microprocessor; And after waiting for a schedule time,, judge the state of first microprocessor by of the reaction of second microprocessor according to first microprocessor.
Description of drawings
Fig. 1 illustrates the calcspar according to the multi-micro processor system of the first embodiment of the present invention.
Fig. 2 illustrates the calcspar according to the multi-micro processor system of the second embodiment of the present invention.
The first component symbol explanation
100,200: multi-micro processor system
102,202: first microprocessor
104,204: the second microprocessors
106,206: storage device
208: the three microprocessors
Embodiment
For foregoing of the present invention can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
The multi-micro processor system of the embodiment of the invention comprises a first microprocessor and one second microprocessor.Second microprocessor is coupled to first microprocessor, in order to monitor this first microprocessor.Second microprocessor transmits a detection signal to first microprocessor when monitoring first microprocessor, and after waiting for a schedule time, according to the reaction of first microprocessor, judges the state of first microprocessor.A plurality of thus embodiment illustrate that multi-micro processor system of the present invention is as follows.
First embodiment
Please refer to Fig. 1, it illustrates the calcspar according to the multi-micro processor system of the present invention's first embodiment.Multi-micro processor system 100 comprises first microprocessor 102, second microprocessor 104 and storage device 106.Second microprocessor 104 is coupled to first microprocessor 102, in order to monitor first microprocessor 102.
Preferably, second microprocessor 104 is the data according to the register 110 of first microprocessor 102, judges that first microprocessor 102 is stopped status or busy condition.For example storing the operational data of first microprocessor 102 in the register 110; this operational data is first microprocessor 102 present work of carrying out or pending work; by analyzing stored operational data in the register 110; can learn first microprocessor 102 present residing states, for example be stopped status, busy condition, normal operating state or other special states.Second microprocessor 104 by the data that read register 110 after, can judge the state that first microprocessor 102 is present according to the data of register 110.
Be stopped status if second microprocessor 104 is judged first microprocessor 104, second microprocessor 104 will judge whether to reset or to restart first microprocessor 102.
Another kind of embodiment is, if after the above-mentioned schedule time, second microprocessor 104 is not received the answer signal R from first microprocessor 102, and then second microprocessor 104 is reset or restarted first microprocessor 104.
If will reset or restart first microprocessor 102, then second microprocessor 104 is copied at least one setting value that is stored in the first microprocessor 102 in the storage device 106 before resetting or restarting first microprocessor 102.Then, reset again or restart first microprocessor 102.Second microprocessor 104 and when resetting or restarting first microprocessor 102 is written into storage device 106 these stored at least one setting values in the first microprocessor 102.
Above-mentioned setting value for example comprises user's setting value.By duplicating this at least one setting value earlier in storage device 106, and this at least one setting value is written into first microprocessor 102 again, can allow first microprocessor 102 after being reset or restarting, storing be reset or restart before identical setting value.So; can make after first microprocessor 102 is reset or resets; total system can revert to first microprocessor 102 shut down before the state that sets of user, and the situation that the user can not perceived shutdown was once arranged takes place, and can successfully continue to use this system.In addition, before this setting value also can comprise that first microprocessor 102 is shut down, the contents value of the parameter of the program that first microprocessor 102 is performed.Again the contents value that is written into parameter also can make first microprocessor 102 revert to apace and shut down preceding duty, continue to finish original uncompleted work.
In addition, if when the state of first microprocessor 102 is busy condition, second microprocessor 104 more carries out the action of a load reduction to first microprocessor 102.For instance, when the utilization rate of first microprocessor 102 surpasses a certain critical value, when the state of first microprocessor 102 is busy condition, second microprocessor 104 can change by second microprocessor 104 by the part work (task) that makes first microprocessor 102 to be carried out, or the part work of cancellation first microprocessor 102, to alleviate the load of first microprocessor 102.
Now with the microprocessor system of present embodiment, be compared as follows with the replacement of traditional microprocessor system or the mode that restarts.In traditional system that only uses a microprocessor; after microprocessor is shut down; the hardware of whole microprocessor is reset by essential elder generation; and then be that the procedure code that microprocessor will be carried out by Bootstrap Loader (boot loader) is written into; to finish the program of resetting or restarting; so, this kind reset or the mode that restarts can cause the loss of user's setting value or original action.
And in present embodiment, suppose that the microprocessor program sign indicating number (micro code) of first microprocessor 102 is stored in storage device 106 or another storage device (not illustrating), for example be to be stored in the flash memory.The procedure code that will carry out when this microprocessor program sign indicating number is first microprocessor 102 normal runnings.When second microprocessor 104 is reset or is restarted first microprocessor 102, utilize direct memory access (DMA) (DirectMemory Access, DMA) mode, the microprocessor program sign indicating number of first microprocessor 102 directly from storage device 106 or another storage device, is loaded in the first microprocessor 102.That is present embodiment system is written into first microprocessor 102 by second microprocessor 104 with the microprocessor program sign indicating number, to finish the program of resetting or restarting.So, can reduce first microprocessor 102 resets or restarts the time that is spent.
Said storage unit 106 for example is flash memory (flash memory) or Erasable Programmable Read Only Memory EPROM (Erasable Programmable Read Only Memory, EPROM), so also be not restricted to this, storage device 106 also can be the storer of other types.Because flash memory and EPROM can be when the power supply stop supplies, it is constant still to keep stored data.Therefore, even power supply suffers to have a mind to or when removing unintentionally, first microprocessor 102 still can be replied the data that before set, to improve the convenience in user's use.
The medium that the first microprocessor 102 and second microprocessor 104 for example are to use the mailbox (mailbox) of register (not illustrating) to transmit as signal.Present embodiment also can be reached signal transmission between the first microprocessor 102 and second microprocessor 104 by interrupting (interrupt) service routine.In addition, first microprocessor 102 for example is the microprocessor of a high-order, in order to carry out an operating system (operatingsy stem); Second microprocessor 104 then for example is the microprocessor of a low order, and right the present invention also is not restricted to this.For instance, first microprocessor 102 for example is 32 a microprocessor, and second microprocessor is 8 8051 single-chips for example then.
The multi-micro processor system of present embodiment can be applicable to use in the electronic installation of plural microprocessor, for example is Digital Television, multimedia player, portable electric device.
In a preferred embodiment, second microprocessor 104 promptly transmits one-time detection signal D to the first microcontroller 102 every the spacer segment time.Hence one can see that, and second microprocessor 104 is constantly first microprocessor 102 to be monitored, and that is to say, detects the state of first microprocessor 102 at any time in second microprocessor system.Therefore; if first microprocessor 102 takes place to shut down or during busy situation; second microprocessor 104 can be learnt immediately; and reset immediately or restart first microprocessor 102; to recover to shut down preceding state; or the load of reduction first microprocessor 102, so can promote the degree of stability and the usefulness of multi-micro processor system 100.
Second embodiment
Please refer to Fig. 2, it illustrates the calcspar according to the multi-micro processor system of the second embodiment of the present invention.Multi-micro processor system 200 comprises first microprocessor 202, second microprocessor 204, the 3rd microprocessor 208 and storage device 206.Second microprocessor 204 is coupled to first microprocessor 202, in order to monitor first microprocessor 202.
Different with first embodiment is, when if second microprocessor 204 is judged first microprocessor 204 for busy condition, second microprocessor 204 will make the part work of first microprocessor 202 change by the 3rd microprocessor 208 and carry out, so that first microprocessor 202 is carried out the action of load reduction.
For example, second microprocessor 204 control first microprocessors 202, make its stop performed more than work in the work to small part.Then, the 3rd microprocessor 208 is carried out the work that first microprocessor 202 stopped to carry out, to alleviate the load of first microprocessor 202 under the control of second microprocessor 204.So,, can not only improve the execution efficient of multi-micro processor system 200, more can improve the degree of stability of system 200 further by alleviating the load of first microprocessor 202.
The disclosed multi-micro processor system of the above embodiment of the present invention monitors first microprocessor constantly by making second microprocessor, detects the first microprocessor state at any time.If when the situation of shutdown takes place first microprocessor, can reset or restart first microprocessor immediately, so can promote the degree of stability of multi-micro processor system.In addition, if first microprocessor is a busy condition, then can alleviate the load of first microprocessor, more can improve the execution efficient of multi-micro processor system effectively.In addition, by the storing and setting value in storage device, can make reset or restart after the state of first microprocessor before recovering to shut down, to improve the convenience in user's use.
In sum, though the present invention discloses as above with embodiment, so it is not in order to limit the present invention.Those skilled in the art, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.
Claims (16)
1. multi-micro processor system comprises:
One first microprocessor; And
One second microprocessor is coupled to this first microprocessor, in order to monitor this first microprocessor;
Wherein, this second microprocessor transmits a detection signal to this first microprocessor when monitoring this first microprocessor, and after waiting for a schedule time, according to the reaction of this first microprocessor, judges the state of this first microprocessor.
2. multi-micro processor system as claimed in claim 1; wherein if after this schedule time; this second microprocessor is not received the answer signal from this first microprocessor, and this second microprocessor is more in order to judge that this first microprocessor is stopped status or busy condition.
3. multi-micro processor system as claimed in claim 2, wherein this second microprocessor judges that according to the data of a register of this first microprocessor this first microprocessor is stopped status or busy condition.
4. multi-micro processor system as claimed in claim 2, wherein when if the state of this first microprocessor is busy condition, this second microprocessor is more in order to carry out the action of a load reduction to this first microprocessor.
5. multi-micro processor system as claimed in claim 2 more comprises:
At least one the 3rd microprocessor is coupled to this second microprocessor;
Wherein, when this first microprocessor was busy condition, this second microprocessor was more with so that the part work of this first microprocessor changes by the 3rd microprocessor carries out.
6. multi-micro processor system as claimed in claim 1, wherein if after this schedule time, this second microprocessor is not received the answer signal from this first microprocessor, this second microprocessor reset or restart this first microprocessor.
7. multi-micro processor system as claimed in claim 6 more comprises:
One storage device is coupled to this second microprocessor;
Wherein, this second microprocessor is before resetting or restarting this first microprocessor, at least one setting value that is stored in this first microprocessor is copied in this storage device, and when resetting or restarting this first microprocessor, at least one setting value of this that this storage device is stored is written in this first microprocessor.
8. multi-micro processor system as claimed in claim 1, wherein if after this schedule time, this second microprocessor is not received the answer signal from this first microprocessor, this second microprocessor transmits once this detection signal again to this first microprocessor.
9. the method for supervising of a multi-micro processor system, this multi-micro processor system comprises a first microprocessor and one second microprocessor, and this second microprocessor system is coupled to this first microprocessor, and this method for supervising comprises:
Transmit a detection signal to this first microprocessor by this second microprocessor; And
After waiting for a schedule time,, judge the state of this first microprocessor by of the reaction of this second microprocessor according to this first microprocessor.
10. method as claimed in claim 9, wherein this method more comprises:
If after this schedule time, this second microprocessor is not received the answer signal from this first microprocessor, is stopped status or busy condition by this this first microprocessor of second microprocessor judges.
11. method as claimed in claim 10, wherein this second microprocessor judges that according to the data of a register of this first microprocessor this first microprocessor is stopped status or busy condition.
12. method as claimed in claim 10, this method more comprises:
If when the state of this first microprocessor is busy condition, this first microprocessor is carried out the action of a load reduction by this second microprocessor.
13. method as claimed in claim 10, wherein this multi-micro processor system comprises that more at least one the 3rd microprocessor is coupled to this second microprocessor, and this method more comprises:
When this first microprocessor is busy condition, by this second microprocessor the part work of this first microprocessor is changed by the 3rd microprocessor and carry out.
14. method as claimed in claim 9, this method more comprises:
If after this schedule time, this second microprocessor is not received the answer signal from this first microprocessor, by this second microprocessor reset or restart this first microprocessor.
15. method as claimed in claim 14, wherein this multi-micro processor system more comprises a storage device, is coupled to this second microprocessor, and this method more comprises:
In this second microprocessor reset or before restarting this first microprocessor, at least one setting value that will be stored in this first microprocessor by this second microprocessor is copied in this storage device, and when resetting or restarting this first microprocessor, at least one setting value of this that this storage device is stored is written in this first microprocessor.
16. method as claimed in claim 9, this method more comprises:
If after this schedule time, this second microprocessor is not received the answer signal from this first microprocessor, and this second microprocessor transmits once this detection signal again to this first microprocessor.
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| CN2008100809044A CN101510169B (en) | 2008-02-15 | 2008-02-15 | Multiple microprocessor system and monitoring method thereof |
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| CN2008100809044A CN101510169B (en) | 2008-02-15 | 2008-02-15 | Multiple microprocessor system and monitoring method thereof |
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| CN101510169A true CN101510169A (en) | 2009-08-19 |
| CN101510169B CN101510169B (en) | 2012-05-09 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103970628A (en) * | 2013-02-01 | 2014-08-06 | 技嘉科技股份有限公司 | Automatic detection system and automatic detection method thereof |
| CN108897248A (en) * | 2018-06-07 | 2018-11-27 | 浙江国自机器人技术有限公司 | A kind of self―tuning control and mobile robot |
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2008
- 2008-02-15 CN CN2008100809044A patent/CN101510169B/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103970628A (en) * | 2013-02-01 | 2014-08-06 | 技嘉科技股份有限公司 | Automatic detection system and automatic detection method thereof |
| CN103970628B (en) * | 2013-02-01 | 2017-09-19 | 技嘉科技股份有限公司 | Automatic detection system and automatic detection method thereof |
| CN108897248A (en) * | 2018-06-07 | 2018-11-27 | 浙江国自机器人技术有限公司 | A kind of self―tuning control and mobile robot |
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| CN101510169B (en) | 2012-05-09 |
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Effective date of registration: 20191224 Address after: No.1, Duhang 1st Road, Hsinchu City, Hsinchu Science Park, Taiwan, China Patentee after: MediaTek.Inc Address before: Hsinchu County, Taiwan, China Patentee before: MStar Semiconductor Co., Ltd. |