CN101509943A - Phase detecting method and apparatus - Google Patents
Phase detecting method and apparatus Download PDFInfo
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- CN101509943A CN101509943A CNA2008102410325A CN200810241032A CN101509943A CN 101509943 A CN101509943 A CN 101509943A CN A2008102410325 A CNA2008102410325 A CN A2008102410325A CN 200810241032 A CN200810241032 A CN 200810241032A CN 101509943 A CN101509943 A CN 101509943A
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Abstract
The invention discloses a phase detection method and device, aiming at solving the problem that the existing digital CDR circuit is comparatively complex during realization. The device comprises: a D trigger used for adopting a first pulse signal to obtain a first counting enabling signal, a logic circuit which obtains a reset signal according to a second pulse signal and the first counting enabling signal, a counting module which latches and outputs a first quantized value and a second quantized value according to effective reset signals, and a comparator which determines the phase relationship between the first pulse signal and the second pulse signal according to the latched output of the second quantized value and the latched output of the first quantized value; as phase detection is realized by the D trigger, the logic circuit, the counting module and the comparator, the circuit is simpler during realization.
Description
Technical field
The invention belongs to the digital circuit field, particularly a kind of phase detection method and device.
Background technology
The synchronous serial interface transmission is a kind of serial communication mode commonly used, for the one-way data transmission, need provide data, bit clock, frame-synchronizing impulse three road signals usually simultaneously.If directly utilize synchronous serial interface to realize that plate progression is reportedly defeated on printed circuit board, so this three-way connected mode is not only wasted lead, and often be subjected to the influence of environment be difficult to realize between three road signals synchronously.Utilize all-digital phase-locked loop to recover its bit synchronization clock (being CDR, Clock and Data Recover) from serial bit stream extracting data ice.There has been the bit synchronization clock just can extract serial data stream at an easy rate.Like this, in printed board, only need a data lines just can receive, simplified the external interface relation from the synchronous serial data outside the plate.Same this technology can be amplified other application, has only as optical-fibre communications, radio communication etc. in the serial communication mode of data-signal transmission.
Phase detecting circuit is one of Key Circuit of decision ce circuit performance, and phase detecting circuit major applications the earliest is in the ce circuit of simulation, and is complicated when the existing digital ce circuit is realized.
Summary of the invention
Than complicated problems, the embodiment of the invention provides a kind of phase detection method, comprising when realizing in order to solve the existing digital ce circuit:
The effective edge that uses first pulse signal obtains first count enable signal along the working direct current level is latched;
Obtain reset signal according to second pulse signal and first count enable signal, reset signal is effective when second pulse signal is significant level, and the cycle of described first pulse signal is the integral multiple in the cycle of second pulse signal;
By the win count enable signal level upset of effective reset enable signal, and the effective edge of reusing first pulse signal is along the working direct current level is latched;
Use a signal period to become the high-frequency clock of multiple relation with second pulse signal cycle, the effective pulse signal of level is counted, obtain first quantized value, this pulse signal effective edge along be synchronized with first pulse signal and reset signal when effective level effective, effective another pulse signal of level is counted, obtain second quantized value, this pulse signal effective edge is along being synchronized with second pulse signal, significant level continue duration less than the second pulse signal cycle time and reset signal when effective level effective;
According to effective reset signal first quantized value is latched output, second quantized value is latched output according to effective reset signal;
First pulse signal and the second pulse signal phase relation are determined in the output of latching of latching the output and first quantized value according to second quantized value.
The embodiment of the invention also provides a kind of device of phase-detection simultaneously, comprising:
D type flip flop: be used to use the effective edge of first pulse signal along the working direct current level is latched, obtain first count enable signal, by the win count enable signal level upset of effective reset enable signal, and the effective edge of reusing first pulse signal is along the working direct current level is latched;
Logical circuit: be used for obtaining reset signal according to second pulse signal and first count enable signal, reset signal is effective when second pulse signal is significant level, and the cycle of described first pulse signal is the integral multiple in the cycle of second pulse signal;
Counting module: be used to use a signal period to become the high-frequency clock of multiple relation with second pulse signal cycle, the effective pulse signal of level is counted, obtain first quantized value, this pulse signal effective edge along be synchronized with first pulse signal and reset signal when effective level effective, effective another pulse signal of level is counted, obtain second quantized value, this pulse signal effective edge is along being synchronized with second pulse signal, significant level continue duration less than the second pulse signal cycle time and reset signal when effective level effective, according to effective reset signal first quantized value is latched output, second quantized value is latched output according to effective reset signal;
Comparer: be used for determining first pulse signal and the second pulse signal phase relation according to the output of latching of latching the output and first quantized value of second quantized value.
The specific embodiments that is provided by the invention described above as can be seen, just because of passing through d type flip flop, logical circuit, counting module and comparer, reset signal latchs first quantized value, second quantized value, first pulse signal and the second pulse signal phase relation are determined in the output of latching of latching the output and first quantized value according to second quantized value, make circuit simpler when realizing.
Description of drawings
Fig. 1 is the phase detecting circuit of embodiment 1 provided by the invention;
Fig. 2 is the phase detecting circuit of embodiment 2 provided by the invention;
Fig. 3 is the phase detecting circuit of embodiment 3 provided by the invention;
Fig. 4 is the phase detecting circuit of embodiment 4 provided by the invention;
Fig. 5 is the phase detecting circuit of embodiment 5 provided by the invention;
Fig. 6 is a phase detecting circuit phase advance circuit signal graph provided by the invention;
Fig. 7 is a phase detecting circuit phase lag network signal graph provided by the invention;
Fig. 8 is the ce circuit figure of embodiment 6 provided by the invention;
Fig. 9 is embodiment 7 method flow diagrams provided by the invention;
Figure 10 is the phase detection device structural drawing of embodiment 8 provided by the invention.
Embodiment
Than complicated problems, the phase-comparison circuit that the embodiment of the invention provides detects phase place at the rising edge of data-signal (or adopt negative edge as the effective edge edge, only prolong with rising below describe) when realizing in order to solve the existing digital ce circuit.Use the rising edge and the rising edge of clock signal of input data that high level VCC (or low level GND) is latched; Data after clock signal latchs are carried out with clock signal itself and are obtained the effective count enable signal of high level (or other logics obtain the effective count enable signal of low level); After latching, data-signal obtains the effective count enable signal of another high level (also can be that low level is effective according to the different logic of circuit); By these 2 count enable signal with or other logical relations obtain the reset signal of d type flip flops, or put 1 signal.Here the phase place of mentioning is meant the low level of the effective edge of data-signal along corresponding clock signal in advance, and phase lag is meant the high level of the effective edge of data-signal along corresponding clock signal; Can certainly put upside down mutually, promptly the leading notion of the phase place here can be the content of phase lag indication, and this moment, phase lag then was the content of the leading indication of phase place so.
And then use one become with clock signal multiple concern high-frequency clock (being preferably in more than 16 times), these 2 count enable signal are counted when effective (these two signals can simultaneously effectively), so that acquisition quantized value, and when the reset signal (or putting 1 signal) of d type flip flop is effective, the quantized value that obtains is latched output.And then judge phase relation according to the size of 2 quantized values, when the quantized value that obtains by data-signal latch output valve greater than zero the time, the output of latching of another quantized value then is zero so; Otherwise when another quantized value latch output valve greater than zero the time, the latching of quantized value that obtains by data-signal is output as zero so; This is decided by circuit structure.Like this, when judging phase relation, just can judge, when the quantized value that obtains by data-signal to latch output valve phase place greater than zero time leading, and the numerical value of this counter is exported; When the output valve that latchs of another quantized value is judged phase lag greater than zero the time, and with the numerical value output of this counter.If the output of latching of 2 quantized values is zero phase-locking.
In digital oscillator, the phase relation of input and the quantized value of phase differential are produced rational clock signal, as under the leading situation of phase place, directly add the phase quantization difference on the divide ratio to high-frequency clock, realize synchronously thereby make the rising edge of clock signal of exporting (or negative edge) align with the edge of data-signal.The ce circuit of Shi Xianing can just can be realized the synchronous of clock and data-signal behind first active data signal edge of input by this way.
In the digital circuit field, usually the minimum period of data-signal 2 times of cycle of clock signal normally, the data-signal cycle in the embodiment of the invention is all adopted 2 times of clock signal period, adopt the data-signal clock signal just as a preferred example that carries out phase-detection between the different pulse signals, 2 pulse signals that carry out phase-detection can also be the clock signal of a standard and clock signal to be detected, and the cycle of these 2 clock signals is identical.
The phase detecting circuit of the embodiment of the invention 1, as shown in Figure 1.This phase detecting circuit comprises: two with door A1, an A2, two not gates, d type flip flop D1, the D2 of 2 band clear terminals, two bands enable counter Cnt1, the Cnt2 with zero clearing, two multichannel latchs (register) L1, L2 and the comparer through changing.
In this phase detecting circuit, the FPDP of trigger D1 and D2 is connected on external high level Vcc (high level the is a significant level in the present embodiment) output port, external data-signal Data_in output port is connected on the clock input terminal of trigger D1, and the Q output terminal of trigger D1 output count enable signal Data_cnt_en is connected on first input end with door A1; The clock signal clk of 2 external frequencys multiplication (clock signal clk also can be 4 times of data-signal Data_in frequency and wait integral multiples) output port is connected on second input terminal with door A1; Be connected on the zero clearing terminal of trigger D1 with the output terminal output signal clear of door A1, also be connected on the clock input terminal of multichannel latch L1 and L2 simultaneously.The counting that the output terminal output signal Data_cnt_en of trigger D1 is connected to counter Cnt1 enables on the terminal, and the output terminal of trigger D1 is connected on the Reset signal terminal that resets of counter Cnt1 through a not gate (make signal Data_cnt_en reverse); The counter that the clock signal clk output port of 2 external frequencys multiplication is connected to counter Cnt2 enables on the terminal, and is connected on the Reset signal terminal of counter Cnt2 through a not gate (make clock signal clk reverse); The output terminal output F_data signal of counter Cnt1 is connected to latch L1 and gets on the input port; The output terminal output L_data signal of counter Cnt2 is connected on the input port of latch L2; The output Frond_data of latch L1 and the output Lag_data of latch L2 are connected respectively on two input ports of comparer, comparer meeting output phase status signal Status[1:0] and phase differential quantification value Data[7:0].Phase state signal Status[1:0 wherein] show 3 kinds of different states of phase state signal with 2 binary numerical tables: leading, lag behind and synchronously.Phase differential quantification value Data[7:0] show 256 different phase differential quantification values with 8 binary numerical tables.
In the present embodiment the low level of the corresponding clock signal of the rising edge of data-signal (effective edge along) being called " phase place is leading " is that data-signal is ahead of clock signal, it is that data-signal lags behind clock signal that the high level of the corresponding clock signal of the rising edge of data-signal is called " phase lag ", and the corresponding rising edge of clock signal of rising edge of data-signal is called " phase-locking ".
The phase detecting circuit of the embodiment of the invention 2, as shown in Figure 2.In the present embodiment, be with the difference of embodiment 1, the counting that no longer output terminal of trigger D1 is connected to counter Cnt1 enables on the terminal, and no longer is connected to the output terminal of trigger D1 on the Reset signal terminal that resets of counter Cnt1 through a not gate; But the counting that external data-signal Data_in output port is connected to counter Cnt1 is enabled on the terminal, data-signal Data_in output port is connected on the Reset signal terminal that resets of counter Cnt1 through a not gate.No matter be that the counting that in the present embodiment external data-signal Data_in output port is connected to counter Cnt1 enables on the terminal, the counting that among the embodiment 1 the output terminal output signal Data_cnt_en of trigger D1 is connected to counter Cnt1 enables on the terminal, still data-signal Data_in is by the pulse signal of other logical circuit generation, the counting that is connected to counter Cnt1 enables terminal, the effective edge that enter counter Cnt1 counting enables the pulse signal of terminal is synchronized with data-signal Data_in along need, and it is effective to count the pulse signal level that enables the terminal input when reset signal is effective.
The phase detecting circuit of the embodiment of the invention 3, as shown in Figure 3.Be with the phase detecting circuit difference among Fig. 1, phase detecting circuit among Fig. 3 is except comprising: 1 and a door A1, two not gates, the d type flip flop D1 of 1 band clear terminal, two bands enable counter Cnt1, the Cnt2 with zero clearing, outside two multichannel latchs (register) L1, L2 and the comparer through changing.Also comprise: 1 and a door A2, the d type flip flop D2 of 1 band clear terminal.The FPDP of trigger D2 is connected on external high level Vcc (high level the is a significant level in the present embodiment) output port, and the clock signal clk output port of 2 external frequencys multiplication is connected on the clock input terminal of trigger D2; The Q output terminal of trigger D2 output Clk_q signal is connected on first input end with door A2, and the clock signal clk input port of 2 external frequencys multiplication is connected on second input terminal with door A2; Be connected on second input terminal with door A1 with the output terminal of door A2 output Clk_cnt_en signal, and the counting that the clock signal clk input port of 2 external frequencys multiplication is not connected to the second input terminal sum counter Cnt2 of door A1 enables on the terminal.The counter that is connected to counter Cnt2 with the output terminal of door A2 enables on the terminal, and is connected on the Reset signal terminal of counter Cnt2 through a not gate with the output terminal of door A2.No matter be that the counting that in the present embodiment the external output terminal with door A2 is connected to counter Cnt2 enables on the terminal, the counting that among the embodiment 1 clock signal clk output port is connected to counter Cnt2 enables on the terminal, still pass through the pulse signal that other logical circuit generates, the counting that is connected to counter Cnt2 enables terminal, the effective edge of the pulse signal of input is synchronized with clock signal clk along need, the significant level duration less than clock signal clk time monocycle (if pulse signal significant level duration of this input greater than clock signal clk time monocycle as adopting the Clk_q signal, then the effective edge of clear reset signal is along being synchronized with data-signal Data_in, make effectively to count and latch), and it is effective to count the pulse signal level that enables the terminal input when reset signal is effective.
The invention provides the phase detecting circuit of embodiment 4, as shown in Figure 4, Fig. 4 is that the phase detecting circuit to Fig. 3 carries out simple conversion, the difference of Fig. 4 FPDP of trigger D1 and D2 in the present embodiment is connected to external low level GND, and the Q output terminal output count enable signal Data_cnt_en of trigger D1 is connected on first input end with door A1 by a not gate; The Q output terminal of trigger D2 output Clk_q signal is connected on first input end with door A2 by a not gate, be connected on the SET terminal (put 1 terminal, signal Data_cnt_en was put 1 when promptly output signal clear level was effective) of trigger D1 and trigger D2 with the output terminal output signal clear of door A1.
The invention provides the phase detecting circuit of embodiment 5, as shown in Figure 5, Fig. 5 is that the phase detecting circuit to Fig. 3 carries out simple conversion, the difference of Fig. 5 FPDP of trigger D1 and D2 in the present embodiment is connected to external low level GND, and the output terminal output signal clear of rejection gate A3 is connected on the SET terminal of trigger D1.The Q output terminal of trigger D1 is connected on first input end of rejection gate A3, the Q output terminal of trigger D2 be connected to or the door A4 first input end on, the clock signal clk input port of 2 external frequencys multiplication through a not gate be connected to or the door A4 second input terminal on; Or the output terminal of door A4 is connected on second input terminal of rejection gate A3, the output terminal of trigger D1 enables on the terminal through the counting that a not gate is connected to counter Cnt1, and the output terminal of trigger D1 is connected on the Reset signal terminal that resets of counter Cnt1; Or the door A4 output terminal enable on the terminal through the counting that a not gate is connected to counter Cnt2, and or the door A4 output terminal be connected on the Reset signal terminal that resets of counter Cnt2.
The action of phase detecting circuit when phase place is leading of embodiment 3 is described referring to Fig. 6.When the phase relation of data-signal Data_in and clock signal clk concerning as shown in Figure 6, the rising that is data-signal Data_in is prolonged (effective edge edge) and is prolonged prior to the rising of clock signal clk, using the rising of data-signal Data_in and clock signal clk to prolong latchs high level Vcc, the count enable signal Data_cnt_en of high level can appear earlier in trigger D1 output terminal, make counter Cnt1 upwards count to get F_data under the triggering of high-speed clock signal hight_clk, the output of F_data numerical value is greater than zero; This moment is because clk_cnt_en is a low level is high level after oppositely, so Cnt2 is a cleared condition, with the output clear of door A1 also be low level.When the rising edge of clk arrives, make the output Clk_q of trigger D2 high level occur, the clk of this moment is high simultaneously, so be output as height with the output clk_cnt_en of door A2, and this moment, Data_cnt_en was high, so when high level occurring on the clk_cnt_en, can make immediately with the door A1 output clear high level appears immediately, thereby trigger D1, D2 are carried out clear operation simultaneously, make that Data_cnt_en and Clk_q are low level, again two counter Cnt1 and Cnt2 are carried out clear operation respectively; Because the high level that occurs above of clk_cnt_en is very of short duration in this case, makes counter Cnt2 not carry out counting operation, the output signal Lag_data of counter Cnt2 is zero.And the high level of of short duration clear latchs the count value of counter Cnt1 and Cnt2 output, make the output of latch L1 and L2 obtain the count value of counter Cnt1 and Cnt2 respectively, because counter Cnt1 has carried out upwards counting operation, and counter Cnt2 does not carry out counting operation, so this moment, the output Front_data of latch L1 had greater than zero numerical value output, and the value of the output Lag_data of latch L2 still is zero.When the value of Front_data and Lag_data is input in the comparer, comparer can compare them, because Lag_data this moment is zero, and have on the Front_data greater than zero numerical value, so can judge whether (parameter of She Zhiing is 2 more than or equal to some numerical value for numerical value on the Front_data this moment here, this numerical value is relevant with synchronous precision, those skilled in the art can be provided with voluntarily according to the operating circuit demand of reality), if greater than this value, can make the value of Status be output as 01 and represent that phase place is leading, the numerical value of Front_data can be composed the unit of exporting to the back to Data simultaneously; If the value of Front_data is worth less than this, can make the value of Status be output as 11 and represent phase-locking, make that the Data output valve is zero.
According to above-mentioned steps as can be known, when the output signal L_data of counter Cnt2 is zero, the output signal F_data of counter Cnt1 is greater than zero the time, show that phase place is leading, it is in order further to determine phase place quantized value accurately in advance that the follow-up output signal to counter Cnt1, counter Cnt2 latchs.
As shown in Figure 6, when the data-signal data_in of input through first high level data when changing low level into, when having rising edge to arrive on the clk signal, can make Clk_q go up and obtain high level, this moment, clk was a high level, output Clk_cnt_en with door A2 can export high level like this, and makes the counter Cnt2 counting operation that makes progress under the triggering of high-speed clock signal Hight_clk again.Subsequently when appearance is low level on the clk signal, though Clk_q keeps high level, but can make with the door A2 output Clk_cnt_en be low level, thereby counter Cnt2 is carried out clear operation, the Clear signal remains low level in this process, so latch L2 can not carry out latch operation to the count value of counter Cnt2.Will make that like this counter Cnt2 has carried out invalid counting operation.
As shown in Figure 6, on the Data_in data-signal, occur to make that equally the output Data_cnt_en of trigger D1 is drawn high in second rising edge, make counter Cnt1 under the triggering of high-frequency clock Hight_clk, carry out technical operation.And the output Clk_q of trigger D2 is a high level at this moment, be output as low level with the output terminal Clk_cnt_en of door A2, like this when the rising edge of clock arrives, can be drawn high by feasible output terminal Clk_cnt_en with door A2, thereby feasible lead-out terminal Clear with door A1 is drawn high, thereby trigger D1, D2 are carried out clear operation simultaneously, make that the lead-out terminal of trigger D1 and D2 is dragged down simultaneously, counter Cnt1 and Cnt2 have carried out a clear operation again like this; The Clear that is drawn high can once latch the output data of counter Cnt1 and Cnt2 equally, makes latch L1 and L2 obtain the count value of counter Cnt1 and Cnt2 respectively; Comparer compares the data that regain come again Status and Data is carried out output function like this.
The action of phase detecting circuit when phase lag of embodiment 3 is described referring to Fig. 7.When the phase relation of data-signal Data_in and clock signal clk concerning as shown in Figure 7, the output Clk_cnt_en of trigger D2 can occur high level earlier, makes the counter Cnt2 counting that makes progress under the triggering of high-frequency clock Hight_clk; This moment is because Data_cnt_en is a low level, so Cnt1 is a cleared condition, with the output clear of door A1 also be low level.When the rising edge of Data_in arrives, make the output Data_cnt_en of trigger D1 high level occur, and this moment, Clk_cnt_en was high, so can make immediately with the door A1 output clear high level appears immediately, thereby trigger D1, D2 are carried out clear operation simultaneously, make that Data_cnt_en and Clk_q are low level, again two counter Cnt1 and Cnt2 are carried out clear operation respectively; Because the high level that occurs above of Data_cnt_en is very of short duration in this case, makes counter Cnt1 not carry out counting operation.And the high level of of short duration clear latchs the count value of counter Cnt1 and Cnt2 output, make the output of latch L1 and L2 obtain the count value of counter Cnt1 and Cnt2 respectively, because counter Cnt2 has carried out upwards counting operation, and counter Cnt1 does not carry out counting operation, so this moment, the output Front_data of latch L1 still was zero,, and the output Lag_data of latch L2 has the numerical value output greater than zero.When the value of Front_data and Lag_data is input in the comparer, comparer can compare them, because Front_data this moment is zero, and have on the Lag_data greater than zero numerical value, so can judge whether (parameter of She Zhiing is 2 more than or equal to some numerical value for numerical value on the Lag_data this moment here, this numerical value is relevant with synchronous precision), if greater than this value, can make the value of Status be output as 10 and represent phase lag, the numerical value of Lag_data can be composed the unit of exporting to the back to Data simultaneously; If the value of Lag_data is worth less than this, can make the value of Status be output as 11 and represent phase-locking, make that the Data output valve is zero.
According to above-mentioned steps as can be known, when the output signal L_data of counter Cnt2 greater than zero, when the output signal F_data of counter Cnt1 is zero, after showing phase position, it is in order further to determine behind the phase position quantized value accurately that the follow-up output signal to counter Cnt1, counter Cnt2 latchs.
As shown in Figure 7, when second rising edge of clk arrives, can make that the lead-out terminal clk_q of trigger D2 is drawn high, because clk is a high level, can make and be drawn high, and make the counter Cnt2 counting operation that under the triggering of high-frequency clock Hight_clk, makes progress with the signal of the output Clk_cnt_en of door A2.Subsequently when appearance is low level on the clk signal, though Clk_q keeps high level, but can make with the door A2 output Clk_cnt_en be low level, thereby counter Cnt2 is carried out clear operation, the Clear signal remains low level in this process, so latch L2 can not carry out latch operation to the count value of counter Cnt2.Will make that like this counter Cnt2 has carried out invalid counting operation.As shown in Figure 3, when the 4th, 5,7,8 rising edge of clock signal clk arrives, all can make counter Cnt2 under the triggering of high-speed clock signal Hight_clk, carry out invalid counting operation.
As shown in Figure 7, when the 3rd rising edge of clk arrives, the output of the output Clk_q of trigger D2 still remains high level, can make this moment and be drawn high with the level of output Clk_cnt_en of door A2, thereby make counter Cnt2 under the triggering of high-speed clock signal Hight_clk, carry out counting operation, this moment, Data_cnt_en was a low level, and Cnt1 is counted; When second rising edge of data-signal Data_in arrives, can make that the output Data_cnt_en of trigger D1 is drawn high, feasible output Clear with door A1 obtains a high level, this level carries out clear operation simultaneously to trigger D1 and D2, thereby make that the output of trigger D1 and D2 is dragged down, the value of output Clear with door A1 is dragged down; The value of counter Cnt1 and Cnt2 should be latched simultaneously, comparer compares the data that regain come again Status and Data is carried out output function like this.As shown in Figure 7, when the 6th rising edge of clock signal clk and the 9th rising edge arrive, just when rising edge appears in the output terminal Clear with door A1, all can make comparer regain phase data and carry out corresponding action.
Action when the phase detecting circuit lead-lag of embodiment 3 being described by Fig. 6 and Fig. 7, the action of action during the phase detecting circuit lead-lag of embodiment 4,5 during with the phase detecting circuit lead-lag of embodiment 3 is slightly different, difference is, because the external low level GND of FPDP of trigger D1 and D2, when therefore the rising edge of data-signal Data_in and clock signal clk arrives, can make that the output Data_cnt_en of trigger D1 and the output Clk_q of trigger D2 are dragged down.The action of action during the phase detecting circuit lead-lag of embodiment 2 during with the phase detecting circuit lead-lag of embodiment 3 is slightly different, difference is, among the embodiment 2, be that data-signal Data_in is counted when phase place is leading, be that clock signal clk is counted in the time of behind the phase position, though the quantized value that counts to get like this can be greater than quantized value leading by reality or that lagging phase obtains, but since the follow-up Shi Buhui of latching to reality the counting after the leading or lagging phase store, make that actual leading or lagging phase counting afterwards is invalid counting.
Fig. 8 shows embodiments of the invention 6CDR (Clock and Data Recover) circuit.Ce circuit is by digital filter, digit phase testing circuit DPD, and a digital oscillator DCO and a d type flip flop constitute.As shown in Figure 8 be digit phase testing circuit DPD, its effect is the phase differential that detects data and clock signal, and the quantized value of phase difference output.The effect of digital filter is the invalid signals of eliminating on the digital signal; The effect of digital oscillator DCO is to be used for producing and the data-signal clock signal synchronous.The principle of work of digital oscillator DCO is that Hight_clk counts frequency division to high-speed clock signal, when obtaining rising edge on the Load signal, to phase state signal Status[1:0] and data-signal Data[7:0] load; If phase place leading (Status[1:0] be 01), then when frequency division, the divide ratio value is added quantification difference Data[7:0], like this will be when next clock signal be exported, make rising edge of clock signal align with the effective edge edge of data-signal, frequency division afterwards then is normal frequency division action, makes data-signal and clock signal keep phase locked state.If phase lag, be status signal Status[1:0] be 10, then when frequency division, the divide ratio value is deducted quantification difference Data[7:0], like this will be when next clock signal be exported, make rising edge of clock signal align with the effective edge edge of data-signal, frequency division afterwards then is normal frequency division action, makes data-signal and clock signal keep phase locked state.If detect phase state is synchronous regime, i.e. status signal Status[1:0] be 11, the frequency division action remains normal frequency division action.Like this, ce circuit will make phase place enter synchronous state after an effective rising edge arrives.
The invention provides embodiment 7 is a kind of method for detecting phases, and as shown in Figure 9, the phase detecting circuit with Fig. 3 is that the basis describes below, and the cycle of data-signal Data_in is 2 times of cycle of clock signal clk.
Step 102: use the rising edge of data-signal Data_in that high level Vcc is latched, obtain the Data_cnt_en signal.
Step 104: use the rising edge of clock signal clk that high level Vcc is latched, obtain the Clk_q signal, Clk_q signal and clock signal clk carry out obtaining the Clk_cnt_en signal with logical operation.
Step 106: carry out obtaining the Clear signal with logical operation according to Clk_cnt_en signal and Data_cnt_en signal.
Step 108: make the Data_cnt_en signal level become low level by effective Clear signal, and the rising edge of reusing data-signal Data_in latchs to high level Vcc by high level.
Step 110: use a high-frequency clock, the Data_cnt_en signal is counted, obtain quantized value F_data.The Clk_cnt_en signal is counted, obtained quantized value L_data.
Step 112: according to effective Clear signal quantized value F_data is latched output, quantized value L_data is latched output, determine that phase place is leading, hysteresis or synchronous according to effective Clear signal.
Step 114: high-frequency clock is counted frequency division, when Clear signal effective edge when arriving, if phase place is leading, then add quantized value F_data on the counting divide ratio to high-frequency clock, if phase lag then deducts quantized value L_data on the counting divide ratio to high-frequency clock.
The Data_cnt_en signal that wherein obtains in the step 102 is a high level, if based on Fig. 4,5 phase detecting circuit, then use the rising edge of data-signal Data_in that low level GND is latched, obtain the Data_cnt_en signal, the Data_cnt_en signal that obtain this moment is a low level.
Wherein in the step 106, the phase detecting circuit as if based on Fig. 1 then directly carries out obtaining the Clear signal with logical operation according to clock signal clk and Data_cnt_en signal, and need not step 104.If based on Fig. 4,5 phase detecting circuit, clock signal clk and Data_cnt_en signal also can obtain the Clear signal by other logical operation, only need Clear signal when clock signal clk is significant level (high level) effectively get final product.
Wherein in the step 108, if based on Fig. 4,5 phase detecting circuit, the Data_cnt_en signal was put 1 when then output signal clear level was effective, and the Data_cnt_en signal level becomes high level by low level.
Wherein in the step 110, the clock signal clk cycle is 16 times of high-speed clock signal cycle, can determine that according to quantized value F_data and quantized value L_data phase place is leading, hysteresis or synchronous, if quantized value L_data is zero, quantized value F_data is greater than zero, then data-signal Data_in phase place is ahead of clock signal clk, if quantized value F_data is zero, quantized value L_data is greater than zero, then data-signal Data_in phase place lags behind clock signal clk, if quantized value L_data and quantized value F_data are zero, then data-signal Data_in and clock signal clk are synchronous.
Wherein in the step 112, if latching, quantized value L_data is output as zero, quantized value F_data latchs output greater than zero, then data-signal Data_in phase place is ahead of clock signal clk, be output as zero if quantized value F_data latchs, quantized value L_data latchs output greater than zero, and then data-signal Data_in phase place lags behind clock signal clk, if quantized value L_data latchs output and quantized value F_data and latchs output and be zero, then data-signal Data_in and clock signal clk are synchronous.
The invention provides embodiment 8 is a kind of phase detection devices, as shown in figure 10, comprising:
D type flip flop 201: be used to use the effective edge of first pulse signal along the working direct current level is latched, obtain first count enable signal, by the win count enable signal level upset of effective reset enable signal, and the effective edge of reusing first pulse signal is along the working direct current level is latched;
Logical circuit 202: be used for obtaining reset signal according to second pulse signal and first count enable signal, reset signal is effective when second pulse signal is significant level, and the cycle of described first pulse signal is the integral multiple in the cycle of second pulse signal;
Counting module 203: be used to use a signal period to become the high-frequency clock of multiple relation with second pulse signal cycle, the effective pulse signal of level is counted, obtain first quantized value, this pulse signal effective edge along be synchronized with first pulse signal and reset signal when effective level effective, effective another pulse signal of level is counted, obtain second quantized value, this pulse signal effective edge is along being synchronized with second pulse signal, significant level continue duration less than the second pulse signal cycle time and reset signal when effective level effective, according to effective reset signal first quantized value is latched output, second quantized value is latched output according to effective reset signal;
Comparer 204: be used for determining first pulse signal and the second pulse signal phase relation according to the output of latching of latching the output and first quantized value of second quantized value.
Further, comparer 204: also be used for being output as zero if second quantized value latchs, first quantized value latchs output greater than zero, then the first pulse signal phase place is ahead of second pulse signal, be output as zero if first quantized value latchs, second quantized value latchs output greater than zero, and then the first pulse signal phase place lags behind second pulse signal, if first quantized value latchs output and second quantized value and latchs output and be zero, then first pulse signal and second pulse signal are synchronous.
Further, comparer 204: also be used for being output as zero if first quantized value latchs, second quantized value latchs output greater than presetting threshold value, then data signal phase is ahead of clock signal, if latching, second quantized value is output as zero, first quantized value latchs output greater than presetting threshold value, and then data signal phase lags behind clock signal.
Further, comparer 204 also is used for high-frequency clock is counted frequency division, when the reset signal effective edge when arriving, if phase place is leading, add on the counting divide ratio to high-frequency clock that then first quantized value latchs the value of output, if phase lag then deducts the value that second quantized value latchs output on the counting divide ratio to high-frequency clock.
Further, logical circuit 202: also be used to use the effective edge of second pulse signal along the working direct current level is latched, the signal and second pulse signal after latching according to second pulse signal obtain second count enable signal, when second pulse signal was significant level, second count enable signal was effective;
Counting module 203: also be used for effective second count enable signal of level is counted, obtain second quantized value.
With Fig. 1 is example, d type flip flop 201 comprises the trigger D1 among Fig. 1, logical circuit 202 comprise among Fig. 1 with door A1 and 2 not gates, counting module 203 comprises counter 1, latch 1, counter 2 and the latch 2 among Fig. 1, comparer 204 is the comparer among Fig. 1.With Fig. 3 is example, d type flip flop 201 comprises trigger D1, the D2 among Fig. 3, logical circuit 202 comprise among Fig. 1 with door A1, A1 and 2 not gates, counting module 203 comprises counter 1, latch 1, counter 2 and the latch 2 among Fig. 1, comparer 204 is the comparer among Fig. 1.Fig. 2,4,5 similarly repeats no more herein.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (13)
1, a kind of phase detection method is characterized in that, comprising:
The effective edge that uses first pulse signal obtains first count enable signal along the working direct current level is latched;
Obtain reset signal according to second pulse signal and first count enable signal, reset signal is effective when second pulse signal is significant level, and the cycle of described first pulse signal is the integral multiple in the cycle of second pulse signal;
By the win count enable signal level upset of effective reset enable signal, and the effective edge of reusing first pulse signal is along the working direct current level is latched;
Use a signal period to become the high-frequency clock of multiple relation with second pulse signal cycle, the effective pulse signal of level is counted, obtain first quantized value, this pulse signal effective edge along be synchronized with first pulse signal and reset signal when effective level effective, effective another pulse signal of level is counted, obtain second quantized value, this pulse signal effective edge is along being synchronized with second pulse signal, significant level continue duration less than the second pulse signal cycle time and reset signal when effective level effective;
According to effective reset signal first quantized value is latched output, second quantized value is latched output according to effective reset signal;
First pulse signal and the second pulse signal phase relation are determined in the output of latching of latching the output and first quantized value according to second quantized value.
2, the method for claim 1 is characterized in that, determines that the step of phase relation is specially:
If latching, second quantized value is output as zero, first quantized value latchs output greater than zero, then the first pulse signal phase place is ahead of second pulse signal, if latching, first quantized value is output as zero, second quantized value latchs output greater than zero, then the first pulse signal phase place lags behind second pulse signal, latchs output and is zero if first quantized value latchs output and second quantized value, and then first pulse signal and second pulse signal are synchronous.
3, method as claimed in claim 2, it is characterized in that, if latching, first quantized value is output as zero, second quantized value latchs output greater than presetting threshold value, then data signal phase is ahead of clock signal, be output as zero if second quantized value latchs, first quantized value latchs output greater than presetting threshold value, and then data signal phase lags behind clock signal.
4, method as claimed in claim 2, it is characterized in that, high-frequency clock is counted frequency division, when the reset signal effective edge when arriving, if phase place is leading, add on the counting divide ratio to high-frequency clock that then first quantized value latchs the value of output, if phase lag then deducts the value that second quantized value latchs output on the counting divide ratio to high-frequency clock.
5, the method for claim 1 is characterized in that, obtains the second quantized value step and is specially:
The effective edge that uses second pulse signal is along the working direct current level is latched;
The signal and second pulse signal after latching according to second pulse signal obtain second count enable signal, and when second pulse signal was significant level, second count enable signal was effective;
Effective second count enable signal of level is counted, obtained second quantized value.
6, the method for claim 1 is characterized in that, it to be 16 times of high-frequency clock cycle that the minimum period of clock signal is minimum.
7, the method for claim 1 is characterized in that, described first pulse signal is a data-signal, and described second pulse signal is a clock signal, and the described data-signal cycle is 2 times of clock signal period at least.
8, the method for claim 1 is characterized in that, described first pulse signal is a standard clock signal, and described second pulse signal is by the verification clock signal, and the described standard clock signal cycle is with little identical by the verification clock signal period.
9, a kind of device of phase-detection is characterized in that, comprising:
D type flip flop: be used to use the effective edge of first pulse signal along the working direct current level is latched, obtain first count enable signal, by the win count enable signal level upset of effective reset enable signal, and the effective edge of reusing first pulse signal is along the working direct current level is latched;
Logical circuit: be used for obtaining reset signal according to second pulse signal and first count enable signal, reset signal is effective when second pulse signal is significant level, and the cycle of described first pulse signal is the integral multiple in the cycle of second pulse signal;
Counting module: be used to use a signal period to become the high-frequency clock of multiple relation with second pulse signal cycle, the effective pulse signal of level is counted, obtain first quantized value, this pulse signal effective edge along be synchronized with first pulse signal and reset signal when effective level effective, effective another pulse signal of level is counted, obtain second quantized value, this pulse signal effective edge is along being synchronized with second pulse signal, significant level continue duration less than the second pulse signal cycle time and reset signal when effective level effective, according to effective reset signal first quantized value is latched output, second quantized value is latched output according to effective reset signal;
Comparer: be used for determining first pulse signal and the second pulse signal phase relation according to the output of latching of latching the output and first quantized value of second quantized value.
10, device as claimed in claim 9 is characterized in that,
Comparer: also be used for being output as zero if second quantized value latchs, first quantized value latchs output greater than zero, then the first pulse signal phase place is ahead of second pulse signal, if latching, first quantized value is output as zero, second quantized value latchs output greater than zero, then the first pulse signal phase place lags behind second pulse signal, latchs output and is zero if first quantized value latchs output and second quantized value, and then first pulse signal and second pulse signal are synchronous.
11, device as claimed in claim 10, it is characterized in that, comparer: also be used for being output as zero if first quantized value latchs, second quantized value latchs output greater than presetting threshold value, then data signal phase is ahead of clock signal, be output as zero if second quantized value latchs, first quantized value latchs output greater than presetting threshold value, and then data signal phase lags behind clock signal.
12, device as claimed in claim 10, it is characterized in that, comparer: also be used for high-frequency clock is counted frequency division, when the reset signal effective edge when arriving, if phase place is leading, add on the counting divide ratio to high-frequency clock that then first quantized value latchs the value of output, if phase lag then deducts the value that second quantized value latchs output on the counting divide ratio to high-frequency clock.
13, device as claimed in claim 9 is characterized in that,
Logical circuit: also be used to use the effective edge of second pulse signal along the working direct current level is latched, the signal and second pulse signal after latching according to second pulse signal obtain second count enable signal, when second pulse signal was significant level, second count enable signal was effective;
Counting module: also be used for effective second count enable signal of level is counted, obtain second quantized value.
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| CN102231627A (en) * | 2011-04-06 | 2011-11-02 | 中国科学院西安光学精密机械研究所 | Method and device for realizing short-time pulse signal |
| CN102611516A (en) * | 2012-01-17 | 2012-07-25 | 成都府河电力自动化成套设备有限责任公司 | Method and device for generating high-precision synchronous clock |
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| US6148050A (en) * | 1997-12-01 | 2000-11-14 | Ericsson Inc | Phase digitizer for radio communications |
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