CN101506988B - Schottky diode for sub-micro IC and method of making the same - Google Patents
Schottky diode for sub-micro IC and method of making the same Download PDFInfo
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- CN101506988B CN101506988B CN2006800554186A CN200680055418A CN101506988B CN 101506988 B CN101506988 B CN 101506988B CN 2006800554186 A CN2006800554186 A CN 2006800554186A CN 200680055418 A CN200680055418 A CN 200680055418A CN 101506988 B CN101506988 B CN 101506988B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000004888 barrier function Effects 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 16
- 230000008569 process Effects 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 31
- 229910044991 metal oxide Inorganic materials 0.000 claims description 23
- 150000004706 metal oxides Chemical class 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 22
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 208000005189 Embolism Diseases 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
A Schottky diode for sub-micro IC and method of making the same are provided. The Schottky diode comprises a substrate, a semiconductor layer (17), a metal-oxide-semiconductor gate dielectric layer (11), a barrier layer (31), a metal-oxide-semiconductor gate (14), and a wiring interconnection (51), wherein the gate dielectric layer (11), the barrier layer (31) and the wiring interconnection (51) are sequentialy laminated on the substrate. The barrier layer (31) is positioned between the gate dielectric layer (11) and the wiring interconnection (51). The wiring interconnection (51) directly contact the semiconductor layer (17), and there is no barrier layer (31) exiting between them. The Schottky diode and the method of making same same can meet the requirements of metal-oxide-semiconductor process and be suitable for integrated production of sub-micro IC also.
Description
Technical field
The present invention relates to a kind of integrated circuit component, particularly a kind of Schottky diode and manufacture method thereof that is applied to submicron integrated circuit.
Background technology
In sub-micron (sub-micro) technology, integrated circuit (IC) adopts tungsten embolism (W-Plug) contact hole and CMP (Chemical Mechanical Polishing) process (Chemical Mechanical PolishingProcess usually, hereinafter to be referred as CMP process) make, this manufacture method makes Schottky diode (Schottky diode) and the production not easy of integration of metal-oxide semiconductor (MOS) (Metal-oxide semiconductor is hereinafter to be referred as MOS) technology.Yet if directly tungsten embolism contact hole is directly contacted the formation Schottky diode with semiconductor layer, its usefulness will not be inconsistent the demand of MOS technology.
Summary of the invention
The purpose of this invention is to provide a kind of submicron integrated circuit that is applied to, and can with the Schottky diode of the integrated production of MOS technology and the manufacture method of this Schottky diode.
In view of above-mentioned purpose, the present invention proposes a kind of Schottky diode that is applied to submicron integrated circuit, comprises substrate, semiconductor layer, metal-oxide semiconductor (MOS) grid dielectric medium, barrier layer, metal-oxide semiconductor (MOS) grid, intraconnections material; Above-mentioned dielectric medium, above-mentioned barrier layer and above-mentioned intraconnections material are comply with down supreme sequence arrangement, above-mentioned barrier layer is present in the interlayer of above-mentioned metal-oxide semiconductor (MOS) grid dielectric medium with above-mentioned intraconnections material, above-mentioned semiconductor layer directly contacts with above-mentioned intraconnections material, and there is not barrier layer in the centre;
Above-mentioned metal-oxide semiconductor (MOS) grid contact with above-mentioned intraconnections material.
Above-mentioned barrier layer also is present in the interlayer of above-mentioned metal-oxide semiconductor (MOS) grid with above-mentioned intraconnections material.In the material of above-mentioned and the identical material of metal-oxide semiconductor (MOS) grid, there is asymmetric wall structure.Above-mentioned semiconductor layer comprises high-concentration dopant matter and low concentration doping matter.In the above-mentioned metal-oxide semiconductor (MOS) grid, the high-concentration dopant matter in its bottom semiconductor layer contacts with shallow groove isolation structure.Above-mentioned Schottky diode also comprises contact hole, is positioned at above-mentioned metal-oxide semiconductor (MOS) grid dielectric medium inside, and contact hole can adopt known integrated circuit contact structure.Above-mentioned submicron integrated circuit adopts tungsten embolism contact hole or CMP (Chemical Mechanical Polishing) process production.
The present invention also proposes a kind of as above-mentioned manufacture method of the Schottky diode that is applied to submicron integrated circuit, and it comprises the following step at least: the first step limits and opens the Schottky diode join domain on above-mentioned substrate; Second step, deposit barrier layers on above-mentioned substrate; The 3rd goes on foot, and removes the barrier layer of Schottky diode join domain on the above-mentioned substrate; In the 4th step, on above-mentioned substrate, connect material in the deposition; The 5th step connected above-mentioned substrate, limited and etching operation, formed Schottky diode.
Advantage of the present invention is this manufacture method that is applied to the Schottky diode and this Schottky diode of submicron integrated circuit, not only can satisfy the MOS process requirements, and is applicable to the integrated production of submicron integrated circuit.
State with other purposes, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 represents to pass through tungsten embolism contact hole or CMP (Chemical Mechanical Polishing) process substrate afterwards.
Fig. 2 is the schematic diagram that limits and open the Schottky diode join domain on substrate of one embodiment of the invention.
Fig. 3 is the deposit barrier layers schematic diagram on substrate of one embodiment of the invention.
Fig. 4 is the schematic diagram of the barrier layer of Schottky diode join domain on the removal substrate of one embodiment of the invention.
Fig. 5 is the schematic diagram that connects material on substrate in the deposition of one embodiment of the invention.
Fig. 6 connects substrate for one embodiment of the invention, limits and etching operation, forms the schematic diagram of Schottky diode.
Embodiment
Fig. 1 is a kind of known tungsten plug Metal Contact window or CMP (Chemical Mechanical Polishing) process substrate schematic diagram afterwards of having carried out.11,19 expression metal-oxide semiconductor (MOS) grid dielectric mediums, 12,14 expression metal-oxide semiconductor (MOS) grid, 13 expression walls, be positioned at around the material with the identical material of metal-oxide semiconductor (MOS) grid, 15 expression contact holes, it can be a tungsten embolism contact hole, 16 expression shallow groove isolation structures, 17 expression semiconductor layers, it comprises high-concentration dopant matter and low concentration doping matter, 18 expression traps.
Fig. 2 to Fig. 5 is respectively the schematic diagram of manufacture method that a kind of in a preferred embodiment of the present invention is applied to the Schottky diode of submicron integrated circuit, Fig. 2 is for limiting and open the schematic diagram after the Schottky diode join domain, be illustrated in the metal-oxide semiconductor (MOS) grid dielectric medium 11 of the position removal substrate of preparing to form Schottky diode on substrate.
Fig. 3 is the schematic diagram of deposit barrier layers 31 on substrate, is illustrated in the thin barrier layer 31 of this substrate top deposition one deck.
Fig. 4 is for removing the schematic diagram of the barrier layer 31 of Schottky diode join domain on the substrate, and expression forms above-mentioned preparation the barrier layer 31 at the position of Schottky diode and removes.
Fig. 5 is the schematic diagram that connects material 51 on substrate in the deposition, is illustrated in this substrate top deposition one deck to connect material 51.
Fig. 6 limits and etching operation for substrate is connected, and forms the schematic diagram of Schottky diode, connects material 51 and barrier layer 31 in expression is removed partly with final formation Schottky diode of the present invention.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the invention; when can doing a little change and improvement, so the present invention's protection range is as the criterion when looking the claim person of defining.
Claims (8)
1. a Schottky diode that is applied to submicron integrated circuit comprises substrate, semiconductor layer, metal-oxide semiconductor (MOS) grid dielectric medium, barrier layer, metal-oxide semiconductor (MOS) grid, and intraconnections material;
Above-mentioned metal-oxide semiconductor (MOS) grid dielectric medium, above-mentioned barrier layer and above-mentioned intraconnections material are comply with down supreme sequence arrangement; Above-mentioned barrier layer is present in the interlayer of above-mentioned metal-oxide semiconductor (MOS) grid dielectric medium with above-mentioned intraconnections material; Above-mentioned semiconductor layer directly contacts at the join domain of Schottky diode with above-mentioned intraconnections material, and there is not barrier layer in the centre;
Above-mentioned metal-oxide semiconductor (MOS) grid contact with above-mentioned intraconnections material.
2. Schottky diode according to claim 1 is characterized in that above-mentioned barrier layer also is present in the interlayer of above-mentioned metal-oxide semiconductor (MOS) grid with above-mentioned intraconnections material.
3. Schottky diode according to claim 2 is characterized in that having asymmetric wall structure in the above-mentioned metal-oxide semiconductor (MOS) grid.
4. Schottky diode according to claim 3 is characterized in that above-mentioned semiconductor layer comprises high-concentration dopant matter and low concentration doping matter.
5. Schottky diode according to claim 4 is characterized in that in the above-mentioned metal-oxide semiconductor (MOS) grid, the high-concentration dopant matter in its bottom semiconductor layer contacts with shallow groove isolation structure.
6. Schottky diode according to claim 5 is characterized in that above-mentioned Schottky diode also comprises contact hole, is positioned at above-mentioned metal-oxide semiconductor (MOS) grid dielectric medium inside.
7. Schottky diode according to claim 6 is characterized in that above-mentioned submicron integrated circuit adopts tungsten embolism contact hole or CMP (Chemical Mechanical Polishing) process production.
8. manufacture method that is applied to the Schottky diode of submicron integrated circuit as claimed in claim 1 is characterized in that comprising at least the following step:
The first step: on above-mentioned substrate, limit and open the Schottky diode join domain;
Second step: deposit barrier layers on above-mentioned substrate;
The 3rd step: the barrier layer of removing Schottky diode join domain on the above-mentioned substrate;
The 4th step: on above-mentioned substrate, connect material in the deposition;
The 5th step: above-mentioned substrate is connected, limit and etching operation, form Schottky diode.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2006/002104 WO2008022488A1 (en) | 2006-08-18 | 2006-08-18 | Schottky diode for sub-micro ic and method of making the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101506988A CN101506988A (en) | 2009-08-12 |
| CN101506988B true CN101506988B (en) | 2010-11-10 |
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ID=39106460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006800554186A Active CN101506988B (en) | 2006-08-18 | 2006-08-18 | Schottky diode for sub-micro IC and method of making the same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN101506988B (en) |
| WO (1) | WO2008022488A1 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5915179A (en) * | 1995-06-09 | 1999-06-22 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
| CN1547765A (en) * | 2001-08-23 | 2004-11-17 | 通用半导体公司 | Trench dmos transistor with embedded trench schottky rectifier |
-
2006
- 2006-08-18 CN CN2006800554186A patent/CN101506988B/en active Active
- 2006-08-18 WO PCT/CN2006/002104 patent/WO2008022488A1/en active Application Filing
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5915179A (en) * | 1995-06-09 | 1999-06-22 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
| CN1547765A (en) * | 2001-08-23 | 2004-11-17 | 通用半导体公司 | Trench dmos transistor with embedded trench schottky rectifier |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2008022488A1 (en) | 2008-02-28 |
| CN101506988A (en) | 2009-08-12 |
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Address after: 215123 333 Xinghua street, Suzhou Industrial Park, Jiangsu Patentee after: Warship chip manufacturing (Suzhou) Limited by Share Ltd Address before: 215123 333 Xinghua Street, Suzhou Industrial Park, Suzhou City, Jiangsu Province Patentee before: Hejian Technology (Suzhou) Co., Ltd. |
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