CN101501819B - 在具有受控界面特性和扩散尾的第ⅳ族衬底上制造半导体器件的方法 - Google Patents
在具有受控界面特性和扩散尾的第ⅳ族衬底上制造半导体器件的方法 Download PDFInfo
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Abstract
在斜切第IV族衬底上具有外延沉积的第III/V族化合物的电子和光电子器件及其制造方法。所述器件包括在Ge衬底上的AlAs成核层。所述第IV族衬底包含p-n结，在含As层的外延生长期间其特性的改变通过AlAs成核层得到最小化。所述AlAs成核层提供器件的改善的形态以及一种手段，以通过扩散As和/或P来控制p-n结位置接近第IV族衬底表面和通过最小化第IV族元素的扩散来控制p-n结位置接近第III/V族结构的底部。
Description
相关申请
本申请要求2006年8月11日提交的美国临时专利申请60/822,138的优先权，通过引用将其并入本文。
技术领域
本发明通常涉及电子和光电子器件的外延沉积。更具体地，本发明涉及在第IV族衬底上沉积第III/V族电子和光电子器件结构。
背景技术
在第IV族衬底上沉积用于第III/V族光电/电子器件如多结太阳能电池和发光二极管(LED)的层序列是已知的。这种器件的电子和光学性能正在被广泛研究，并且这些性能和衬底外延层界面特性之间的关联性受到极大关注。对于衬底外延层界面给予关注的原因多半是由于这些器件的性能由该界面的品质决定。
当在第IV族衬底例如Ge上外延沉积第III/V族材料例如GaAs时，不易于形成第III和V族层的合适的原子层序列。第IV族位点(Ge原子)可结合第III族或第V族原子。实际上，第IV族衬底的某些区域会结合第III族原子，而一些其它区域会结合第V族原子。这些不同的生长区之间的边界区产生相当的结构缺陷，如反相畴(anti-phase domains)，这不利地影响器件的性能。
为减少这些不希望事件中的一些，第IV族衬底通常是晶向偏角(off cutangle)为0-15°的斜切衬底(vicinal substrate)。这些斜切衬底提供其中原子能够与不同接合结构相附着的台面(terrace)和台阶边缘(step edge)，因此在生长工艺中提供更高级别。
在器件例如具有在第IV族衬底上外延沉积的第III/V族化合物的太阳能电池中，经常需要通过在第IV族衬底中扩散例如第V族物质从而在第IV族衬底中产生器件本身的一部分。作为一个实例，对于太阳能电池，如果在p-型Ge衬底中扩散第V族元素，那么形成n-型区域，产生p-n结。 该p-n结变成光活性的并且可以是单一或多结太阳能电池的一部分。然而，当在通常工艺温度(500-750℃)下在Ge衬底上沉积第III/V族化合物时，化合物的第V族元素在衬底中趋于难以控制地扩散，由此使得可预期的p-n结的形成变得困难。在包括具有预先存在的p-n结的Ge衬底的情况下，例如可以是在Ge、SiGe和SiC电子电路上的异质集成第III-V族光电/电子器件的情况下，沉积覆盖第III/V族化合物可改变预先存在的p-n结的掺杂分布，导致p-n结与器件的性能低于正常标准。因此，电特性难以控制。在此情况下，获得和保持衬底p-n结的期望的掺杂分布和电特性可变得相当困难，甚至是不可能，在太阳能电池的情况下，这些电特性包括开路电压(Voc)。此外，第IV族原子会从衬底扩散进入外延沉积的第III/V族层。因此，当没有通过使用适合的成核条件和材料来减小第IV族原子的过度扩散时，初始0.5～1μm的第III/V层序列内的层可高度掺杂有第IV族元素。第IV族原子例如Si和Ge在适中的浓度下通常是第III/V族半导体材料中的n-型掺杂剂。然而，这些原子由于它们的两性本质，因此在以显著大于2×1018cm-3的浓度引入时，可导致大程度的补偿(组合引入n-和p-型杂质)，经常导致基质半导体层的电性能和光学性能的显著劣化。
Ermer等人的美国专利6,380,601B1(以下称为Ermer)教导在p-型Ge衬底上的n掺杂的中间层上沉积GaInP，并在所述GaInP层上后续沉积GaAs二元化合物。GaInP层的磷在Ge衬底中的扩散不趋于如GaAs层的砷一样深。因此，磷掺杂和GaInP层的后续沉积使得能够较好地控制Ge衬底的n-型层的掺杂分布，并因此导致较好地控制在Ge衬底中形成的p-n结的电特性。然而，在Ge衬底界面处具有GaInP界面层的问题是：在用于这些材料的典型外延工艺条件下制备的器件的形态不理想：经常存在很多缺陷。似乎需要GaInP界面层的极端成核条件(温度、沉积速率、第V族过压)以获得具有适当形态的器件。
因此，需要提供在典型外延工艺条件下制造半导体器件的方法，所述半导体器件具有在第IV族衬底上外延沉积的第III/V族化合物，所述器件具有合适的形态，并且所述方法允许更好地控制光学和电学的界面特性以及在第IV族衬底中的扩散层。
发明内容
本发明的一个目的是避免或减轻具有在第IV族衬底上的外延第III/V族层的上述器件的至少一个缺点。
第一方面中，本发明提供一种半导体器件，所述半导体器件包括：第IV族层；和在所述第IV族层上形成的成核层。所述成核层包括第III-V族化合物，所述第III-V族化合物具有至少铝(Al)作为第III族元素以及砷(As)、氮(N)和锑(Sb)中的至少一种作为第V族元素。
第二方面中，本发明提供一种在第IV族层上制造半导体结构的方法。所述方法包括：在第IV族层上形成成核层的步骤，所述成核层包括第III-V族化合物，所述第III-V族化合物具有至少铝(Al)作为第III族元素以及砷(As)、氮(N)和锑(Sb)中的至少一种作为第V族元素。所述方法还包括在成核层上形成第一第III-V族化合物层的步骤。
第三方面中，本发明提供一种控制在第IV族衬底中形成的p-n结掺杂分布(doping profile)的方法。所述方法包括在第IV族衬底上形成成核层的步骤，所述成核层包括第III-V族化合物，所述第III-V族化合物具有至少铝(Al)作为第III族元素以及砷(As)、氮(N)和锑(Sb)中的至少一种作为第V族元素。所述方法还包括在成核层上形成第III-V族化合物层的步骤，所述成核层用于控制第V族元素扩散进入第IV族衬底和用于控制第IV族元素从第IV族衬底中扩散出来。
当参考下文结合附图对本发明的具体实施方案的描述时，本发明的其它方面和特征对于本领域技术人员将变得显而易见。
附图说明
现在将参考附图，通过仅作为示例的方式来描述本发明的实施方案，其中：
图1是本发明的一个实施方案的侧视图；
图2A和2B是本发明实施方案的具有不同厚度的AlAs成核层的照片；
图3是图1的实施方案的雾度测量值作为AlAs成核层厚度的函数图；
图4是在斜切Ge衬底上AlAs的沉积工艺的说明图；
图5是当AlAs层的厚度是零时，对于图1实施方案的结构的不同原子物质的SIMS数据图；
图6是当AlAs层的厚度是 时，对于图1实施方案的结构的不同 原子物质的SIMS数据图；
图7是本发明方法的流程图；
图8是作为图1实施方案的结构的AlAs厚度的函数的磷SIMS数据图；
图9是作为图1实施方案的结构的AlAs厚度的函数的砷SIMS数据图；
图10是作为图1实施方案的结构的AlAs厚度的函数的Ge SIMS数据图；
图11显示作为图1实施方案结构的四个不同的AlAs厚度的样品深度的函数的磷浓度；
图12显示作为图1实施方案结构的四个不同的AlAs厚度的样品深度的函数的砷浓度；
图13显示作为图1实施方案结构的四个不同的AlAs厚度的样品深度的函数的Ge浓度；
图14是具有类似于图1实施方案中显示的结构的光伏电池的电流对电压的图；和
图15是对于没有利用AlAs成核层制造的光生伏打电池和利用AlAs成核层制造的光生伏打电池的一系列电流对电压的图。
具体实施方式
通常，本发明提供制造具有其上沉积第III/V族层结构的第IV族衬底的电子或光电子器件的方法。所述方法使得能够制造具有改善的形态和进入第IV族衬底的第V族组分和进入第III/V族层的第IV族组分的受控掺杂分布的器件。
图1显示本发明包括的一个示例性三结半导体结构18。这种结构可用于多结太阳能电池例如三结太阳能电池中。此外，本领域技术人员可容易理解，类似的结构可用于发光二极管(LEDs)及其它电子和/或光电子器件。在斜切Ge衬底20顶上沉积厚度t1的AlAs层22。本领域技术人员可理解，术语“斜切”此处指的是在基面(fundamental plane)附近取向的晶面。斜切Ge衬底的角度可以为0°-20°；Ge衬底的晶体取向可以是朝向最 近的<111>平面例如为6°或任何其它适合的取向。在AlAs层22顶上是厚度为t2的GaInP层24和厚度为t3的GaAs层26。AlAs层22、GaInP层24和GaAs层26的沉积可通过诸如金属有机化学气相沉积(MOCVD)、化学束外延(CBE)、分子束外延(MBE)、固相外延(SPE)、氢化物气相外延或其它类似的混合系统或其组合的任何适当方法来实现。虽然显示Ge衬底20，但是也可以使用任何其它适合的第IV族衬底例如Si、SiGe或SiC衬底。此外，本领域技术人员可理解，上述说明也适用于以下情况：其中使用需要从第IV族材料到第III-V族化合物的过渡的器件，而不是第IV族衬底。类似地，可用具有高浓度Al其它的第III-V族化合物半导体合金例如AlN、AlSb或Al(Ga)As的来取代AlAs层，而没有脱离本发明的范围。
在图2A和2B中，比较了AlAs层22的两个不同厚度t1的结构18的形态。在图2A和2B中，试验结构28对应于t1＝0的结构18，试验结构30对应于具有t1＝4的单层AlAs的试验结构18。图2A和2B显示试验结构28和30的顶表面的显微照片，其中在所有情况下t2＝0.025μm，t3＝0.2μm。通过MOCVD在650-730℃的温度下，以GaAs、GaInP和AlAs的沉积速率分别为4μm/小时、0.8μm/小时和0.7-0.42μm/小时来制造试验结构28和30。
如图2A(Ge上的GaInP)所示，显示为白色斑点的缺陷数目显著比图2B(Ge上的AlAs)中较多。缺陷密度的数量级在图2A中为每平方厘米(cm2)数千而在图2B中基本上为0。这类缺陷在图2B上完全不存在。在图2B中部的大的斑点归因于在试验结构30上的杂质粒子，这不是成核工艺固有的。
图3显示结构18的雾度作为AlAs层22厚度t1的函数的图。所述测量采用由California的KLA-Tencor制造的SurfscanTM雾度测量设备来实施。由雾度图清楚可见：加入仅仅一小部分的单层AlAs即显著改善结构18的表面形态。
在后续第III/V族化合物之间具有中间AlAs层22的在斜切Ge衬底上沉积的第III/V族化合物的形态改善的原因如下。如图4A和4B所示，Al原子相对于As原子较小。因而，Al原子电化学势，该电化学势有利于这些Al原子位于在斜切Ge衬底20上存在的台阶(step)40处。因此，假如由于衬底温度而导致表面能足够高以允许发生表面重构，则在生长腔室中引入Al和As并允许经历充分的时间，将使得台阶40主要被Al原子 占据。这使得能够建立均匀的生长序列，导致形态完好的样品，如图2B所示，其中适当地建立成核序列并因此反相畴缺陷显著减少。该工艺是已知的成核工艺并且在图4A和4B示出的情况下可在沉积AlAs层外延层的典型温度(例如，650-730℃)下发生。
图5显示对类似于图2A的试验结构28的试验结构即t1＝0的结构18实施的二次离子质谱(SIMS)测量。线50表示Ge衬底20和第III/V族化合物之间的边界。由图5的SIMS图可看出，测量原子质量72(Ge)、75(As)、31(P)、27(Al)、69(Ga)和115(In)，作为暴露于通过3kV电压加速的Cs原子束的时间的函数。显示了通过SIMS束探测的暴露时间对深度的关系的深度标尺。值得注意的是：测量的是锗同位素72而不是普通的锗74。以此来避免原子质量为75的As的测量的任何干扰。
如图的区域52所示，P扩散进入Ge衬底并相对于所有其它的物质扩散占优势。这导致在Ge衬底中高水平的n-型导电率，这并不总是所需要的。在Ge衬底中存在这种水平的P可导致低的反向击穿电压，这是不能容许的。在这种结构中，在Ge衬底中P的扩散只能通过在Ge衬底上GaInP成核层的温度和厚度(生长时间)来控制。这使得很难控制Ge衬底中p-n结的参数。
因此，诸如在图2A中所示其中t1＝0的结构不仅显示出差的形态品质而且具有基本上无法控制的深入Ge衬底的n-型掺杂，所述结构具有在650-730℃下以0.8μm/小时的生长速率在Ge衬底上直接沉积的GaInP。在其中掺杂分布是可接受的情况下，所得器件的差的形态通常会产生较低的光电子性能。
图6显示对图2B的试验结构30即在Ge衬底20顶上具有t1＝4单层(AlAs)的样品来实施的SIMS测量。线50表示Ge衬底20和第III/V族化合物之间的边界。由图6的SIMS图可看出，测量原子量72(Ge)、75(As)、31+31+31(三离子体P)、69(Ga)和115(In)，作为暴露于通过3kV电压加速的Cs原子束的时间的函数。
显然，在Ge衬底中P的扩散显著小于图5中所示。在Ge衬底中P的扩散深度为约0.02μm，在Ge衬底中As的扩散为约0.10μm。因此，当制造类似于用于太阳能电池、LED或其它光电子或电子器件的结构18的结构时，更加非常容易在使用高Al含量合金诸如AlAs作为成核层时控制在Ge衬底中的掺杂分布。
图7显示用于结构如图1的结构18的工艺步骤。在步骤60，在p-型第IV族衬底上形成包含AlAs的成核层。在步骤62，实施包含磷的第III/V族层的外延沉积，同时在衬底表面附近形成p-n结。随后为步骤64，其中根据需要实施另外的半导体材料的外延沉积。
图8-10显示对于四个不同厚度t1的AlAs层22的类似于结构18的结构的其它SIMS数据。图8是显示采用仅仅 
的AlAs厚度在多大程度上减小了在Ge衬底中磷扩散的P分布。图9是显示极少As扩散进入Ge衬底的As分布。图10是显示AlAs层的存在显著减小Ge向外扩散进入第III/V族层的底部的Ge分布。Ge通常是在第III/V族材料中的n-型掺杂剂。Ge的增强的向外扩散将防止p-n结位置接近于成核层。图8-10中的每一个显示AlAs质量分布的轨迹以确定利用 
至 
所沉积的结构的界面位置。在t1＝0的沉积结构18的情况下，在界面显然没有检测到Al，但是其在半导体内部的位置可接近于72Ge或31P分布。图11-13显示相同数据组，但是这次根据材料标准进行分析，这允许溅射时间转换为分布深度和计数速率转换为原子浓度(对取样的同位素的相对丰度校正)。如图8-10所示，它们显示AlAs层厚度分别对作为样品深度函数的P、Ge和As原子浓度的影响。垂直的点画线标记第III-V族层和Ge衬底之间的边界。图11显示P扩散进入Ge衬底如何随着AlAs层的厚度增加而减小。图12显示如何通过选择AlAs层的合适厚度可调节As扩散进入Ge衬底。图13显示Ge扩散进入第III-V族层如何随着AlAs层的厚度增加而减小。一个AlAs的单层足以使得从与Ge衬底的界面的150nm内的Ge原子浓度下降到乃至低于1×1017cm-3。
图14显示具有类似于18的结构的Ge太阳能电池的作为电压函数的电流图。该Ge太阳能电池的开路电压(Voc)为0.247mV，在Voc下的电阻为7.2欧姆，短路电流密度(Jsc)为-36mA/cm2，串联电阻为2欧姆，填充因子(fill factor)为60.5％，所述填充因子为电流/电压图的垂直度(squareness)的度量。这些参数是Ge二极管具有良好性能的指示。
图15表示对于利用或不利用AlAs成核层制造的Ge太阳能电池的一系列的电流相对于电压的图。没有AlAs成核层的太阳能电池的两个电流/电压图由箭头指示。对于这些电池，Voc＝280mV，Jsc＝-36mA/cm2，串联电阻为2欧姆，填充因子为63％。在正向偏压也表现出良好的二极管性能，但是，如箭头所示，反向击穿电压非常差(约-0.2V)。具有AlAs成核层 的太阳能电池的电流/电压图没有显示击穿电压，表明AlAs成核提供整体上优异的二极管性能。更重要的是，在当使用AlAs成核层的情况下获得更平滑的形态，这对于在该p/n结上生长的其它有源元件性能而言通常将是关健的，例如在太阳能电池中通常如此。
虽然上述示例性实施方案显示在Ge衬底上生长第III/V族结构，本领域技术人员可容易地理解，可使用其它类型的第IV族衬底。类似地，虽然使用二元的AlAs化合物作为成核层，也应理解，包含AlAs的三元或四元的第III/V族化合物也可以用作成核层，而没有脱离本发明的范围。本领域技术人员可理解：本发明同样可适用于在包括或者不包括p-n结的所有种类的第IV族衬底上制造器件。此外，本领域技术人员可理解：当在第III和第V族原子之间在用于表面结合的电化学势或尺寸上存在显著差异时，第III-V族化合物的其它组合可以取代AlAs。这种第III-V族化合物包括例如AlN、AlSb或BAs、BSb、GaN、GaSb、InN、或InAs。
本领域技术人员可理解：虽然上述描述指的是p-型第IV族衬底，也可使用其它类型的第IV族衬底。这种衬底包括n-型、未掺杂的和半绝缘的衬底。
本发明提供制造具有其上沉积第III/V族层结构的第IV族衬底的电子或光电子器件的方法。所述方法使得能够制造具有改善的形态以及进入第IV族衬底的第V族组分和进入第III/V族层的第IV族组分的受控掺杂分布的器件。根据本发明制造的器件具有很好的反向击穿电压特性和极好的正向偏压特性，还具有平滑的形态，该形态对于在成核序列期间产生的p/n结上(或没有)外延生长另外的有源层是理想的。
本发明的上述实施方案意图是仅仅示例。本领域技术人员可对特定的实施方案进行改变、变更和变化，而没有脱离仅由所附的权利要求限定的本发明的范围。
Claims (15)
1.一种半导体器件，包括：
p-型锗层；和
在所述p-型锗层上形成的成核层，所述成核层是AlAs化合物；和
在所述成核层上形成的第一第III-V族GaInP化合物层，所述p-型锗层具有从所述第一第III-V族GaInP化合物层扩散的磷(P)原子，从所述第一第III-V族GaInP化合物层扩散扩到所述p-型锗层中的所述磷原子数随所述成核层的厚度的增大而减小，所述第一第III-V族GaInP化合物层具有从所述p-型锗层扩散的锗原子，扩散到所述第一第III-V族GaInP化合物层中的所述锗原子数随所述成核层的厚度的增大而减小。
2.根据权利要求1所述的器件，还包括在所述第一第III-V族GaInP化合物层上形成的第二第III-V族化合物层。
3.根据权利要求2所述的器件，其中所述第二第III-V族化合物层包括GaAs。
4.根据权利要求1所述的器件，其中所述p-型锗层具有邻近所述成核层的p-n结。
5.根据权利要求1所述的器件，其中所述器件是电子器件。
6.根据权利要求5所述的器件，其中所述电子器件是光电子器件。
7.根据权利要求6所述的器件，其中所述光电子器件是太阳能电池或发光二极管。
8.根据权利要求1所述的器件，其中所述p-型锗层是p-型锗衬底。
9.根据权利要求8所述的器件，其中所述p-型锗衬底是斜切衬底。
10.根据权利要求9所述的器件，其中所述斜切衬底具有0～20°的角度。
11.根据权利要求2所述的器件，其中所述成核层、所述第一第III-V族GaInP化合物层和所述第二第III-V族化合物层中的至少一个通过外延生长工艺形成。
12.根据权利要求1所述的器件，其中所述成核层的厚度为1～20个单层。
13.一种制造半导体结构的方法，所述方法包括以下步骤：
在p-型锗层上形成成核层，所述成核层是AlAs化合物；和
在所述成核层上形成第一第III-V族GaInP化合物层，所述p-型锗层具有从所述第一第III-V族GaInP化合物层扩散的磷(P)原子，从所述第一第III-V族GaInP化合物层扩散到所述p-型锗层中的所述磷原子数随所述成核层的厚度的增大而减小，所述第一第III-V族GaInP化合物层具有从所述p-型锗层扩散的锗原子，所述第一第III-V族GaInP化合物层中的所述锗原子数随所述成核层的厚度的增大而减小。
14.根据权利要求13所述的方法，还包括在所述第一第III-V族GaInP化合物层上形成第二第III-V族化合物层结构的步骤。
15.一种控制在衬底中形成的p-n结的掺杂分布的方法，所述方法包括以下步骤：
在p-型第IV族衬底上形成成核层，所述第IV族层包括锗(Ge)和硅锗(SiGe)中的一种，所述成核层包括第III-V族化合物，所述第III-V族化合物具有至少铝(Al)作为第III族元素以及砷(As)、氮(N)和锑(Sb)中的至少一种作为第V族元素；和
在所述成核层上形成第III-V族化合物层，所述第III-V族化合物层包括GaInP、AlInP和AlGaInP中的至少一种，所述成核层用于控制第V族元素扩散进入所述第IV族衬底和用于控制第IV族元素从所述第IV族衬底中扩散出来。
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| MX2009001151A (es) | 2009-04-30 |
| IL196477A0 (en) | 2009-09-22 |
| WO2008017143A1 (en) | 2008-02-14 |
| EP2428981A1 (en) | 2012-03-14 |
| US8124958B2 (en) | 2012-02-28 |
| EP2050124A4 (en) | 2009-10-21 |
| JP2010500741A (ja) | 2010-01-07 |
| US7872252B2 (en) | 2011-01-18 |
| CA2657504A1 (en) | 2008-02-14 |
| EP2050124B1 (en) | 2012-02-22 |
| EP2050124A1 (en) | 2009-04-22 |
| CY1112913T1 (el) | 2016-04-13 |
| US20110073913A1 (en) | 2011-03-31 |
| ES2383872T3 (es) | 2012-06-27 |
| CN101501819A (zh) | 2009-08-05 |
| BRPI0714267A2 (pt) | 2013-04-24 |
| US20080035939A1 (en) | 2008-02-14 |
| PT2050124E (pt) | 2012-05-28 |
| AU2007283383B2 (en) | 2013-01-10 |
| AU2007283383A1 (en) | 2008-02-14 |
| IL196477A (en) | 2012-05-31 |
| ATE546828T1 (de) | 2012-03-15 |
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