CN101499772A - Cascade 5 level frequency variant speed regulating circuit based on DSP and working method thereof - Google Patents
Cascade 5 level frequency variant speed regulating circuit based on DSP and working method thereof Download PDFInfo
- Publication number
- CN101499772A CN101499772A CNA2008101527971A CN200810152797A CN101499772A CN 101499772 A CN101499772 A CN 101499772A CN A2008101527971 A CNA2008101527971 A CN A2008101527971A CN 200810152797 A CN200810152797 A CN 200810152797A CN 101499772 A CN101499772 A CN 101499772A
- Authority
- CN
- China
- Prior art keywords
- output
- circuit
- dsp
- input
- cascade
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention provides a cascaded five-level frequency conversion speed regulation circuit based on a DSP, which is characterized in that the circuit consists of a phase-shifting transformer, a frequency converter main circuit, a detection circuit and a control circuit; the working method comprises a detection stage, a software control stage and a hardware working stage; the circuit has the advantages that a high-performance digital signal processing chip (DSP) and advanced electric and electronic technology (cascaded multi-level technology) are utilized to realize the cascaded five-level frequency conversion speed regulation circuit so as to improve the power quality of the output voltage of the frequency converter to a great extent; furthermore, the response speed and precision of the motor are improved greatly and the harmonic wave content and du/dt of the output voltage are reduced; the switch tube of an inverter works at a low-voltage and low-frequency (or power frequency) state, the switch loss and EMI are small, and the efficiency is high; and the invention is a new generation frequency conversion speed regulation device with excellent market prospect.
Description
(1) technical field:
The present invention relates to a kind of frequency variant speed regulating circuit, particularly a kind of frequency variant speed regulating circuit and method of work thereof of the cascade 5 level frequency converter based on DSP.
(2) background technology:
Electric energy is the power of current mankind development of civilization, also is an important indicator of national development of current measurement and people's lives.The electrical energy production of China has ranked world's first with development, but still can not satisfy the needs that industrial production and people's lives improve, one of them main cause is exactly that the waste of electric energy phenomenon is very serious, so frequency variant speed regulating circuit more and more is subject to people's attention with its excellent electricity saving performance.Frequency control is a kind of more satisfactory speed regulating method, and its speed adjusting performance is good, efficient is high, is the main developing direction of AC speed regulating circuit.Carry out the Variable Frequency and Speed Adjusting of Electromotor transformation, can reduce the overall performance of circuit energy consumption, optimization circuit, for enterprise wins considerable economic; Simultaneously can economize on resources, reduce environmental pollution, optimize operational environment etc., have good economic results in society.In frequency variant speed regulating circuit, frequency converter is its core component, and entire circuit is to finish required finishing of task by it, to reach saves energy, the purpose of protection environment.At present, frequency converter both domestic and external, the frequency converter of especially middle low capacity, still adopt the main circuit structure of two-level inverter, the voltage waveform quality of its output is not very desirable, particularly for the higher occasion of ask for something precision, be badly in need of a kind of output voltage quality height, new type inverter that switching loss is little.
(3) summary of the invention:
The object of the present invention is to provide a kind of cascade 5 level frequency variant speed regulating circuit and method of work thereof based on DSP, it is in conjunction with high performance signal processor (DSP) and advanced power electronic technology (cascade connection multi-level technology), construct a kind of novel being applicable to and be operated in the novel frequency variant speed regulating circuit that degree of precision requires occasion, quick to obtain, high-precision effect, and its output harmonic wave content is low, (THD) is little for irregularity of wave form, switching device IGBT switch number of times is few, dv/dt is little, switching loss is little, and market prospects are boundless.
Technical scheme of the present invention: a kind of cascade 5 level frequency variant speed regulating circuit based on DSP is characterized in that: it is made up of phase shifting transformer, main circuit of converter, testing circuit, control circuit; Wherein, the input of phase shifting transformer connects the power frequency electricity, and the output of phase shifting transformer connects the input of main circuit of converter; The output of main circuit of converter is connected respectively to testing circuit input and asynchronous machine; The testing circuit output connects the control circuit input, and the control circuit output is connected to main circuit of converter.
Above-mentioned said main circuit of converter is made up of 6 power cells, and each power cell all is AC/DC/AC frequency converters of a single-phase output, and a phase is formed in the output cascade of 2 adjacent power cells, and three-phase connects with star structure; The control circuit output is connected respectively to each power cell in the main circuit of converter.
Above-mentioned said control circuit adopts tertiary structure, and top layer is made up of a slice dsp chip, and the intermediate layer is made up of two CPLD chips, and bottom is made up of 4 CPLD chips, 2 A/D modular converters, 1 D/A modular converter and 2 fifo fifo chips; Wherein, the input of the dsp chip of top layer is connected to the output of the first CPLD chip in intermediate layer of being responsible for decoding, control D/A conversion, A/D conversion, FIFO read-write, and the output of the dsp chip of top layer is connected to is responsible for the input that the second CPLD chip in intermediate layer of pulse output and error protection interrupt requests distributed and sent to the PWM pulsewidth; The input of first CPLD chip in intermediate layer connects the output of the output of 2 fifo fifo chips of bottom, 2 A/D modular converters and the output of 1 D/A modular converter respectively; Detection signal is input to the input of the input of 2 fifo fifo chips of bottom, 2 A/D modular converters and the input of 1 D/A modular converter respectively; The output of the second CPLD chip in intermediate layer connects the input of 4 CPLD chips of bottom respectively, the output output control signal of 4 CPLD chips of bottom.
Above-mentioned said dsp chip adopts the TMS320C32 model.
2 CPLD chips in the intermediate layer of above-mentioned said control circuit adopt CY30785P84 model and CY37064P84 model respectively; 4 CPLD chips of the bottom of said control circuit all adopt the CY37064P84 model.
The A/D modular converter of above-mentioned said control circuit adopts the AD7684 model.
The D/A modular converter of above-mentioned said control circuit adopts the DAC4813 model.
The fifo fifo chip of above-mentioned said control circuit adopts the CY7C425 model.
A kind of method of work of above-mentioned cascade 5 level frequency variant speed regulating circuit based on DSP is characterized in that it comprised with the next stage:
(1) detection-phase: through 3/2 conversion, become that digital quantity signal is sent to DSP is in the control core circuit to testing circuit detected signal;
(2) the software control stage: with DSP is that the control core circuit calculates the output pwm pulse according to input variable according to selected control law, the trigger angle of power controlling switching device and the pass angle of rupture make each power cell output phase, the identical voltage of amplitude;
(3) the hardware effort stage: the voltage of each power cell output is through the sinusoidal voltage of stack formation different frequency and amplitude, and directly motor is supplied with in output.
Operation principle of the present invention is: electrical network is given and is shifted to transformer-supplied, through the step-down of transformer, gives 6 power models (the AC/DC/AC frequency converter of single-phase output) power supply again, and a phase is formed in the output cascade of 2 adjacent modules, and three-phase connects with star structure; Pwm pulse is exported in each unit under the control of controller, because these participate in the shared sine wave of PWM modulating wave of stack, the carrier wave that adjacent 2 unit PWM produce differs 90 °, phase place, the amplitude of the fundamental voltage that produces are identical, form sinusoidal voltage through stack, directly motor is supplied with in output; The present invention has the following function: data acquisition, variable frequency control, sequential control, man-machine interaction, failure diagnosis, error protection, fault warning, communication interface, memory function.
Central processing unit DSP application software is selected C language or assembler language usually for use, and starts with from the controlled function block diagram of frequency converter and state change process and to analyze design, and its programming process comprises following step:
(1) writes data dictionary to data variable-definition and management: extract data from computing formula, the state transition graph of circuit function block diagram, all data element tabulations relevant with circuit, and these variablees are carried out strict definition, accurately limit variable's attribute.When writing, data dictionary mainly comprises contents such as name variable, text description, data type, the scope of application, variable numerical value source, the numerical value domain of definition;
(2) dispatch between architecture Design and the module:, be a plurality of functional modules software demarcation according to software engineering method.The principle of dividing is strong interior poly-, loose coupling.Square is represented software function module, and arrow is represented the data flow direction, and filled arrows is represented the control information direction that flows, and the layering call relation wherein, at first is called on the functional module left side with one deck.Compare by analysis, the real-time that Control Parameter is calculated, the PWM pulsewidth is calculated and output control, hardware detection fault warning and error protection action, data send and receive is had relatively high expectations, and should adopt interrupt call.Priority level is divided into: error protection action, PWM pulsewidth are calculated and output control, data transmit-receive.The INTO interrupt priority level is the highest, and error protection and pulse output are public, by pulse distribution CPLD request, carries out service object by the decision of correlating markings variable in service routine, and the fault break in service is preferential; DSP carries serial ports and interrupts not using, serial communication uses the ST16C552 management of software ic, and the public external interrupt INT2 of data transmit-receive sends interrupt requests by ST16C552, in interrupt service routine,, determine the service object by reading the interrupt status register in this chip.The TimeO interrupt priority level is minimum, is responsible for calling control calculating and data acquisition, state exchange program module, and these contents are more, and a plurality of TimeO interrupt gradation to be finished in batches.In order to guarantee error protection and pulse output real-time, except fault interruption and the service of pulse output cycle interruption, the necessary energy of all breaks in service nested interrupt;
(3) design of software module process is write with code: according to subroutine module function and subroutine interface, analyze design module and realize detailed process, progressively refinement, refineing to each block diagram can be with till the computer instruction realization, adopt normal process figure to express then, just can obtain program code and write blueprint.
Superiority of the present invention is: 1. utilize high performance digital signal process chip (DSP) and advanced power electronic technology (cascade connection multi-level technology) to realize cascade 5 level frequency variant speed regulating circuit, can improve the quality of power supply of frequency converter output voltage to a great extent, make the response speed of motor and precision also have significant improvement; 2. harmonic component in output voltage and du/dt have been reduced; 3. the switching tube of inverter is operated in low pressure low frequency (or power frequency) state, and switching loss and EMI are less, and efficient is higher, is a kind of frequency variant speed regulating circuit of new generation with very big market prospect.
(4) description of drawings:
Accompanying drawing 1 is the system architecture diagram of the related a kind of cascade 5 level frequency variant speed regulating circuit based on DSP of the present invention.
Accompanying drawing 2 is the main circuit of converter topological diagram of the related a kind of cascade 5 level frequency variant speed regulating circuit based on DSP of the present invention.
Accompanying drawing 3 is the control circuit structured flowchart of the related a kind of cascade 5 level frequency variant speed regulating circuit based on DSP of the present invention.
Accompanying drawing 4 is the control circuit functional block diagram of the related a kind of cascade 5 level frequency variant speed regulating circuit based on DSP of the present invention.
(5) embodiment:
Embodiment: a kind of cascade 5 level frequency variant speed regulating circuit (seeing accompanying drawing 1) based on DSP, it is characterized in that: it is made up of phase shifting transformer, main circuit of converter, testing circuit, control circuit; Wherein, the input of phase shifting transformer connects the power frequency electricity, and the output of phase shifting transformer connects the input of main circuit of converter; The output of main circuit of converter is connected respectively to testing circuit input and asynchronous machine; The testing circuit output connects the control circuit input, and the control circuit output is connected to main circuit of converter.
Above-mentioned said main circuit of converter (seeing accompanying drawing 1,2) is made up of 6 power cells, and each power cell all is AC/DC/AC frequency converters of a single-phase output, and a phase is formed in the output cascade of 2 adjacent power cells, and three-phase connects with star structure; The control circuit output is connected respectively to each power cell in the main circuit of converter.
Above-mentioned said control circuit (seeing accompanying drawing 3,4) adopts tertiary structure, top layer is made up of a slice dsp chip, the intermediate layer is made up of two CPLD chips, and bottom is made up of 4 CPLD chips, 2 A/D modular converters, 1 D/A modular converter and 2 fifo fifo chips; Wherein, the input of the dsp chip of top layer is connected to the output of the first CPLD chip in intermediate layer of being responsible for decoding, control D/A conversion, A/D conversion, FIFO read-write, and the output of the dsp chip of top layer is connected to is responsible for the input that the second CPLD chip in intermediate layer of pulse output and error protection interrupt requests distributed and sent to the PWM pulsewidth; The input of first CPLD chip in intermediate layer connects the output of the output of 2 fifo fifo chips of bottom, 2 A/D modular converters and the output of 1 D/A modular converter respectively; Detection signal is input to the input of the input of 2 fifo fifo chips of bottom, 2 A/D modular converters and the input of 1 D/A modular converter respectively; The output of the second CPLD chip in intermediate layer connects the input of 4 CPLD chips of bottom respectively, the output output control signal of 4 CPLD chips of bottom.
Above-mentioned said dsp chip (seeing accompanying drawing 3) adopts the TMS320C32 model.
2 CPLD chips in the intermediate layer of above-mentioned said control circuit (seeing accompanying drawing 3) adopt CY30785P84 model and CY37064P84 model respectively; 4 CPLD chips of the bottom of said control circuit all adopt the CY37064P84 model.
The A/D modular converter of above-mentioned said control circuit (seeing accompanying drawing 3) adopts the AD7684 model.
The D/A modular converter of above-mentioned said control circuit (seeing accompanying drawing 3) adopts the DAC4813 model.
The fifo fifo chip of above-mentioned said control circuit (seeing accompanying drawing 3) adopts the CY7C425 model.
A kind of method of work of above-mentioned cascade 5 level frequency variant speed regulating circuit based on DSP is characterized in that it comprised with the next stage:
(1) detection-phase: through 3/2 conversion, become that digital quantity signal is sent to DSP is in the control core circuit to testing circuit detected signal;
(2) the software control stage: with DSP is that the control core circuit calculates the output pwm pulse according to input variable according to selected control law, the trigger angle of power controlling switching device and the pass angle of rupture make each power cell output phase, the identical voltage of amplitude;
(3) the hardware effort stage: the voltage of each power cell output is through the sinusoidal voltage of stack formation different frequency and amplitude, and directly motor is supplied with in output.
Claims (9)
1, a kind of cascade 5 level frequency variant speed regulating circuit based on DSP, it is characterized in that: it is made up of phase shifting transformer, main circuit of converter, testing circuit, control circuit; Wherein, the input of phase shifting transformer connects the power frequency electricity, and the output of phase shifting transformer connects the input of main circuit of converter; The output of main circuit of converter is connected respectively to testing circuit input and asynchronous machine; The testing circuit output connects the control circuit input, and the control circuit output is connected to main circuit of converter.
2, according to the said a kind of cascade 5 level frequency variant speed regulating circuit of claim 1 based on DSP, it is characterized in that said main circuit of converter is made up of 6 power cells, each power cell all is AC/DC/AC frequency converters of a single-phase output, a phase is formed in the output cascade of 2 adjacent power cells, and three-phase connects with star structure; The control circuit output is connected respectively to each power cell in the main circuit of converter.
3, according to the said a kind of cascade 5 level frequency variant speed regulating circuit of claim 1 based on DSP, it is characterized in that said control circuit adopts tertiary structure, top layer is made up of a slice dsp chip, the intermediate layer is made up of two CPLD chips, and bottom is made up of 4 CPLD chips, 2 A/D modular converters, 1 D/A modular converter and 2 fifo fifo chips; Wherein, the input of the dsp chip of top layer is connected to the output of the first CPLD chip in intermediate layer of being responsible for decoding, control D/A conversion, A/D conversion, FIFO read-write, and the output of the dsp chip of top layer is connected to is responsible for the input that the second CPLD chip in intermediate layer of pulse output and error protection interrupt requests distributed and sent to the PWM pulsewidth; The input of first CPLD chip in intermediate layer connects the output of the output of 2 fifo fifo chips of bottom, 2 A/D modular converters and the output of 1 D/A modular converter respectively; Detection signal is input to the input of the input of 2 fifo fifo chips of bottom, 2 A/D modular converters and the input of 1 D/A modular converter respectively; The output of the second CPLD chip in intermediate layer connects the input of 4 CPLD chips of bottom respectively, the output output control signal of 4 CPLD chips of bottom.
4,, it is characterized in that said dsp chip adopts the TMS320C32 model according to the said a kind of cascade 5 level frequency variant speed regulating circuit of claim 3 based on DSP.
5,, it is characterized in that 2 CPLD chips in the intermediate layer of said control circuit adopt CY30785P84 model and CY37064P84 model respectively according to the said a kind of cascade 5 level frequency variant speed regulating circuit of claim 3 based on DSP; 4 CPLD chips of the bottom of said control circuit all adopt the CY37064P84 model.
6,, it is characterized in that the A/D modular converter of said control circuit adopts the AD7684 model according to the said a kind of cascade 5 level frequency variant speed regulating circuit of claim 3 based on DSP.
7,, it is characterized in that the D/A modular converter of said control circuit adopts the DAC4813 model according to the said a kind of cascade 5 level frequency variant speed regulating circuit of claim 3 based on DSP.
8,, it is characterized in that the fifo fifo chip of said control circuit adopts the CY7C425 model according to the said a kind of cascade 5 level frequency variant speed regulating circuit of claim 3 based on DSP.
9, a kind of method of work of the cascade 5 level frequency variant speed regulating circuit based on DSP is characterized in that it comprised with the next stage:
(1) detection-phase: through 3/2 conversion, become that digital quantity signal is sent to DSP is in the control core circuit to testing circuit detected signal;
(2) the software control stage: with DSP is that the control core circuit calculates the output pwm pulse according to input variable according to selected control law, the trigger angle of power controlling switching device and the pass angle of rupture make each power cell output phase, the identical voltage of amplitude;
(3) the hardware effort stage: the voltage of each power cell output is through the sinusoidal voltage of stack formation different frequency and amplitude, and directly motor is supplied with in output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101527971A CN101499772A (en) | 2008-11-03 | 2008-11-03 | Cascade 5 level frequency variant speed regulating circuit based on DSP and working method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101527971A CN101499772A (en) | 2008-11-03 | 2008-11-03 | Cascade 5 level frequency variant speed regulating circuit based on DSP and working method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101499772A true CN101499772A (en) | 2009-08-05 |
Family
ID=40946681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2008101527971A Pending CN101499772A (en) | 2008-11-03 | 2008-11-03 | Cascade 5 level frequency variant speed regulating circuit based on DSP and working method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101499772A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103731042A (en) * | 2013-09-11 | 2014-04-16 | 上海交通大学 | AC-AC variable frequency phase control trigger device |
| CN104638881A (en) * | 2013-11-12 | 2015-05-20 | 哈尔滨商业大学 | Three-phase power supply |
| CN105763069A (en) * | 2016-02-29 | 2016-07-13 | 珠海格力电器股份有限公司 | Voltage regulating system and method |
-
2008
- 2008-11-03 CN CNA2008101527971A patent/CN101499772A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103731042A (en) * | 2013-09-11 | 2014-04-16 | 上海交通大学 | AC-AC variable frequency phase control trigger device |
| CN104638881A (en) * | 2013-11-12 | 2015-05-20 | 哈尔滨商业大学 | Three-phase power supply |
| CN104638881B (en) * | 2013-11-12 | 2017-08-25 | 哈尔滨商业大学 | A kind of three phase mains |
| CN105763069A (en) * | 2016-02-29 | 2016-07-13 | 珠海格力电器股份有限公司 | Voltage regulating system and method |
| CN105763069B (en) * | 2016-02-29 | 2018-11-06 | 珠海格力电器股份有限公司 | Voltage-regulating system and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106649927B (en) | FPGA-based real-time simulation combined modeling method for power electronic element | |
| CN101667787B (en) | Voltage oriented energy bidirectional flowing rectifier control device | |
| CN102739100B (en) | Three-level three-phase four-bridge arm converter | |
| CN102593859B (en) | Three-phase UPQC (Unified Power Quality Controller) topology circuit based on MMC (Multi Media Card) | |
| CN103311932A (en) | Double-DSP (digital signal processor) control system based on chained SVG (scalable vector graphics) | |
| CN101615853A (en) | The voltage vector pulse duration modulation method in three-level PWM rectifier symmetry three districts | |
| CN201197078Y (en) | Mixing type static idle work generator | |
| CN1738172B (en) | Matrix type middle, high voltage variable-frequency power supply | |
| CN106026096A (en) | SVG-based multi-level coordination energy-saving optimization control system for distribution network | |
| CN103472734A (en) | Semi-physical simulation method and system of urban rail traction system | |
| CN101699765A (en) | Cascade multilevel variable frequency speed control system based on phase-shifting SVPWM modulation method | |
| CN204068723U (en) | A kind of three-phase voltage sag generating means | |
| CN103457478A (en) | Cascading type multi-level frequency converter control system based on DSP and FPGA | |
| CN201563101U (en) | Cascade multi-level variable frequency speed-control device based on phase-shifting SVPWM modulator method | |
| CN202353217U (en) | Dynamic voltage quick compensating device | |
| CN103647526B (en) | A kind of PWM locking control circuits | |
| CN101499772A (en) | Cascade 5 level frequency variant speed regulating circuit based on DSP and working method thereof | |
| CN101502908A (en) | Complete digital inversion type square wave alternating-current argon arc welder | |
| Ruiz et al. | Design methodologies and programmable devices used in power electronic converters—A survey | |
| CN201623641U (en) | Rectification control device for double-flow voltage directional energy | |
| CN204190402U (en) | Building photovoltaic generation supply intelligent system | |
| CN102545269B (en) | Series type digital-analog comprehensive simulation system interface | |
| CN202443262U (en) | Parallel-type digital/analog comprehensive simulation system interface and physical simulation subsystem interface | |
| CN103236729A (en) | TMS320F2812-based digital control system for uninterrupted power supply (UPS) | |
| CN203826969U (en) | Chained SVG control circuit based on DSP and FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Open date: 20090805 |