CN101499464B - Method for manufacturing stack package using through-electrodes - Google Patents
Method for manufacturing stack package using through-electrodes Download PDFInfo
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- CN101499464B CN101499464B CN2009100033822A CN200910003382A CN101499464B CN 101499464 B CN101499464 B CN 101499464B CN 2009100033822 A CN2009100033822 A CN 2009100033822A CN 200910003382 A CN200910003382 A CN 200910003382A CN 101499464 B CN101499464 B CN 101499464B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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Abstract
Manufacturing a wafer level stack package includes the steps of back-grinding a lower surface of a wafer including a plurality of first semiconductor chips. A support member is attached to a lower surface of the back-grinded wafer. One or more second semiconductor chips are stacked on the respective first semiconductor chips of the back-grinded wafer. First through-electrodes are formed to electrically connect the stacked first semiconductor chips and second semiconductor chips. Third semiconductor chips are attached to uppermost ones of the stacked second semiconductor chips, and the third semiconductor chips have second through-electrodes which are electrically connected to the first through-electrodes and re-distribution lines which are connected to the second through-electrodes. Outside connection terminals are attached to the re-distribution lines of the third semiconductor chips. The first semiconductor chips of a wafer level on which the second and third semiconductor chips are stacked are sawed to for semiconductor packages at a chip level.
Description
Technical field
The present invention generally relates to the method for preparing stacked package (stack package), more specifically, relates to a kind of method for preparing stacked package, and it can prevent from preparing decline and because the quality reduction of the semiconductor chip that thermal fatigue causes of yield.
Background technology
In semiconductor industry, the positive various encapsulation technologies of sustainable development are to satisfy the lasting demand for miniaturization and installation reliability.For example, accelerated the encapsulation exploitation to making package dimension very near the degree of the size of chip own for the demand of miniaturization.Accelerated for the installation exercise usefulness of improving the rear device of installation and mechanical, the electrically technical development of reliability for the demand that reliability is installed.
The development trend of electrical equipment and electronic installation obviously just strides forward towards miniaturization and high functionality.In order to stride forward towards less and multi-functional device, to research and develop various technology the module of the semiconductor with high power capacity is being provided.A kind ofly just provide the integrated semiconductor chip of a kind of height in order to the technology that the semiconductor module with high power capacity is provided.Owing to require miniaturization, so unit (cell) can be formed in the zone limited in the semiconductor chip.Therefore, realize the semiconductor chip of high integration by integrated more unit in the finite region of semiconductor chip.
Yet the storage chip of high integration needs high precision technology (for example fine linewidth) and tediously long construction cycle.Because this restriction, the past has proposed various Stack Technologies with as the another kind of method that the semiconductor module with high power capacity is provided.
At present, in various Stack Technologies, the most widely used Stack Technology is the stacked package of using through-electrode.In the stacked package of using through-electrode, stacking semiconductor chip is electrically connected mutually via through-electrode.The use of through-electrode causes stacked package size reduction and signal transmission path to shorten.Therefore, stacked package is so that become possible towards miniaturization and multifunctionality.
Generally speaking, use the stacked package of through-electrode can be divided into two types: in the first kind, through-electrode is formed in wafer (wafer) the level chip, and all techniques were namely finished before stacking, and chip is cut then stacking with chip-scale afterwards; In the Second Type, with through-electrode form and at the wafer of stacking front all techniques of experience with wafer level stack, then cut.
Although diagram and describing in detail not, in the first kind that forms stacked package, because can the stacking semiconductor chip that has passed through test process, therefore can promote the preparation yield.Yet in the first kind, the required technique number of preparation stacked package increases.Moreover when welding was used for stacked semiconductor chips, problem was that the configuration of solder ball and welding temperature cause the semiconductor chip quality to reduce.In the stacked package of Second Type, can reduce process costs and technique itself can be simplified.Yet, all techniques are all carried out at wafer scale in Second Type, therefore problem is, if a plurality of semiconductor chips of wafer when the preparation yield of preparation initial period is not good, in the end the preparation yield of the stacked package of preparatory phase might descend suddenly.
Therefore, when preparation has the stacked package of through-electrode, need a kind of can prevent from preparing yield reduction and because the new technology that the semiconductor chip quality that thermal fatigue causes reduces.
Summary of the invention
Embodiments of the invention are for a kind of method for preparing stacked package, and it can prevent from preparing, and yield reduces and because the semiconductor chip quality reduction that thermal fatigue causes.
In one aspect of the invention, a kind of method of making wafer level stack package comprises step: grinding back surface comprises the lower surface of the wafer of a plurality of the first semiconductor chips; Supporting member is invested described by the lower surface of the wafer of grinding back surface; Described by each first semiconductor chip of the wafer of grinding back surface on stacking one or more the second semiconductor chips; Form the first through-electrode to be electrically connected the first stacking semiconductor chip and the second semiconductor chip; The 3rd semiconductor chip is attached to uppermost chip in the second stacking semiconductor chip, and the 3rd semiconductor chip has the second through-electrode that is electrically connected to the first through-electrode and the line of reshuffling that is connected with the second through-electrode; External connection terminals is connected to the line of reshuffling of the 3rd semiconductor chip; And with on it stacking second and the first semiconductor chip of the wafer scale of the 3rd semiconductor chip cut into chip-scale.
This supporting member can comprise any in glass and the chip carrier.
Carried out by first semiconductor chip that is regarded as good dies (die) of the wafer of grinding back surface for stacking of the second semiconductor chip.
After forming the step of the first through-electrode and before the step of attaching the 3rd semiconductor chip, the method also comprises the step that removes this supporting member.
After connecting the step of external connection terminals and cutting before the first semiconductor chip becomes the step of chip-scale, the method also comprises the step that removes this supporting member.
The step of stacking the second semiconductor chip can utilize adhesive or adhesive tape to carry out.
The step that forms the first through-electrode comprises step: define through hole via the second and first stacking semiconductor chip of etching until expose supporting member; And metallic alloy is filled in this through hole.
The step of filling metallic alloy can be by inserting metal pins (pin) or carrying out by plating (plating).
This first, second, and third semiconductor chip can comprise the semiconductor chip of the same type with identical function.
For the election, this first, second, and third semiconductor chip can comprise the dissimilar semiconductor chip with difference in functionality.
In the present invention on the other hand, a kind of method for preparing wafer level stack package comprises step: grinding back surface comprises the lower surface of the wafer of a plurality of the first semiconductor chips; Supporting member is attached to described by the lower surface of the wafer of grinding back surface; Described by each first semiconductor chip of the wafer of grinding back surface on stacking one or more the second semiconductor chips; Form the first through-electrode to be electrically connected stacking the first semiconductor chip and the second semiconductor chip; The 3rd semiconductor chip is attached to uppermost chip in the second stacking semiconductor chip; In the 3rd semiconductor chip, form and be electrically connected to the second through-electrode of the first through-electrode and the line of reshuffling that is connected with the second through-electrode; External connection terminals is connected to the line of reshuffling of the 3rd semiconductor chip; And with on it stacking second and the first semiconductor chip of the wafer scale of the 3rd semiconductor chip cut into chip-scale.
This supporting member can comprise any in glass and the chip carrier.
Carried out by first semiconductor chip that is regarded as good dies (die) of the wafer of grinding back surface for stacking of the second semiconductor chip.
After forming the step of the first through-electrode and before the step of attaching the 3rd semiconductor chip, the method also comprises the step that removes this supporting member.
After connecting the step of external connection terminals and cutting before the first semiconductor chip becomes the step of chip-scale, the method also comprises the step that removes this supporting member.
The step of stacking the second semiconductor chip can utilize adhesive or adhesive tape to carry out.
The step that forms the first through-electrode comprises step: second semiconductor chip and first semiconductor chip stacking via etching define through hole until expose supporting member; And metallic alloy is filled in this through hole.
The step of filling metallic alloy can be by inserting metal pins (pin) or carrying out by plating (plating).
This first, second, and third semiconductor chip can comprise the semiconductor chip of the same type with identical function.
For the election, this first, second, and third semiconductor chip can comprise the dissimilar semiconductor chip with difference in functionality.
Description of drawings
Figure 1A-1F is cutaway view, is used for illustrating the operation of the method for preparing according to an embodiment of the invention stacked package.
Embodiment
The below will briefly describe know-why of the present invention.In the present invention, when semiconductor chip tested and be confirmed as good dies after, semiconductor chip is stacked on each semiconductor chip of wafer.Then, form through-electrode to be electrically connected stacking semiconductor chip with wafer scale.Then wafer is cut into chip-scale, prepares by this a plurality of stacked package.
Therefore, routine techniques stacking with chip-scale with semiconductor chip and that then form through-electrode is compared, and number of processes reduces in the present invention.In the present invention, can solve the relevant problem of semiconductor chip quality decline that causes with welding temperature.In addition, in the present invention, owing to test to determine good crystal grain before on the wafer level semiconductor chip in that semiconductor chip is stacking, so can solve initial preparatory phase because the semiconductor chip of wafer prepares the not good yield that causes of yield descends suddenly.Particularly, when on the stacking wafer level semiconductor chip in being defined as good dies of the semiconductor chip that only is defined as good dies, the preparation yield can significantly promote.
Hereinafter, a specific embodiment of the present invention is described with reference to the accompanying drawings.
Figure 1A-1F is cutaway view, and the according to an embodiment of the invention preparation method's of stacked package operation is shown.
With reference to Figure 1A, prepare to comprise through being confirmed as the wafer 100 (causing by this high preparation yield) of a plurality of first semiconductor chips 102 of good dies after the test.Each first semiconductor chip 102 has the first weld pad 104.
With reference to Figure 1B, the predetermined thickness of the lower surface of wafer 100 is by grinding back surface.Reference numeral 100a represents by the wafer of grinding back surface.Supporting member 110 for example glass or chip carrier is attached to by the lower surface of the wafer 100a of grinding back surface.
With reference to Fig. 1 C, one or more the second semiconductor chips 112 only be stacked on supporting member 110 be attached to its lower surface by on the chip that is confirmed as good dies in the first semiconductor chip 102 of the wafer 100a of grinding back surface.That is to say that one or more the second semiconductor chips (only) are stacked on each of the first semiconductor chip 110 of being defined as good dies.In an embodiment of the present invention, the second semiconductor chip 112 is optional from the semiconductor chip that is confirmed as good dies from the wafer with low fine ratio of product.Then, these selected semiconductor chips can cut from the wafer with low preparation yield, and then provide as the second semiconductor chip 112.For example, if a wafer is confirmed as having the wafer of low good dies productive rate, then this wafer can be selected as the wafer of supplying with the second semiconductor chip.Under any circumstance, the second semiconductor chip 112 (it is chip-scale) should be the semiconductor chip that is confirmed as good dies.Each second semiconductor chip 112 has the second weld pad 114, and for example adhesive or adhesive tape are stacked on corresponding the first semiconductor chip 102 (or second semiconductor chip corresponding with the first semiconductor chip) to use adhesive member 120.In addition, the second semiconductor chip 112 is for example facing up stacking in a mode, so that the second weld pad 114 of the correspondence of the first weld pad 104 of the first semiconductor chip 102 and the second semiconductor chip 112 is aimed at along vertical line.
With reference to Fig. 1 D, by etching the first semiconductor chip 102 and be stacked in one or more the second semiconductor chips 112 on the first corresponding semiconductor chip 102 each until supporting member 110 is exposed, define through hole.For example, through hole is defined as all weld pads 104 and 114 that pass the first stacking semiconductor chip 102 and one or more second semiconductor chips 112 corresponding with the first semiconductor chip, and the weld pad that through hole passes is aimed at along vertical line.
By using the metallic alloy filling vias, in through hole, form the first through-electrode 130, thereby connect the weld pad 104 and 114 of the correspondence of the first stacking semiconductor chip 102 and the second semiconductor chip 112.That is to say that the weld pad of aiming at along vertical line connects by the metallic alloy that is filled in each corresponding through hole.The first through-electrode 130 for example forms by depositing process or by inserting metal pins.
With reference to Fig. 1 E, be attached to by the supporting member 106 of the lower surface of the wafer 100a of grinding back surface and be removed.The 3rd semiconductor chip 132 is attached to the uppermost chip in the second stacking semiconductor chip 112.The 3rd semiconductor chip 132 as block crystal grain and have the second through-electrode 140 that is electrically connected to the first through-electrode 130 and be electrically connected to the second through-electrode 140 reshuffle line 146.The 3rd semiconductor chip 132 utilizes adhesive member 120 in the mode identical with adhering to of the second semiconductor chip 112, and for example adhesive or adhesive tape adhere to.With the external connection terminals 150 of the erecting device of accomplishing external circuit for example solder ball be attached to the ball-pads part of reshuffling line 146 of the 3rd semiconductor chip 132.
With reference to Fig. 1 F, the 3rd semiconductor chip 132 that stacking external connection terminals 150 is connected on it and the wafer 100a by grinding back surface of one or more the second semiconductor chips 112 are cut.By this cutting, form according to an embodiment of the invention stacked package 200, wherein the first semiconductor chip 102, one or more the second semiconductor chip 112 and be stacked and be electrically connected to each other by the first and second through- electrodes 130 and 140 as the 3rd semiconductor chip 132 of block crystal grain.
From the above description, in the present invention, the individual semiconductor chip that is confirmed as good dies uses adhesive member, and for example adhesive or adhesive tape are stacked on have a plurality of good dies each semiconductor chip (this semiconductor chip is good dies) of correspondence of wafer of (therefore having high preparation yield).Through-electrode forms to be electrically connected the semiconductor chip with wafer level stack, and wafer is cut into chip-scale afterwards, prepares thus stacked package.
Therefore, in the present invention, only good dies is stacked, and therefore compared to routine techniques, can promote the preparation yield.Particularly, when the semiconductor chip that is confirmed as good dies only was stacked on the semiconductor chip of the wafer that also is confirmed as good dies, the preparation yield can further promote.In addition, in the present invention, the complicated technology that forms through-electrode carries out rather than carries out in chip-scale at wafer scale, therefore can reduce number of processes and processing cost.In addition, in the present invention, semiconductor chip with adhesive member stacking and thereby do not need thermal process; Therefore can prevent semiconductor chip quality decline owing to thermal fatigue.
In the preparation method of stacked package according to an embodiment of the invention, the first to the 3rd stacking semiconductor chip can comprise same type or dissimilar minutes semiconductor chips according to the occasion demand mutually.
Although in the aforementioned embodiment, be attached to by the supporting member of the lower surface of the wafer of grinding back surface and before adhering to the 3rd semiconductor chip, be removed, but should be understood that this supporting member can be removed after reshuffling line adhering to the 3rd semiconductor chip or external connection terminals is connected to.
In addition, in the preparation method of above-mentioned according to an embodiment of the invention stacked package, be attached to the second semiconductor chip as the 3rd semiconductor chip of block crystal grain with the state that is formed with the second through-electrode and reshuffle line.Thus, in another embodiment of the present invention, can predict, be attached to the second semiconductor chip and after not having the second through-electrode and reshuffling line at the 3rd semiconductor chip, the second through-electrode and reshuffle that line can be formed in the 3rd accompanying semiconductor chip or on.In the preparation method of stacked package according to another embodiment of the present invention, except adhering to the 3rd semiconductor chip and forming the second through-electrode and reshuffle the technique of line, all the other techniques are identical with previous embodiment.
Be used for explanation although described specific embodiment of the present invention, one of skill in the art will appreciate that various modifications, interpolation and replacement are feasible, do not depart from thought of the present invention and scope such as the claims definition.
The application requires the priority of the korean patent application No.10-2008-0010470 that submitted on February 1st, 2008 and the korean patent application No.10-2008-103086 that submitted on October 21st, 2008, is incorporated herein by reference in its entirety.
Claims (16)
1. method for preparing wafer level stack package comprises step:
Grinding back surface comprises the lower surface of the wafer of a plurality of the first semiconductor chips, and this first semiconductor chip is wafer scale;
Supporting member is attached to by the lower surface of the wafer of grinding back surface;
One or more the second independent semiconductor chips are stacked on the first corresponding semiconductor chip, wherein plant adhesive or adhesive tape between the adjacent semiconductor chip in the first and second semiconductor chips stacking;
Form the first through-electrode this first semiconductor chip is electrically connected to corresponding one or more the second semiconductor chips;
The 3rd semiconductor chip is attached to each uppermost chip in the second stacking semiconductor chip, and the 3rd semiconductor chip has the second through-electrode that is electrically connected to the first through-electrode and the line of reshuffling that is electrically connected to this second through-electrode;
External connection terminals is connected to the line of reshuffling of the 3rd semiconductor chip; And
Cut the first semiconductor chip of the wafer scale of the second and the 3rd semiconductor chip of stacking correspondence on it, so that this first semiconductor chip is in chip-scale,
Wherein this second semiconductor chip only is stacked on the first semiconductor chip that is confirmed as good dies.
2. the method for claim 1, wherein this supporting member comprises any in glass and the chip carrier.
3. the method for claim 1 also comprises step:
After forming this first through-electrode and before adhering to the 3rd semiconductor chip, remove this supporting member.
4. the method for claim 1 also comprises step:
After connecting this external connection terminals and cutting this first semiconductor chip so that before this first semiconductor chip is in chip-scale, remove this supporting member.
5. the method for claim 1, the step that wherein forms the first through-electrode comprises:
Each first semiconductor chip of etching and be stacked on one or more the second semiconductor chips on each corresponding first semiconductor chip to define the through hole that exposes described supporting member; And
Metallic alloy is filled in each through hole.
6. method as claimed in claim 5, the step of wherein filling metallic alloy comprise inserts metal pins or plating.
7. the method for claim 1, wherein each of this first, second, and third semiconductor chip comprises the semiconductor chip of identical type, each semiconductor chip has identical function.
8. the method for claim 1, wherein each of this first, second, and third semiconductor chip comprises different types of semiconductor chip, each semiconductor chip has different functions.
9. method for preparing wafer level stack package comprises step:
The wafer that comprises a plurality of the first semiconductor chips is provided, and this first semiconductor chip is in wafer scale;
On the first semiconductor chip with the stacking correspondence in this wafer of one or more independent the second semiconductor chips, wherein plant adhesive or adhesive tape between the adjacent semiconductor chip in described the first and second semiconductor chips stacking;
Form the first through-electrode this first semiconductor chip is electrically connected to corresponding one or more the second independent semiconductor chips; And
Cut the first semiconductor chip of the wafer scale of the second independent semiconductor chip of stacking correspondence on it, so that this first semiconductor chip is in chip-scale,
Wherein this second semiconductor chip only is stacked on this first semiconductor chip that is regarded as good dies.
10. method as claimed in claim 9, in the step that forms this first through-electrode with cut and also comprise step between the step of the first semiconductor chip of this wafer scale:
The 3rd semiconductor chip is attached to each uppermost chip of the second stacking semiconductor chip;
In the 3rd accompanying semiconductor chip, form the second through-electrode, so that this second through-electrode is electrically connected to this first through-electrode;
Reshuffle line in the formation of the 3rd semiconductor chip, be electrically connected to this second through-electrode so that this reshuffles line; And
External connection terminals is connected to the line of reshuffling of the 3rd semiconductor chip.
11. method as claimed in claim 10 wherein provides the step of wafer to comprise:
Grinding back surface comprises the lower surface of the wafer of described a plurality of the first semiconductor chips; And
Supporting member is attached to by the lower surface of the wafer of grinding back surface.
12. method as claimed in claim 11 also comprises step:
After forming this first through-electrode and before adhering to the 3rd semiconductor chip, remove this supporting member.
13. method as claimed in claim 11 also comprises step:
After connecting the step of described external connection terminals and cutting this first semiconductor chip so that before this first semiconductor chip is in the step of chip-scale, remove this supporting member.
14. method as claimed in claim 11, the step that wherein forms this first through-electrode comprises:
Each first semiconductor chip of etching and be stacked on one or more the second semiconductor chips on each corresponding first semiconductor chip to define the through hole that exposes described supporting member; And
In each through hole, fill metallic alloy.
15. comprising, method as claimed in claim 14, the step of wherein filling metallic alloy plug metal pins or plating.
16. method as claimed in claim 10, wherein each of this first, second, and third semiconductor chip comprises semiconductor chip or different types of semiconductor chip of identical type, each has identical function the semiconductor chip of this identical type, and each has different functions this different types of semiconductor chip.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20080010470 | 2008-02-01 | ||
| KR10470/08 | 2008-02-01 | ||
| KR103086/08 | 2008-10-21 | ||
| KR1020080103086A KR101013556B1 (en) | 2008-02-01 | 2008-10-21 | Method for fabricating stack package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101499464A CN101499464A (en) | 2009-08-05 |
| CN101499464B true CN101499464B (en) | 2013-01-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100033822A Expired - Fee Related CN101499464B (en) | 2008-02-01 | 2009-01-22 | Method for manufacturing stack package using through-electrodes |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR101013556B1 (en) |
| CN (1) | CN101499464B (en) |
| TW (1) | TW200935580A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101078737B1 (en) | 2009-08-10 | 2011-11-02 | 주식회사 하이닉스반도체 | Stacked semiconductor package |
| TWI405321B (en) * | 2009-09-08 | 2013-08-11 | Ind Tech Res Inst | 3d multi-wafer stacked semiconductor structure and method for manufacturing the same |
| TWI476865B (en) * | 2011-05-25 | 2015-03-11 | Advanced Semiconductor Eng | Method for making stacked semiconductor package |
| KR102258743B1 (en) | 2014-04-30 | 2021-06-02 | 삼성전자주식회사 | Method of fabricating semiconductor package, the semiconductor package formed thereby, and semiconductor device comprising the same |
| CN113314510A (en) * | 2021-07-02 | 2021-08-27 | 西安紫光国芯半导体有限公司 | Stacked chip and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6252300B1 (en) * | 1999-01-14 | 2001-06-26 | United Microelectronics Corp. | Direct contact through hole type wafer structure |
| CN101017786A (en) * | 2006-02-08 | 2007-08-15 | 冲电气工业株式会社 | Manufacturing method of semiconductor package |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6143476A (en) * | 1997-12-12 | 2000-11-07 | Applied Materials Inc | Method for high temperature etching of patterned layers using an organic mask stack |
| KR20020024624A (en) * | 2000-09-26 | 2002-04-01 | 윤종용 | Stack package of chip size level and manufacturing method thereof |
| KR20030050665A (en) * | 2001-12-19 | 2003-06-25 | 삼성전자주식회사 | Stack chip package and manufacturing method thereof |
| KR100842910B1 (en) * | 2006-06-29 | 2008-07-02 | 주식회사 하이닉스반도체 | Stack package |
-
2008
- 2008-10-21 KR KR1020080103086A patent/KR101013556B1/en not_active IP Right Cessation
- 2008-12-12 TW TW097148366A patent/TW200935580A/en unknown
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2009
- 2009-01-22 CN CN2009100033822A patent/CN101499464B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6252300B1 (en) * | 1999-01-14 | 2001-06-26 | United Microelectronics Corp. | Direct contact through hole type wafer structure |
| CN101017786A (en) * | 2006-02-08 | 2007-08-15 | 冲电气工业株式会社 | Manufacturing method of semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101499464A (en) | 2009-08-05 |
| KR20090084645A (en) | 2009-08-05 |
| KR101013556B1 (en) | 2011-02-14 |
| TW200935580A (en) | 2009-08-16 |
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