CN101499405A - Method for producing single-layer polysilicon gate non-volatile memory - Google Patents
Method for producing single-layer polysilicon gate non-volatile memory Download PDFInfo
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- CN101499405A CN101499405A CNA2008100333644A CN200810033364A CN101499405A CN 101499405 A CN101499405 A CN 101499405A CN A2008100333644 A CNA2008100333644 A CN A2008100333644A CN 200810033364 A CN200810033364 A CN 200810033364A CN 101499405 A CN101499405 A CN 101499405A
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Abstract
The invention relates to a method for improving the performance of a single-layer polysilicon gate nonvolatile memory. By changing the materials of an SAB (Salicide-Block) layer, the number of positive movable ions entering the floating gate of a single-layer polysilicon gate nonvolatile memory unit can be decreased, so the charge retention of a storage unit is enhanced.
Description
Technical field
The present invention relates to a kind of method that is used to prepare single-layer polysilicon gate non-volatile memory.
Background technology
The principal character of non-volatility memorizer technology is to be extensive use of the floating boom unit, as EEPROM.According to grid structure difference, the floating boom unit can be divided into two classes, a kind of is so-called stacking gate (being the double-layered polycrystal Si-gate) structure, as shown in Figure 1, comprising: P type silicon substrate 11, P-trap 12, shallow-trench isolation 13, grid oxic horizon 14, floating boom 15, internal layer separator 16, control gate 17 are stacked and placed on floating boom 15 tops; The single-layer polysilicon gate structure as shown in Figure 2, comprising: P type silicon substrate 21, P-trap 22, N-trap 23, shallow-trench isolation 24, grid oxic horizon 25, floating boom 26 and highly doped contact zone 27.In the single-layer polysilicon gate memory cell, N-trap 23 has played the effect of control gate.
This single-layer polysilicon gate non-volatile memory cell structure, advantage with respect to described double-layered polycrystal Si-gate memory cell is that it and existing processes technology are complementary, do not need other processing step just can finish together, reduced process complexity with other circuit.
For memory, the charge storage performance is most important for the reliability of memory.Fig. 3 is the change curve of the floating boom voltage Vt of described single-layer polysilicon gate non-volatile memory cell with the testing time, as shown in Figure 3, after programming finishes for the first time, described voltage Vt reaches maximum voltage value, and room temperature was placed after 30 minutes, and described voltage Vt descends rapidly, then memory cell is carried out the programming second time, make described voltage Vt reach maximum once more, room temperature was placed after 30 minutes, and described voltage Vt decrease speed tends towards stability.This phenomenon illustrates that described single-layer polysilicon gate non-volatile charge storing unit memory property and mobile ion are closely related.
Described single-layer polysilicon gate memory just is that with respect to the shortcoming of described double-layered polycrystal Si-gate memory the charge storage performance of described single-layer polysilicon gate memory is poor, be that positive mobile ion concentration ratio is higher in the Si-gate, how address this problem for the application of described single-layer polysilicon gate non-volatile memory most important.
Fig. 4 has disclosed the main cause of introducing positive mobile ion in the single-layer polysilicon gate non-volatile memory cell.Curve a is not for carrying out the floating boom voltage Vt of the memory cell under salicide (metal silication) technology along with the change curve of time after floating boom growth, curve b is for carrying out the change curve of the floating boom voltage Vt of the memory cell under the salicide technology along with the time after the floating boom growth.Therefrom as can be seen, salicide technology has caused the decline of charge storing unit memory property, can judge that the positive mobile ion major part in the memory cell is introduced by salicide technology.Usually the silication of adopting stops (Salicide-Block; be abbreviated as SAB; other parts of specification use the silication of abbreviation SAB acute pyogenic infection of finger tip to stop) layer is not enough to stop that the described positive mobile ion that salicide technology is introduced enters floating boom; and the described positive mobile ion of part can be penetrated into metal silicide protective material lower floor by the SAB layer in rapid thermal treatment process, forms metal silicide with polysilicon.
Summary of the invention
The present invention relates to a kind of method that is used to prepare single-layer polysilicon gate non-volatile memory, be with the difference of existing preparation technology, selected the oxygen enrichment silicon (Silicon-Rich-Oxide that replaces prior art to use with compatible mutually material of technological requirement and growth pattern thereof for use, be abbreviated as SRO, other parts use abbreviations of specification SRO acute pyogenic infection of finger tip oxygen enrichment silicon) material and growth pattern thereof are used as the SAB layer, and other step for preparing described single-layer polysilicon gate non-volatile memory is constant.
According to a kind of method that is used to prepare single-layer polysilicon gate non-volatile memory of the present invention, it is characterized in that, with comprising that single or multiple lift is through low-pressure chemical vapor phase deposition tetraethoxysilane (Tetraethyl Orthosilicate, be abbreviated as TEOS, the rete that uses low pressure chemical deposit TEOS to generate is called Low Pressure Chemical Vapor Deposition from TEOS, be abbreviated as LPTEOS, other parts of specification are used abbreviation TEOS acute pyogenic infection of finger tip tetraethoxysilane, the rete that uses abbreviation LPTEOS rete acute pyogenic infection of finger tip to generate with low pressure chemical deposit TEOS) rete that generates is as suicide block.
Compared with prior art, the present invention has the following advantages: because the density of LPTEOS rete will be higher than described sro film layer, so replace described sro film layer with the material that comprises single or multiple lift LPTEOS rete, as the SAB layer that relates in the preparation single-layer polysilicon gate non-volatile memory process, can further reduce because silicification technics is incorporated into the positive mobile ion on the floating boom, thereby improved described single-layer polysilicon gate non-volatile charge storing unit memory property, and the temperature that described LPTEOS rete generates is moderate, can not influence the structure and the performance of layer device down.
Owing to only changed the component of SAB layer, the present invention is suitable for for the manufacturing that has the single level polysilicon grid Nonvolatile storage unit under the technology now.
Description of drawings
Fig. 1 is the schematic cross-section of the double-layered polycrystal Si-gate EPROM of prior art;
Fig. 2 is the schematic cross-section of the single-layer polysilicon gate EPROM of prior art;
Fig. 3 is the change curve of the floating boom voltage Vt of single-layer polysilicon gate non-volatile memory cell with the testing time;
Fig. 4 carries out silicification technics and does not carry out under two kinds of situations of silicification technics, and floating boom voltage Vt is with the change curve of testing time;
Fig. 5 is to use ageing test result's (floating boom voltage Vt is with the change curve of testing time and probe temperature) of the single-layer polysilicon gate non-volatile memory cell of making under the situation of different materials as the SAB layer.
Embodiment
The present invention is described in detail below in conjunction with drawings and Examples.
Under 0.18 μ m standard CMOS process, the method that is used to prepare single-layer polysilicon gate non-volatile memory that application the present invention relates to, promptly in making the single-layer polysilicon gate memory cell, use the material that comprises single or multiple lift LPTEOS rete as the SAB layer, and made the contrast ageing test as the single-layer polysilicon gate memory cell of SAB layer manufacturing with the sro film layer that uses prior art to use.
[embodiment 1]
Use identical prior art to finish (comprising the employed material of art methods and prior art) part-structure of single-layer polysilicon gate memory cell, comprise the steps:
1 forms isolated area on P type silicon substrate;
2 photoetching form the N-trap pattern as control gate, and carry out N-trap ion and inject;
3 form grid oxic horizon and undoped polycrystalline silicon grid successively;
4 carry out lightly doped drain (LDD) injects;
5 form grid side protective layer;
6 form contact hole.
Afterwards, use the method for low-pressure vapor phase chemical deposition (method of low-pressure chemical vapor phase deposition is identical with the growing method of LPTEOS rete in the prior art) TEOS herein, growth
The LPTEOS rete of thickness is as the SAB layer, replaces available technology adopting
The sro film layer of thickness is as the SAB layer.And the SAB layer that is generated carried out etching (method with prior art etching LPTEOS rete is identical), obtain the SAB layer pattern that needs.
Then, the manufacturing of finishing whole single-layer polysilicon gate memory cell remaining part by the step and the method for prior art.
Purport of the present invention is to change the material of the SAB layer that relates in the storage of single-layer polysilicon gate in the prior art manufacture process, does not specify so all the other of whole manufacturing process step same as the prior art and specific implementation method are not done herein.
With resulting single-layer polysilicon gate memory cell and use
Thick sro film layer carries out ageing test as the produced single-layer polysilicon gate memory cell of SAB layer (use prior art manufacturing) under similarity condition, result of the test as shown in Figure 5:
At first memory cell is carried out ultraviolet erasing (uv wipes), then memory cell is programmed, make the floating boom voltage Vt of memory cell reach maximum, the process ageing test is (with reference to figure 5, kept 1 hour under the room temperature before this, 250 ℃ kept 96 hours down then), use the loss speed (reference curve d) of the floating boom voltage Vt of the single-layer polysilicon gate memory cell that described LPTEOS rete obtains as the SAB layer to be far smaller than and use described sro film layer as the produced single-layer polysilicon gate memory cell of SAB layer (reference curve c).
Correlation curve c and curve d can see, use described LPTEOS rete can effectively improve single-layer polysilicon gate charge storing unit memory property.The thickness of described LPTEOS rete should specifically be controlled according to the requirement of technology, is generally
When described LPTEOS thicknesses of layers less than
After, limited for the raising of charge storage performance, described LPTEOS rete should approach on the basis that can realize effectively positive mobile ion control as far as possible.
[embodiment 2]
In the present embodiment, after the described step 6 in described embodiment 1, use following method to make the SAB layer:
At first, use the method for low-pressure vapor phase chemical deposition (method of low-pressure chemical vapor phase deposition is identical with the growing method of LPTEOS rete in the prior art) herein, growth
The first low-pressure chemical vapor phase deposition tetraethoxysilane rete (also can be called a LPTEOS rete) of thickness; Then, the method growth by low-pressure vapor phase chemical deposition (method with low-pressure chemical vapor phase deposition method grown silicon nitride rete is identical in the method for low-pressure chemical vapor phase deposition and the prior art) herein
The silicon nitride film layer of thickness; At last, use the method for low-pressure vapor phase chemical deposition (method of low-pressure chemical vapor phase deposition is identical with the growing method of LPTEOS rete in the prior art) herein, growth
The second low-pressure chemical vapor phase deposition tetraethoxysilane rete (also can be called the 2nd LPTEOS rete) of thickness.Use this LPTEOS-SiN-LPTEOS layer to replace available technology adopting
The sro film layer of thickness is as the SAB layer.And the LPTEOS-SiN-LPTEOS layer that is generated is carried out etching (method of the silicon nitride film layer that lithographic method generates for the existing described LPTEOS rete of etching and described low-pressure vapor phase chemical deposition does not do specifying herein) obtain the SAB layer pattern that needs.
Then, the manufacturing of finishing whole single-layer polysilicon gate memory cell remaining part by the step and the method for prior art.
Purport of the present invention is to change SAB layer of the prior art, does not specify so all the other of whole manufacturing process step same as the prior art and specific implementation method are not done herein.
When making described LPTEOS-SiN-LPTEOS layer, the thickness of each layer can be selected within the specific limits, and the described first low-pressure chemical vapor phase deposition tetraethoxysilane thicknesses of layers range of choice is
, described silicon nitride film layer thickness range of choice is
, the range of choice of the described second low-pressure chemical vapor phase deposition tetraethoxysilane thicknesses of layers is
The thickness of each rete is unsuitable blocked up, and blocked up meeting influence superstructure; Each rete also should not be thin excessively, crosses to approach and can not play the positive mobile ion that stops that effectively salicide technology is introduced.
Resulting single-layer polysilicon gate memory cell is carried out ageing test (test method is identical with the test method among the embodiment 1) with using described sro film layer as the produced single-layer polysilicon gate memory cell of SAB layer (using the prior art manufacturing) under similarity condition, result of the test as shown in Figure 5:
Correlation curve c and curve e, as can be seen, use the LPTEOS-SiN-LPTEOS layer can effectively improve single-layer polysilicon gate charge storing unit memory property as SAB layer (corresponding curve e), its performance is than also good as the single-layer polysilicon gate charge storing unit memory property of SAB layer manufacturing with described LPTEOS rete among the embodiment 1, which kind of but, can select with material as the SAB layer according to specific requirement owing to used three-decker on process complexity and cost, to be improved as the SAB layer.
Claims (5)
1. a method that is used to prepare single-layer polysilicon gate non-volatile memory is characterized in that, with comprising that rete that single or multiple lift generates through the low-pressure chemical vapor phase deposition tetraethoxysilane is as suicide block.
2. method according to claim 1 is characterized in that, the rete that generates through the low-pressure chemical vapor phase deposition tetraethoxysilane is as described suicide block.
3. method according to claim 2 is characterized in that, described suicide block thickness is
4. method according to claim 1, it is characterized in that, described suicide block comprises the first low-pressure chemical vapor phase deposition tetraethoxysilane rete, silicon nitride film layer and the second low-pressure chemical vapor phase deposition tetraethoxysilane rete, and wherein, the step of described deposit suicide block comprises:
-generate the described first low-pressure chemical vapor phase deposition tetraethoxysilane rete through the low-pressure chemical vapor phase deposition tetraethoxysilane;
-described the silicon nitride film layer of usefulness low-pressure chemical vapor phase deposition on the described first low-pressure chemical vapor phase deposition tetraethoxysilane rete;
-on described silicon nitride film layer, generate the described second low-pressure chemical vapor phase deposition tetraethoxysilane rete through the low-pressure chemical vapor phase deposition tetraethoxysilane.
5. method according to claim 4 is characterized in that, the described first low-pressure chemical vapor phase deposition tetraethoxysilane thicknesses of layers is
Described silicon nitride film layer thickness is
The described second low-pressure chemical vapor phase deposition tetraethoxysilane thicknesses of layers is
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102930981A (en) * | 2011-08-12 | 2013-02-13 | 无锡华润上华半导体有限公司 | Capacitor and manufacturing method for same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102930981A (en) * | 2011-08-12 | 2013-02-13 | 无锡华润上华半导体有限公司 | Capacitor and manufacturing method for same |
| CN102930981B (en) * | 2011-08-12 | 2015-08-19 | 无锡华润上华半导体有限公司 | A kind of electric capacity and preparation method thereof |
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