CN101494194A - Integrated circuit and formation method thereof, electrostatic discharge protection circuit - Google Patents
Integrated circuit and formation method thereof, electrostatic discharge protection circuit Download PDFInfo
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- CN101494194A CN101494194A CNA200810008549XA CN200810008549A CN101494194A CN 101494194 A CN101494194 A CN 101494194A CN A200810008549X A CNA200810008549X A CN A200810008549XA CN 200810008549 A CN200810008549 A CN 200810008549A CN 101494194 A CN101494194 A CN 101494194A
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Abstract
The invention discloses an integrated circuit capable of saving layout area and a forming method thereof. The integrated circuit comprises a diffusion layer, a first polysilicon layer and a second polysilicon layer. The first polysilicon layer is arranged above the diffusion layer to form a transistor. The second polysilicon layer comprises a first section and a second section. The first section of the second polysilicon layer is arranged above the first polysilicon layer to form a capacitance and the second section of the second polysilicon layer is arranged above the diffusion layer to form a resistance. The invention also discloses an electrostatic discharge protection circuit that can save layout area.
Description
Technical field
The present invention relates to a kind of layout of integrated circuit, refer to a kind of integrated circuit of saving layout area and forming method thereof and a kind of ESD protection circuit especially.
Background technology
Along with the semiconductor integrated circuit size of component continues to dwindle, in the manufacturing technology of the CMOS transistor (CMOS) of deep-submicron (deep submicron), not only channel length (channel length) need be shortened, grid oxic horizon (gate oxide layer) must be thinner, and junction depth (junction depth) shoals, the implantation concentration (dopant concentration) of trap (well) also must be raised simultaneously.But above-mentioned technology but often makes the easier infringement that suffers Electrostatic Discharge of integrated circuit; therefore the more effective esd protection circuit of essential adding in the chip discharges the ESD electric current, avoids the infringement of ESD with the protection integrated circuit; in other words, promptly increase the ESD tolerance of integrated circuit.Desire to produce effective esd protection circuit, at first must be with the esd protection circuit that is fit to, design is in integrated circuit.Secondly,, discharge the ESD path of current to increase by increasing the area of esd protection circuit, also be a kind of directly and effective method.Yet, when increasing the area of esd protection circuit, but must consider to take too many chip area (chip area), otherwise will run counter to the principle of as far as possible dwindling chip size.
Please refer to Fig. 1, Fig. 1 is the schematic diagram of the esd protection circuit of prior art.Esd protection circuit 10 comprises P-type mos (PMOS) field-effect transistor 12, resistance 14 and electric capacity 16.Resistance 14 is coupled between the grid and source electrode of transistor 12, and electric capacity 16 is coupled between the grid and drain electrode of transistor 12, and resistance 14 and electric capacity 16 form resistance-capacitance network (RC network).The source electrode of transistor 12 is coupled to power end, and the drain electrode of transistor 12 is coupled to earth terminal.When the static waveform occurs in this power end, because this resistance-capacitance network can make signal produce late effect, therefore the speed of the voltage of node V1 rising can be slow than this power end, therefore form potential difference at node V1 and this power end, at this moment, identical potential difference appears between transistor 12 and this power end.When this potential difference during greater than the threshold voltage (threshold voltage) of transistor 12, transistor 12 promptly can conducting.Therefore esd protection circuit 10 just can provide the ESD current path, in order to avoid electric current flows into internal circuit and causes damage during static discharge.In addition, also can utilize N type metal oxide semiconductor (NMOS) transistor to form esd protection circuit, the esd protection circuit that its mode of operation and PMOS transistor are formed is similar.
Please refer to Fig. 2 and Fig. 3, Fig. 2 is the schematic diagram of the first previous case of the layout (layout) of the esd protection circuit of Fig. 1, and Fig. 3 is the schematic diagram of the second previous case of layout of the esd protection circuit of Fig. 2.As shown in Figure 2, transistor 12 forms on diffusion layer 22 by first polysilicon layer 24 is set, and electric capacity 14 forms on first polysilicon layer 24 by second polysilicon layer 26 is set, and resistance 16 forms by second polysilicon layer 26.According to semiconductor technology, diffusion layer 22, first polysilicon layer 24 and second polysilicon layer 26 are all conducting shell, completely cut off by oxide layer between each conducting shell, so each conducting shell need to connect by contact hole 28.In addition, have usually around the esd protection circuit 10 and pick up ring (pickup ring), picking up ring is to utilize diffusion layer 22 to form.Because esd protection circuit 10 needs to discharge bigger electric current, can form transistor 12 by many first polysilicon layers 24, connect each bar first polysilicon layer 24 by metal level (figure does not show) again.In Fig. 2, transistor 12 is formed by two first polysilicon layers 24, and 16 needs of this external resistance 14 and electric capacity are disposed at another space, therefore utilizes to pick up to encircle to cross two zones, a zone is used for disposing transistor 12, and another zone then is used for disposing resistance 14 and electric capacity 16.In Fig. 3,12 in transistor is formed by eight first polysilicon layers 24, similarly, utilizes to pick up to encircle to cross two zones, and a zone is used for disposing transistor 12, and another zone then is used for disposing resistance 14 and electric capacity 16.
In sum, when the process of integrated circuit (IC) products dwindles gradually, make the infringement of the easier ESD of suffering of integrated circuit also.Desire increases the ESD tolerance of integrated circuit (IC) products, and the area that strengthens esd protection circuit is a kind of simple and direct method, but the result that often can cause layout area to increase again seriously reduces integrated level (integration).
Summary of the invention
Therefore, a purpose of the present invention is to provide a kind of integrated circuit of saving layout area and forming method thereof, to solve the above problems.
The invention provides a kind of formation and can save the method for the integrated circuit of layout area, comprise: the top of first polysilicon layer in diffusion layer is set, to form transistor; The top of second polysilicon layer in this first polysilicon layer is set, to form electric capacity; And this second polysilicon layer is arranged at the top of this diffusion layer, to form resistance.
The present invention provides a kind of integrated circuit of saving layout area in addition, comprises: diffusion layer; First polysilicon layer is arranged at the top of this diffusion layer, to form transistor; And second polysilicon layer, comprise: first section is arranged at the top of this first polysilicon layer, to form electric capacity; Reach second section, be arranged at the top of this diffusion layer, to form resistance.
The present invention provides a kind of ESD protection circuit of saving layout area in addition, comprises: transistor forms in the top of diffusion layer by first polysilicon layer is set; Electric capacity is coupled between this transistorized grid and the drain electrode, and this electric capacity forms in the top of this first polysilicon layer by second polysilicon layer is set; And resistance, being coupled between this transistorized grid and the source electrode, this resistance forms in the top of this diffusion layer by this second polysilicon layer is set.
Description of drawings
Fig. 1 is the schematic diagram of the esd protection circuit of prior art.
Fig. 2 is the schematic diagram of first embodiment of layout of the esd protection circuit of Fig. 1.
Fig. 3 is the schematic diagram of second embodiment of layout of the esd protection circuit of Fig. 1.
Fig. 4 is the schematic diagram of first embodiment of the layout of esd protection circuit of the present invention.
Fig. 5 is the schematic diagram of second embodiment of the layout of esd protection circuit of the present invention.
Description of reference numerals
10ESD protective circuit 12 transistors
14 resistance, 16 electric capacity
22 diffusion layers, 24 first polysilicon layers
26 second polysilicon layers, 28 contact holes
261 first sections, 262 second sections
Embodiment
For the integrated circuit with transistor, electric capacity and resistance, the present invention utilizes transistorized layout (layout) space, adds the layout of electric capacity and resistance, therefore can save the layout area of integrated circuit.In an embodiment of the present invention, explain, yet the present invention also is applicable to the integrated circuit that comprises transistor, electric capacity and resistance with the Electrostatic Discharge protective circuit.The method according to this invention at first, is provided with the top of first polysilicon layer in diffusion layer, to form transistor.Secondly, the top of second polysilicon layer in this first polysilicon layer is set,, just utilizes the arrangement space of this transistorized grid to form this electric capacity to form electric capacity.At last, this second polysilicon layer is arranged at the top of this diffusion layer,, just utilizes the arrangement space of this transistorized active area (active region) to form this resistance to form resistance.Therefore, integrated circuit of the present invention comprises this diffusion layer, this first polysilicon layer and this second polysilicon layer, wherein, the top that this first polysilicon layer is arranged at this diffusion layer forms this transistor, this second polysilicon layer comprises first section and second section, the top that first section of this second polysilicon layer is arranged at this first polysilicon layer forms this electric capacity, and the top that second section of this second polysilicon layer is arranged at this diffusion layer forms this resistance.
Please refer to Fig. 4, Fig. 4 is the schematic diagram of first embodiment of the layout of esd protection circuit of the present invention.The equivalent circuit diagram of Fig. 4 as shown in Figure 1.Transistor 12 forms in the top of diffusion layer 22 by first polysilicon layer 24 is set.Electric capacity 14 is coupled between the grid and drain electrode of transistor 12, forms in the top of first polysilicon layer 24 by second polysilicon layer 26 is set.Resistance 16 is coupled between the grid and source electrode of transistor 12, forms in the top of diffusion layer 22 by second polysilicon layer 24 is set.According to semiconductor technology, diffusion layer 22, first polysilicon layer 24 and second polysilicon layer 26 are all conducting shell, completely cut off by oxide layer between each conducting shell, so each conducting shell need to connect by contact hole 28.In addition, have usually around the esd protection circuit 10 and pick up ring (pickup ring), picking up ring is to utilize diffusion layer 22 to form.Because esd protection circuit 10 needs to discharge bigger electric current, can form transistor 12 by many first polysilicon layers 24, connect each bar first polysilicon layer 24 by metal level (figure does not show) again.In the present embodiment, transistor 12 is formed by two first polysilicon layers 24.Second section 262 that first section 261 that second polysilicon layer 26 comprises first section 261 and second section, 262, the second polysilicon layers 26 is used for forming electric capacity 16, the second polysilicons 26 is used for forming resistance 14.In order to add the capacitance that increases electric capacity 16, first polysilicon layer 24 is arranged at the top of diffusion layer 22 and extends to diffusion layer 22 and pick up zone between the ring, and first section 261 of second polysilicon 26 then covers the first whole polysilicon layers 24.So, the capacitance that can produce electric capacity 16 is 970.64pF, and 14 the resistance value of can having a resistance is 2544 Ω.
In the semiconductor technology of dual poly layer, the bottom crown relation is gone up in first polysilicon layer 24 and 26 formation of second polysilicon layer promptly becomes electric capacity 16, so electric capacity 16 is arranged at the grid top of transistor 12.In addition; because esd protection circuit 10 has the ring of picking up; and the distance of picking up between the active area of ring and transistor 12 is also bigger than the minimum widith of polysilicon layer; so can utilize the zone of picking up between ring and the transistorized active area to increase the capacitance of electric capacity 16, and can not influence the characteristic of transistor 12.Moreover the drain electrode and the distance between the grid of the transistor 12 of esd protection circuit 10 are bigger usually, therefore utilize this space that the layout of resistance 14 is set.In order to illustrate that the present invention can save the characteristics of layout area, for the esd protection circuit 10 of Fig. 1, the layout of comparison diagram 2 prior arts and the size of Fig. 4 layout of the present invention.In Fig. 2 and Fig. 4, transistor 12 utilizes two first polysilicon layers 24 to form transistor 12 equally, and the layout area of Fig. 2 is 71.55 μ m*23 μ m=1645.65 μ m
2, the layout area of Fig. 4 is 43.9 μ m*31.9 μ m=1400.41 μ m
2, therefore, the layout of Fig. 4 has been saved 14.90% space than the layout of Fig. 2.
Please refer to Fig. 5, Fig. 5 is the schematic diagram of second embodiment of the layout of esd protection circuit of the present invention.In the present embodiment, transistor 12 is formed by eight first polysilicon layers 24, and second section 262 that first section 261 of second polysilicon layer 26 is used for forming electric capacity 16, the second polysilicons 26 is used for forming resistance 14.For the esd protection circuit 10 of Fig. 1, the layout of comparison diagram 3 prior arts and the size of Fig. 5 layout of the present invention.In Fig. 3 and Fig. 5, transistor 12 utilizes eight first polysilicon layers 24 to form transistor 12 equally, and the layout area of Fig. 3 is 69.0 μ m*61.7 μ m=4257.30 μ m
2, the layout area of Fig. 5 is 77.9 μ m*44.3 μ m=3450.97 μ m
2, therefore, the layout of Fig. 5 has been saved 18.93% space than the layout of Fig. 3.
In sum, the present invention utilizes transistorized arrangement space, adds the layout of electric capacity and resistance, therefore can save the layout area of integrated circuit.With the esd protection circuit is example, and esd protection circuit comprises transistor, electric capacity and resistance, utilizes the arrangement space of this transistorized grid to form this electric capacity, and utilizes the arrangement space of this transistorized active area to form this resistance.Therefore, according to the present invention, integrated circuit comprises diffusion layer, first polysilicon layer and second polysilicon layer.The top that this first polysilicon layer is arranged at this diffusion layer forms transistor, this second polysilicon layer comprises first section and second section, the top that first section of this second polysilicon layer is arranged at this first polysilicon layer forms electric capacity, and the top that second section of this second polysilicon layer is arranged at this diffusion layer forms resistance.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (17)
1. method that formation can be saved the integrated circuit of layout area comprises:
The top of first polysilicon layer in diffusion layer is set, to form transistor;
The top of second polysilicon layer in this first polysilicon layer is set, to form electric capacity; And
This second polysilicon layer is arranged at the top of this diffusion layer, to form resistance.
2. the method for claim 1, other comprises:
Setting is picked up and is encircled around this diffusion layer;
This first polysilicon layer is extended to this diffusion layer and this pick up zone between the ring; And
This second polysilicon layer is covered this whole first polysilicon layers, to increase the capacitance of this electric capacity.
3. the method for claim 1, other comprises:
This electric capacity is coupled between this transistorized grid and the drain electrode; And
This resistance is coupled between this transistorized grid and the source electrode to form ESD protection circuit.
4. the method for claim 1 wherein is provided with this second polysilicon layer in the top of this first polysilicon layer, is that the top of this second polysilicon layer in this first polysilicon layer that forms this transistorized grid is set to form this electric capacity, to form this electric capacity.
5. the method for claim 1 wherein is arranged at this second polysilicon layer the top of this diffusion layer, is the top that this second polysilicon layer is arranged at this diffusion layer that forms this transistorized active area to form this resistance, to form this resistance.
6. the integrated circuit that can save layout area comprises:
Diffusion layer;
First polysilicon layer is arranged at the top of this diffusion layer, to form transistor; And
Second polysilicon layer comprises:
First section is arranged at the top of this first polysilicon layer, to form electric capacity; And
Second section is arranged at the top of this diffusion layer, to form resistance.
7. integrated circuit as claimed in claim 6, other comprises:
Pick up ring, be arranged at this diffusion layer around.
8. integrated circuit as claimed in claim 7, wherein this first polysilicon layer is arranged at the top of this diffusion layer and extends to this diffusion layer and this picks up zone between the ring.
9. integrated circuit as claimed in claim 8, wherein first section of this second polysilicon is arranged at the top of this first polysilicon layer and covers this whole first polysilicon layers.
10. integrated circuit as claimed in claim 6, wherein this electric capacity is coupled between this transistorized grid and the drain electrode, and this resistance is coupled between this transistorized grid and the source electrode, and this integrated circuit is an ESD protection circuit.
11. integrated circuit as claimed in claim 6, wherein first section of this second polysilicon layer is arranged at the zone of this transistorized grid.
12. integrated circuit as claimed in claim 6, wherein second section of this second polysilicon layer is arranged at the zone of this transistorized active area.
13. the ESD protection circuit that can save layout area comprises:
Transistor forms in the top of diffusion layer by first polysilicon layer is set;
Electric capacity is coupled between this transistorized grid and the drain electrode, and this electric capacity forms in the top of this first polysilicon layer by second polysilicon layer is set; And
Resistance is coupled between this transistorized grid and the source electrode, and this resistance forms in the top of this diffusion layer by this second polysilicon layer is set.
14. ESD protection circuit as claimed in claim 13, other comprises:
Pick up ring, be arranged at this transistorized diffusion layer around.
15. ESD protection circuit as claimed in claim 13, wherein second polysilicon layer of this electric capacity and first polysilicon layer extend to this transistorized diffusion layer and this and pick up zone between the ring.
16. ESD protection circuit as claimed in claim 13, wherein this electric capacity is arranged at the zone of this transistorized grid.
17. ESD protection circuit as claimed in claim 13, wherein this resistance is arranged at the zone of this transistorized active area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200810008549XA CN101494194A (en) | 2008-01-23 | 2008-01-23 | Integrated circuit and formation method thereof, electrostatic discharge protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA200810008549XA CN101494194A (en) | 2008-01-23 | 2008-01-23 | Integrated circuit and formation method thereof, electrostatic discharge protection circuit |
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| CN101494194A true CN101494194A (en) | 2009-07-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNA200810008549XA Pending CN101494194A (en) | 2008-01-23 | 2008-01-23 | Integrated circuit and formation method thereof, electrostatic discharge protection circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064795A (en) * | 2010-12-23 | 2011-05-18 | 北京海尔集成电路设计有限公司 | Integrated circuit layout method for offset cancelling circuit |
| CN103035624A (en) * | 2012-12-14 | 2013-04-10 | 广东风华芯电科技股份有限公司 | Electrostatic protection device and chip thereof |
| CN103646947A (en) * | 2013-11-29 | 2014-03-19 | 无锡中星微电子有限公司 | A three-dimensional integrated circuit in a planar process and a method for manufacturing the same |
| US10270134B2 (en) | 2013-05-23 | 2019-04-23 | Lg Chem, Ltd. | Method of manufacturing electrode assembly |
-
2008
- 2008-01-23 CN CNA200810008549XA patent/CN101494194A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064795A (en) * | 2010-12-23 | 2011-05-18 | 北京海尔集成电路设计有限公司 | Integrated circuit layout method for offset cancelling circuit |
| CN102064795B (en) * | 2010-12-23 | 2013-09-11 | 北京海尔集成电路设计有限公司 | Integrated circuit layout method for offset cancelling circuit |
| CN103035624A (en) * | 2012-12-14 | 2013-04-10 | 广东风华芯电科技股份有限公司 | Electrostatic protection device and chip thereof |
| US10270134B2 (en) | 2013-05-23 | 2019-04-23 | Lg Chem, Ltd. | Method of manufacturing electrode assembly |
| CN103646947A (en) * | 2013-11-29 | 2014-03-19 | 无锡中星微电子有限公司 | A three-dimensional integrated circuit in a planar process and a method for manufacturing the same |
| CN103646947B (en) * | 2013-11-29 | 2016-05-04 | 无锡中感微电子股份有限公司 | Three dimensional integrated circuits under planar technology and manufacture method thereof |
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Application publication date: 20090729 |