CN101490996A - Apparatus for transmitting multiple CDMA channels - Google Patents
Apparatus for transmitting multiple CDMA channels Download PDFInfo
- Publication number
- CN101490996A CN101490996A CNA2007800265068A CN200780026506A CN101490996A CN 101490996 A CN101490996 A CN 101490996A CN A2007800265068 A CNA2007800265068 A CN A2007800265068A CN 200780026506 A CN200780026506 A CN 200780026506A CN 101490996 A CN101490996 A CN 101490996A
- Authority
- CN
- China
- Prior art keywords
- frequency channels
- sampling
- frequency
- channel
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Transmitters (AREA)
Abstract
A multi-carrier transmitter capable of transmitting on one or multiple frequency channels simultaneously is described. In one design, the multi-carrier transmitter includes at least one processor and a single radio frequency (RF) transmission chain. The processor(s) may generate output chips for each of multiple frequency channels, digitally filter and upsample the output chips for each frequency channel to obtain filtered samples, and digitally upconvert the filtered samples for each frequency channel to a different frequency to obtain upconverted samples. The processor(s) may then combine the upconverted samples for the multiple frequency channels to obtain composite samples, perform pre-distortion on the composite samples for I/Q mismatch compensation, and upsample the pre-distorted samples to obtain output samples. The output samples may be converted to an analog signal with a wideband DAC. The RF transmit chain may process the analog signal to generate an RF output signal.
Description
Related application
The title that present patent application requires on July 14th, 2006 to submit to is the provisional application No.60/831 of " MODULATION OFMULTIPLE DATA CHANNELS WITH A SINGLE RF TRANSMIT CHAIN ", 044 priority, this provisional application has transferred the application's assignee, and incorporates it into this paper clearly with way of reference.
Technical field
The disclosed content of the application relates generally to communication, relates in particular to the transmitter in the wireless communication system.
Background technology
Wireless communication system is disposed widely so that various communication services such as voice, video, grouped data, message, broadcasting etc. to be provided.These systems can support a plurality of users' multi-address system by sharing free system resources, and the example of these multi-address systems comprises code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, OFDM (OFDMA) system and single-carrier frequency division multiple access (SC-FDMA) system.
Number of users that increases and the appearance with new application of higher demand data all make the data in the wireless communication system use sustainable growth.System can support a specific maximum data rate on a frequency channels with good channel conditions, this maximum data rate is typically determined by system design.System can use a plurality of frequency channels to transmit, with the increase capacity.Yet in order to be supported in the transmission on a plurality of frequency channels, the design complexities of transmitter and cost may significantly increase.
Therefore need in the art a kind ofly can be supported in the cost-effective transmitter of operating on a plurality of frequency channels.
Summary of the invention
This paper has described a kind of multicarrier transmitter, and it can be launched on one or more frequency channels by using an independent radio frequency (RF) emission chain simultaneously.This independent radio-frequency transmissions chain can be the broadband, and is designed for the individual frequency channels of specific maximum number (T).By using this independent radio-frequency transmissions chain, can nearly launch nearly T signal simultaneously on T frequency channels.
In a design, multicarrier transmitter comprises at least one processor and a radio-frequency transmissions chain.This processor can be according to specific system, and for example High Rate Packet Data (HRPD) system is each the generation output chip in a plurality of frequency channels.The output chip of each frequency channels can be with based on the transmitting power of this frequency channels and convergent-divergent is carried out in the gain of selecting.This processor can carry out digital filtering and up-sampling to the output chip of each frequency channels obtaining filtered sampling, and can each frequency channels of Digital Up Convert filteredly sample a different frequency to obtain the sampling after the up-conversion.This processor can make up sampling after the up-conversion of a plurality of frequency channels to obtain compound sampling, this compound sampling is carried out predistortion with gain and phase mismatch in the compensation simulation quadrature up-conversion subsequently, and the sampling of this predistortion is carried out up-sampling to obtain the output sampling.Can should export sample conversion with broadband digital to analog converter (DAC) and become analog signal.Then, this radio-frequency transmissions chain can be handled (for example filtering, quadrature up-conversion and amplification) this analog signal to generate the radio frequency output signal.
Various aspects of the present invention and feature will describe in further detail hereinafter.
Description of drawings
Fig. 1 shows CDMA signal transmitted on a plurality of CDMA Channel;
Fig. 2 shows the block diagram of multicarrier transmitter;
Fig. 3 shows the processing procedure of not having the feedback multiplexing modes in HRPD;
Fig. 4 shows the processing procedure of basic feedback multiplexing modes in HRPD;
Fig. 5 shows the processing procedure that strengthens the feedback multiplexing modes in HRPD;
Fig. 6 shows the data processor that is used for all three feedbacks of HRPD multiplexing modes;
Fig. 7 shows the block diagram of CDMA Channel processor among Fig. 6;
Fig. 8 shows the block diagram of digital filter and circulator;
Fig. 9 shows the block diagram of preprocessor;
Figure 10 shows the processing procedure of launching on a plurality of frequency channels;
Figure 11 shows the processing procedure that the radio-frequency transmissions chain is carried out.
Embodiment
Multicarrier transmitter described herein can be used for various wireless communication systems, for example code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, OFDM (OFDMA) system and single-carrier frequency division multiple access (SC-FDMA) system, term " system " and " network " are often used by exchange.Cdma system can realize inserting such as cdma2000, universal terrestrial radio the wireless technology of (UTRA) or the like, and cdma2000 is contained IS-2000, IS-95 and IS-856 standard.UTRA comprises wideband CDMA (W-CDMA) and low spreading rate (LCR).Tdma system can be realized the wireless technology such as global system for mobile communications (GSM).The OFDMA system can realize UTRA (E-UTRA), IEEE 802.11, IEEE802.16, IEEE 802.20, the Flash-OFDM such as evolution
Or the like wireless technology.Wireless technology that these are different and standard are known in the art.In the document from " third generation partner program " tissue (3GPP) by name UTRA, E-UTRA and GSM have been described.In the document from " third generation partner program 2 " tissue (3GPP2) by name cdma2000 has been described.3GPP and 3GPP2 document are that the public is obtainable.
Some aspect of multicarrier transmitter for clarity sake, is described at High Rate Packet Data (HRPD) system that realizes IS-856.HRPD is also referred to as CDMA2000 1xEV-DO (Evolution-Data Optimized Evolution-Data Optimized), 1xEV-DO, 1x-DO, DO, high data rate (HDR) etc.Term " HRPD ", " EV-DO " and " DO " are often used by exchange.HRPD is described in 3GPP2C.S0024-B, and name is called " cdma2000 High Rate Packet Data Air InterfaceSpecification ", and its date issued is in March, 2007, is that the public is obtainable.For clarity sake, the many local term HRPD that uses of following specification.
Multiple carrier transmitter described herein can be used to access terminal and access point.Access point normally with the fixed station that accesses terminal and communicate by letter, also can be called as base station, Node B etc.It can be static or mobile accessing terminal, and also can be called as travelling carriage, subscriber equipment (UE), mobile device, terminal, subscriber unit, stand etc.Accessing terminal can be cell phone, PDA(Personal Digital Assistant), hand-held set, Wireless Telecom Equipment, handheld device, radio modem, laptop computer etc.For clarity sake, will be described in the use of the middle multicarrier transmitter that accesses terminal below.
Multicarrier transmitter can transmit one or more CDMA signals simultaneously, and each CDMA signal can send on different CDMA Channel.A CDMA Channel is the frequency channels that is used for a CDMA signal, is that 1.2288MHz is wide in HRPD.CDMA Channel is also referred to as carrier wave usually.
Fig. 1 shows on N CDMA Channel the example of N CDMA signal of transmission, and common N 〉=1 is as N〉be used for multi-carrier operation 1 the time.In this example, CDMA Channel 1 has carrier frequency f
Ch1, CDMA Channel 2 has carrier frequency f
Ch2, the rest may be inferred, and CDMA Channel N has carrier frequency f
ChNEach carrier frequency typically is selected as making CDMA Channel enough far to reduce interchannel interference separatedly.Usually, the carrier frequency of N CDMA Channel can be interrelated or not related.The carrier frequency of each CDMA Channel can independently be selected under the condition that satisfies a minimum channel interbody spacer standard.Each carrier frequency is evenly distributed on the frequency range and separates fixed frequency f at interval
Spacing, this fixed frequency can be 1.2288MHz or certain bigger value at interval.N CDMA signal can be with different (as shown in Figure 1) or identical power level.N CDMA signal can carry any kind data that are used for any business, for example voice, video, grouped data, text message etc.N CDMA signal can be sent to same access point or different access points.
In order to reduce cost, to reduce energy consumption, improve reliability and obtain other benefit, wish to use the least possible circuit to support the transmission of one or more CDMA Channel.T different radio-frequency transmissions chain can be used for reaching T CDMA signal into T CDMA Channel nearly generates, and T herein is the maximum number of the CDMA signal that can be sent simultaneously.Yet this T radio-frequency transmissions chain may increase the cost that accesses terminal significantly.
On the one hand, multicarrier transmitter uses an independent radio-frequency transmissions chain to be supported in and reaches and transmits nearly T CDMA signal on T the different CDMA Channel simultaneously, this independent radio-frequency transmissions chain can be the broadband and be designed to T adjacent CDMA Channel, T herein can be any suitable value.N CDMA signal can use this independent radio-frequency transmissions chain to transmit, and the number of N herein can reach T.Owing to use independent radio-frequency transmissions chain, this multicarrier transmitter can not only be saved power consumption but also economical and effective.
Fig. 2 shows the block diagram of a kind of design of multicarrier transmitter 200, and this multicarrier transmitter can be used to access terminal.Multicarrier transmitter 200 comprises numerical portion 202 and radio-frequency transmissions chain 204.
In numerical portion 202, have data processor 210, data processor 210 deal with data, pilot tone, control information, and provide N output code sheet of N CDMA signal to flow to N digital filter 212a to 212n.The complex value that chip sends a chip period typically, chip period are the duration sections by system's decision.Each output code laminar flow can be on a spreading rate (cx1), and this spreading rate is 1.2288 million chips/ second (Mcps) for HRPD.Each digital filter 212 carries out filtering to its output code laminar flow, carries out up-sampling and provides filtered sampling to flow to circulator 214.Each filtered sample streams can be at a sampling rate f
SampleOn.Sampling rate can be fix and based on the maximum CDMA number of signals that can be transmitted simultaneously and selected; Alternatively, sampling rate can be configurable and based on just at the same time the transmission the CDMA number of signals and selected.Each circulator 214 is operated as digital up converter, with digital local oscillator (LO) signal filtered sample streams is carried out up-conversion, and the sample streams after the up-conversion is provided.The digital LO signal of the CDMA signal that sends on CDMA Channel n has frequency f
n, frequency f
nCarrier frequency f by CDMA Channel n
ChnFrequency f with the simulation LO signal that is used to upconvert to radio frequency
cDetermine.Adder 216 receives and adds up from the sample streams after N the up-conversion of N circulator 214a to 214n, and a compound sampling stream is provided.218 pairs of compound sampling streams of preprocessor are carried out reprocessing and an output sample streams are provided.Digital to analog converter 220 will be exported sample streams and be converted to analog signal and the analog baseband signal that comprises N CDMA signal is provided.
A radio-frequency transmissions chain can be realized super-heterodyne architecture or Direct Conversion structure.In super-heterodyne architecture, in a plurality of level, baseband signal is carried out up-conversion, for example, in a level from the base band to the intermediate frequency (IF), subsequently in another level from if-to-rf.The Direct Conversion structure is also referred to as the zero intermediate frequency structure, and baseband signal is directly upconverted to radio frequency in a level.Super-heterodyne architecture can be used different circuit blocks and/or different circuit requirements is arranged with the Direct Conversion structure.The Direct Conversion structure is used in following description supposition.
Have simulation low-pass filter 222 in radio-frequency transmissions chain 204,222 pairs of analog baseband signals from digital to analog converter 220 of simulation low-pass filter carry out filtering, to remove the mirror image that produces and filtered signal is provided in digital-to-analogue conversion.Frequency mixer 224 uses the simulation LO signal from local oscillations maker 226 to come filtered signal is carried out up-conversion, with it from the baseband-converted to the radio frequency.Local oscillations maker 226 can comprise voltage-controlled oscillator (VCO), phase-locked loop (PLL), reference oscillator etc.Variable gain of variable gain amplifier (VGA) 228 usefulness is amplified the up-conversion signal from frequency mixer 224.230 pairs of signals from variable gain amplifier (VGA) 228 of band pass filter carry out filtering to remove the mirror image that produces in up-conversion.Band pass filter 230 can be the filter of surface acoustic wave (SAW) filter, ceramic filter or certain other type.232 pairs of signals from band pass filter 230 of power amplifier (PA) amplify, and the output signal of the radio frequency with suitable power levels is provided.This radio frequency output signal is by duplexer 234 routes and via antenna 236 emissions.As shown in Figure 2,224 signal is typically the complex signal of (I) component that has homophase and quadrature (Q) component from data processor 210 to frequency mixer.
Digital to analog converter 220 and radio-frequency transmissions chain 204 can be the broadbands, to support N CDMA signal of transmission on N CDMA Channel simultaneously.Digital to analog converter 220 can be operated under sufficiently high clock frequency, and has enough resolution conversions to comprise the digital sample streams of all N CDMA signals.Simulation low-pass filter 222 can have fixing or bandwidth varying, and this bandwidth can be enough wide so that by all CDMA signals that sends simultaneously.The analog circuit block of back also can be the broadband with by all CDMA signals.Band pass filter 230 can be the broadband and can pass through a complete frequency band, for example, the cellular band from 824 to 849MHz and from 1850 to 1910MHz Personal Communications Services (PCS) frequency band.
Fig. 2 shows a kind of particular design of radio-frequency transmissions chain 204.Usually, radio-frequency transmissions chain can comprise one or more levels of amplifier, filter, frequency mixer etc.These circuit blocks can have the arrangement different with layout shown in Figure 2.The radio-frequency transmissions chain also can comprise unshowned different and/or other circuit block among Fig. 2.The radio-frequency transmissions chain 204 of all or part can be implemented on one or more radio frequency integrated circuit (RFIC), the composite signal integrated circuits etc.For example, simulation low-pass filter 222, frequency mixer 224, local oscillations maker 226 and variable gain amplifier (VGA) 228 can be implemented on the radio frequency integrated circuit, for example, radio frequency sending set (RFT) or radio frequency sending set/receiver (RTR) chip.
In HRPD, accessing terminal to send one or more data channels, pilot channel, inverted speed indication (RRI) channel, Auxiliary Pilot Channel, data rate control (DRC) channel, affirmation (ACK) channel and data source control (DSC) channel in a CDMA signal to the reverse link of an access point.Data channel carries user data, and pilot channel carries pilot tone, and pilot tone is to access terminal and the priori data known of access point.Auxiliary Pilot Channel carries auxiliary pilot, the speed that inverted speed indication (RRI) channel designator it is believed that, data rate control (DRC) channel indicate this speed and this hope that accesses terminal that can receive a forward traffic channel that accesses terminal to receive the sector of this forward traffic channel from it.Data source of data source control (DSC) channel indication, this accesses terminal and wishes to receive forward traffic channel from this data source.Confirm that the Data Receiving on (ACK) channel indication forward traffic channel is success or failure.This DRC, ACK and DSC channel are sending on the reverse link to support the transfer of data on the forward link.This DRC, ACK and DSC channel are also referred to as the reverse overhead channel of forward link, or abbreviate the ROC channel as.
Access terminal and on one or more Forward CDMA Channels, to receive data, and can send data at one or more reverse CDMA channels.Forward CDMA Channel is the CDMA Channel on forward link, and reverse CDMA channel is the CDMA Channel in backward chaining.HRPD supports three kinds of patterns that send the ROC channel for Forward CDMA Channel.
In a kind of nothing feedback multiplexing modes, each Forward CDMA Channel is related with a different reverse CDMA channel.The ROC channel of each Forward CDMA Channel is sent out on the reverse CDMA channel of association.User's long code is used to expand all reverse CDMA channels.User's long code is a pseudo random number (PN) sequence that accesses terminal at.
In a kind of basic feedback multiplexing modes, a plurality of Forward CDMA Channels can be related with a given reverse CDMA channel.The ROC channel of these a plurality of Forward CDMA Channels is sent out with different long codes on the reverse CDMA channel of association, and each Forward CDMA Channel uses a long code, so just allows to distinguish the ROC channel of different Forward CDMA Channels.
In a kind of enhancing feedback multiplexing modes, nearly 16 Forward CDMA Channels can be related with a given reverse CDMA channel, nearly can in time and/or to use different Walsh (Walsh) sign indicating number to carry out multiplexed for the ROC channel of 4 Forward CDMA Channels, and use a different long code to send on the reverse CDMA channel of association.
Table 1 has been listed in HRPD three kinds feedback multiplexing modes and is provided Short Description for every kind of pattern.
Table 1
| Pattern | Describe |
| It is multiplexed not have feedback | The ROC channel of each Forward CDMA Channel is sent out with a common long code on the reverse CDMA channel of an association. |
| Basic feedback is multiplexed | The ROC channel of a plurality of Forward CDMA Channels is sent out with different long codes on the reverse CDMA channel of an association. |
| It is multiplexed to strengthen feedback | Nearly the ROC channel of 16 Forward CDMA Channels is sent out on the reverse CDMA channel of an association, and wherein nearly the ROC channel of 4 Forward CDMA Channels in time and/or the use sign indicating number carries out multiplexed and use a different long code to be sent out. |
Fig. 3 shows the processing procedure of not having the feedback multiplexing modes.N CDMA Channel processor 310a to 310n carries out N reverse CDMA channel 1 to N respectively and handles.In CDMA Channel processor 310a, data and overhead processor 320a carry out following content and handle: (i) data channel of reverse CDMA channel 1, pilot channel, RRI channel and Auxiliary Pilot Channel; The (ii) ROC channel of Guan Lian Forward CDMA Channel (DRC, ACK and DSC channel).Quadrature spread device 330a uses the chip of user's long code expansion from processor 320a and provides the output chip as reverse CDMA channel 1.CDMA Channel processor 310b to 310n carries out processing in a similar manner to reverse CDMA channel 2 to N respectively.Identical user's long code is used to all N reverse CDMA channel.
Fig. 4 shows the processing procedure of basic feedback multiplexing modes.N CDMA Channel processor 410a to 410n carries out N reverse CDMA channel 1 to N respectively and handles.In CDMA Channel processor 410a, data and overhead processor 420a and quadrature spread device 430a respectively with Fig. 3 in the data mode identical with quadrature spread device 330a with overhead processor 320a reverse CDMA channel 1 carried out handled.ROC processor 422b to 422m carries out the ROC channel of Forward CDMA Channel 2 to M respectively and handles, and this Forward CDMA Channel 2 to M is associated with reverse CDMA channel 1.The chip that quadrature spread device 432b to 432m uses long code 2 to M to expand respectively from ROC processor 422b to 422m respectively.The ROC channel that is mapped to M Forward CDMA Channel of reverse CDMA channel 1 can use M different long code.Adder 434a adds up and exports chip from the I chip of expander 430a and 432b to 432m and for reverse CDMA channel 1 provides I.Adder 434b adds up and exports chip from the Q chip of expander 430a and 432b to 432m and for reverse CDMA channel 1 provides Q.
CDMA Channel processor 410b to 410n carries out reverse CDMA channel 2 to N respectively and handles.In the reverse CDMA channel 2 to N each can be carried the ROC channel of zero, one or more Forward CDMA Channels.For among the CDMA Channel processor 410a to 410n each, come growth data channel, pilot channel, RRI channel and Auxiliary Pilot Channel with identical user's long code 1, use different long codes to expand the ROC channel of different Forward CDMA Channels.
Fig. 5 shows the processing procedure that strengthens the feedback multiplexing modes.N CDMA Channel processor 510a to 510n carries out N reverse CDMA channel 1 to N respectively and handles.In CDMA Channel processor 510a, data and overhead processor 520a carry out following content and handle: (i) data channel of reverse CDMA channel 1, pilot channel, RRI channel and Auxiliary Pilot Channel; The (ii) ROC channel of Guan Lian Forward CDMA Channel 1 to 4.The ROC channel of other Forward CDMA Channel that 522b to 522d pair of ROC processor and reverse CDMA channel 1 are related is carried out and is handled.522 pairs of nearly ROC channel execution processing of 4 related Forward CDMA Channels of each ROC processor.The chip that quadrature spread device 532b to 532d uses long code 2 to 4 to expand respectively from ROC processor 522b to 522d respectively.Nearly 4 different long codes can be used to nearly 16 Forward CDMA Channels that are mapped to reverse CDMA channel 1.Adder 534a and 534b add up respectively from the I of expander 530a and 532b to 532m and Q chip, and export chip for reverse CDMA channel 1 provides I and Q respectively.
CDMA Channel processor 510b to 510n carries out reverse CDMA channel 2 to N respectively and handles.In the reverse CDMA channel 2 to N each can be carried the ROC channel of zero, one or more Forward CDMA Channels.For among the CDMA Channel processor 510a to 510n each, come growth data channel, pilot channel, RRI channel and Auxiliary Pilot Channel with identical user's long code 1, use different long codes to expand and comprise the nearly ROC channel of the different sets of 4 Forward CDMA Channels.
Fig. 6 shows the block diagram of a kind of design of the data processor 210 that is used for all three kinds feedbacks of HRPD multiplexing modes.In this design, data processor 210 is supported in transmission that reaches on N the reverse CDMA channel and the feedback that reaches N Forward CDMA Channel, and data processor 210 comprises N CDMA Channel processor 620a to 620n.620 pairs of following contents of each CDMA Channel processor are carried out and are handled: (i) data channel of a reverse CDMA channel, pilot channel, RRI channel and Auxiliary Pilot Channel; The (ii) ROC channel of a Forward CDMA Channel.
In data processor 210, N PN maker 610a to 610n is respectively nearly N the Forward CDMA Channel that can be associated with a reverse CDMA channel and generates N different long code PN
T1To PN
TN PN maker 610a provides its long code PN respectively for all N CDMA Channel processor 620a to 620n of N reverse CDMA channel 1 to N
T1Long code PN
T1Be used to data channel, pilot channel, RRI channel and the Auxiliary Pilot Channel of all N reverse CDMA channel.Selector 612 receives this N long code and provides a suitable R OC long code PN for each CDMA Channel processor 620 from PN maker 610a to 610n
ROCThe ROC long code that offers each CDMA Channel processor 620 is used to the ROC channel of the Forward CDMA Channel that this CDMA Channel processor handling.For there not being the feedback multiplexing modes, selector 612 provides the ROC long code that is used for all N CDMA Channel processor 620a to 620n from the long code conduct of PN maker 610a, thus PN
ROC1=...=PN
ROCN=PN
T1For basic feedback multiplexing modes, selector 612 can provide the ROC long code that is used for N CDMA Channel processor 620a to 620n from the long code conduct of PN maker 610a to 610n respectively, thus PN
ROC1=PN
T1..., and PN
ROCN=PN
TNFor strengthening the feedback multiplexing modes, selector 612 can provide the long code conduct from each PN maker 610 to be used for the nearly ROC long code of 4 CDMA Channel processors 620.Usually, the operation of selector 612 depends on the mapping to reverse CDMA channel of the feedback multiplexing modes of selection and Forward CDMA Channel.
Each CDMA Channel processor 620 long code PN
T1Come data channel, pilot channel, RRI channel and Auxiliary Pilot Channel to carry out processing to a reverse CDMA channel.Each CDMA Channel processor 620 is also used ROC long code PN
ROCCome the ROC channel of a Forward CDMA Channel is carried out processing.Each CDMA Channel processor 620 can offer its ROC chip another CDMA Channel processor or receive the ROC chip from other CDMA Channel processor.Each CDMA Channel processor 620 provides the digital filter 212 of the output chip of a reverse CDMA channel to an association.
Output chip from each CDMA Channel processor 620 is carried out filtering by the digital filter 212 of an association, and is carried out Digital Up Convert by the circulator 214 of an association.Adder 216 adds up from sampling after the up-conversion of all N circulator 214a to 214n and direct current offset and compound sampling is provided.This direct current offset can be a programmable value, and it can be used to reduce the LO feedthrough of frequency mixer 224 in Fig. 2 radio-frequency transmissions link 204.Calibration can be performed to determine the amount of direct current offset, the amount of this direct current offset energy minimization LO feedthrough.This direct current offset can be provided for adder 216 subsequently.
Fig. 7 has shown the design of CDMA Channel processor 620a among Fig. 6.In CDMA Channel processor 620a, 712 pairs of pilot tones of processor are carried out and are handled and provide pilot chip, and 714 pairs of auxiliary pilots of processor are carried out and handled gain G of multiplier 716 usefulness
APCome the output of convergent-divergent processor 714 and the auxiliary pilot chip is provided, 718 pairs of RRI channels of processor are carried out and are handled gain G of multiplier 720 usefulness
RRICome the output of convergent-divergent processor 718 and RRI is provided chip, 722 pairs of L data channels of processor are carried out and are handled, herein L 〉=1.Multiplier 724a to 7241 uses gain G respectively
D1To G
DLCome convergent-divergent be used for L data channel processor 722 output and data chips is provided.The add up chip of from processor 712 and multiplier 716,720,724a to 7241 of adder 726.Quadrature spread device 728 long code PN
T1Expansion is from the chip of adder 726 and the chip of data channel, pilot channel, RRI channel and the Auxiliary Pilot Channel of reverse CDMA channel 1 is provided.
732 couples of ACK of processor and DSC channel are carried out and are handled.Gain G of multiplier 734 usefulness
ACK/DSCCome the output of convergent-divergent processor 732 and ACK/DSC is provided chip.736 pairs of DRC channels of processor are carried out and are handled.Gain G of multiplier 738 usefulness
DRCCome the output of convergent-divergent processor 736 and DRC is provided chip.Quadrature spread device 740 long code PN
ROC1Expansion is from the chip of multiplier 734 and 738 and the ROC chip of Forward CDMA Channel 1 is provided.Gating unit 742a to 742n receives the ROC chip of Forward CDMA Channel 1 to N respectively.For each gating unit 742, if the ROC channel of its Forward CDMA Channel is sent out on reverse CDMA channel 1, then this gating unit 742 provides its ROC chip to arrive adder 744 at a reasonable time.
Adder 744 adds up from the chip of expander 728 and gating unit 742a to 742n.Gain G of multiplier 746 usefulness
1Come convergent-divergent from the chip of adder 744 and the output chip of reverse CDMA channel 1 is provided.Gain G
1Transmitting power decision by reverse CDMA channel 1.Gain G
AP, G
RRI, G
D1To G
DL, G
ACK/DSCAnd G
DRCDecision is in the pertinent transmit power of different data, pilot tone and the overhead channel of reverse CDMA channel 1 transmission.
Fig. 7 has shown the exemplary designs of CDMA Channel processor 620a.Among Fig. 6 each CDMA Channel processor 620b to 620n can with Fig. 7 in the same mode of CDMA Channel processor 620a realize.The processing of N reverse CDMA channel also can otherwise realize.In another design, each CDMA Channel processor is carried out data channel, pilot channel, RRI channel and the Auxiliary Pilot Channel of a reverse CDMA channel and is handled, and this CDMA Channel processor can comprise unit 712 to 728 and the unit 742 to 746 among Fig. 7.A ROC processor can be carried out the ROC channel of all Forward CDMA Channels and handle, and ROC chip to an appropriate C dma channel processor of each Forward CDMA Channel is provided.
The digital gain G that is used for N reverse CDMA channel
1To G
NCan be provided to obtain the transmitting power of hope into each CDMA Channel.This N reverse CDMA channel can have different transmitting powers, supports different data rates and/or communicates with different access point.This gain G
1To G
NAlso can be provided to obtain total transmitting power of hope, also can be used to automatic gain control (AGC) into all N CDMA Channel.In a design, the gain of the VGA228 in the radio-frequency transmissions link 204 can be with thick step-size change, gain G
1To G
NCan in a particular range, (for example 12dB) change with thin step-length (for example 0.25dB).Gain G
1To G
NResolution (for example with regard to bit number) can be based on the maximum differential between the strongest and the most weak reverse CDMA channel (in a design, being 15dB) and the thin step-length of wishing and selected.
Fig. 8 has shown the structure chart of the design of the digital filter 212a that is used for reverse CDMA channel 1 and circulator 214a.In digital filter 212a, finite impulse response (FIR) (FIR) filter 812 receives also filtering from the output chip of CDMA Channel processor 620a.FIR filter 812 can be carried out shaping pulse comes to obtain for the CDMA signal that sends hope on reverse CDMA channel 1 spectrum signature.FIR filter 812 also can should be exported chip by up-sampling, for example, was upsampled to four times of spreading rates (cx4) from spreading rate.FIR filter 812 can be realized with tap (tap) number of enough numbers, to obtain the filter response of expectation.Interpolation filter 814 is carried out interpolation in the sampling from FIR filter 812, and with sampling rate f
SampleProvide filtered sampling, this f
SampleCan be 16 times of spreading rates (cx16).Interpolation filter 814 can realize with one or more level, for example, in a level from cx4 to cx8, in another level from cx8 to cx16.Can separate based on the peak frequency between the minimum and the highest CDMA Channel of supporting at multicarrier transmitter 200 and select sampling rate f
SampleThe up-sampling that filter 812 and/or filter 814 are carried out allows this filtered sampling quilt circulator 214a Digital Up Convert to a higher frequency subsequently.
In circulator 214a, adder 822 and register 824 forms phase accumulators, and it is in the add up frequency f of CDMA Channel 1 of each sampling period
1The bit wide of this phase accumulator can be based on the highest up-conversion frequency and desired frequency resolution and is selected.For example, the frequency range of frequency resolution support ± 9.83MHz of 23 phase accumulator usefulness 2.34Hz.In each sampling period, 826 pairs of adders are from current phase value and a phase deviations summation of register 824, this phase deviation can be used to solve with radio-frequency transmissions chain 204 in VGA 228 or the out of phase that is associated of the different conditions of PA 232.
In each sampling period, 828 usefulness phase place from adder 826 in CORDIC (CORDIC) unit is rotated a filtered second mining sample from digital filter 212a, and a sampling after the up-conversion is provided.A kind of iterative algorithm is realized in CORDIC unit 828, and the quick hardware that this iterative algorithm allows to use simple displacement and addition/subtraction hardware to realize trigonometric function calculates.CORDIC unit 828 can rotate compound sampling in the mode of iteration, the more high accuracy of iteration produce output result more frequently wherein, and for example, 9 iteration can provide ± accuracy of 0.22 degree.In a design, CORDIC unit 828 may operate in clock frequency Qf
SampleCome to provide in each sampling period the sampling of a up-conversion with the delay in a sampling period down.In another design, CORDIC unit 828 can realize with a plurality of pipeline stages, and operates in and be lower than Qf
SampleClock frequency under.For example, clock frequency f be realized and be operated in CORDIC unit 828 can with Q pipeline stages
SampleFollowing, and the pipelining delay in an available Q sampling period provides a sampling after the up-conversion in each sampling period.
Fig. 9 shows the block diagram of a design of preprocessor 218 in Fig. 2 and 6.In preprocessor 218, I/Q mismatch compensation unit 912 combine digital predistortions solve in I and gain Q path between and phase place (or I/Q) mismatch of this quadrature up-conversion in the radio frequency.One group of digital to analog converter 220, simulation low-pass filter 222 and frequency mixer 224 can be used to each in I and the Q path.This gain mismatches can be caused by the different gains of digital to analog converter, simulation low-pass filter and the frequency mixer in I and Q path.This phase mismatch may be owing to I and QLO signal from LO maker 226 are not caused by complete 90 ° of out-phase.This gain and/or phase mismatch can cause generating residual sideband energy (RSB) mirror image in from the output waveform of frequency mixer 224.This RSB mirror image can reduce performance, and especially when between the transmitting power of the N that sends at the same time CDMA signal big difference being arranged, it can be relative big causing this RSB mirror image to be compared with the most weak CDMA Channel.
Output from desirable quad upconverter can be represented as:
Y (t)=X
I(t) cos (ω
cT)-X
Q(t) sin (ω
cT), equation (1)
X herein
I(t) and X
Q(t) provide the I and the Q baseband signal of upconverter,
The signal of Y (t) after from the up-conversion of upconverter, and
ω
c=2 π f
cIt is the LO frequency of representing with radian per second.
The output of nonideal quad upconverter can be represented as:
Y (t)=X
I(t) cos (ω
cT)-KX
Q(t) sin (ω
cT+ θ), equation (2)
K herein is a gain mismatches, and θ is a phase mismatch.Equation (2) with gain mismatches and phase mismatch merger in Q component.
The predistortion that is used for compensating gain mismatch and phase mismatch can be represented as:
X
I, pre-dis(t)=X
I(t)+AX
QAnd equation (3) (t),
X
Q, pre-dis(t)=BX
Q(t), equation (4)
X herein
I, pre-dis(t) and X
Q, pre-dis(t) be the signal of I and Q predistortion,
α be gain mismatches estimation and
Parameter alpha and
Can obtain from the calibration of radio-frequency transmissions link 204.If the gain and the estimation of phase mismatch are accurately, so α ≈ K with
Then pass through signal after the up-conversion of the predistortion signal after near the desirable up-conversion shown in the equation (1).
I/Q mismatch compensation unit 912 from adder 216 receive I and Q second mining sample and generate I and the Q predistortion after sampling, shown in equation (3) and (4).From the I of adder 216 and Q second mining sample corresponding to the X in equation (3) and (4)
I(t) and X
Q(t), and from the I of unit 912 and the sampling after the Q predistortion corresponding to X
I, pre-dis(t) and X
Q, pre-dis(t).
The sampling of convergent-divergent such as (for example, 4,2,1,0.5,0.25) that can slightly gain with one by left or the dextroposition figure place of wishing of thick unit for scaling 916 from filter 914 with the position of each sampling.Unit for scaling 916 can be used to thick digital gain control, and the multiplier 746 among each CDMA Channel processor 620a to 620n can be used to count accurately the word gain controlling.
Get back to Fig. 2, simulation low-pass filter 222 provides mirror image to suppress in the analog baseband signal from DAC 220, to satisfy the spurious emissions demand.This analog baseband signal is included in DAC clock frequency (for example, cx64) mirror image under and the mirror image under interpolation clock frequency (for example, cx16 and cx32).This analog baseband signal is because sampling and the holding circuit in DAC 220 also has sine to roll-off.This sine roll-offs and can for example digitally be solved with the filter among Fig. 9 914.In a design, the fixed broadband filter can be used to simulation low-pass filter 222, and its bandwidth that is set to the highest supporting signal bandwidth twice can be arranged, with the amount that tilts in the check strap.This filter can be Butterworth (Butterworth) filter or other filter, and can have suitable exponent number (for example, second order).When the interpolation filter in Fig. 8 and 9 814 and 914 carried out filtering to sampling respectively fully, this filter can provide the mirror image of hope to suppress.In another design, variable filter can be used to simulation low-pass filter 222, and its bandwidth based on the highest actual signal bandwidth setting can be arranged, and this variable filter can be a single order RC filter, second order Butterworth (Butterworth) filter etc.
Figure 10 shows a design that is used for the processing procedure 1000 transmitted on a plurality of frequency channels.A frequency channels can be a CDMA Channel, a GSM channel, a RF channel, a carrier wave or the like.System according to specific for example HRPD can be each the generation output chip (piece 1012) in a plurality of frequency channels.For piece 1012, to the processing of each frequency channels can comprise coding, interweave, sign map and expansion or the like.The output chip of each frequency channels can be with based on the transmitting power of this frequency channels and convergent-divergent is carried out in the gain of selecting.The output chip of each frequency channels can be thought that this frequency channels obtains filtered sampling (piece 1014) by digitally filtering and up-sampling.
The filtered sampling of each frequency channels can be thought the sampling (piece 1016) after this frequency channels obtains up-conversion by Digital Up Convert to a different frequency.The filtered sampling of a frequency channels can be the center by Digital Up Convert and with DC by 0Hz.Digital Up Convert can be calculated based on CORDIC and is performed.In a design, can carry out the repeatedly iteration that CORDIC calculates for each filtered sampling in a plurality of pipeline stages (for example, a level is used for an iteration), to rotate this filtered sampling with a phase place by the channel frequency decision.
Sampling after the up-conversion of a plurality of frequency channels can be combined to obtain to comprise the compound sampling (piece 1018) of the signal that is used for these a plurality of frequency channels.Can on compound sampling, carry out predistortion with gain and the phase mismatch (piece 1020) of compensation simulation quadrature up-conversion subsequently to radio frequency.Sampling after the predistortion can be upsampled to second sampling rate from first sampling rate, to obtain output sampling (piece 1022).Second sampling rate can be optionally, for example, selects based on the frequency channels number that is sent out.Can will export sample conversion with digital to analog converter and become analog signal (piece 1024).This analog signal can be handled (for example, filtering, quadrature up-conversion and amplification) with an independent radio-frequency transmissions chain and generate radio frequency output signal (piece 1026).
In a design of the piece 1012 that can be applicable to HRPD, at least one long code (for example, PN
T1To PN
TN) can be generated.First group of physical layer channel of a plurality of frequency channels (for example, data channel, pilot channel, RRI channel and Auxiliary Pilot Channel) can be specified long code (for example, PN based on one in this at least one long code
T1) expand.Second group of physical layer channel of these a plurality of frequency channels (for example, DRC channel, ack channel and DSC channel) can be expanded based on this at least one long code.For there not being the feedback multiplexing modes, second group of physical layer channel of each frequency channels can be expanded based on the long code of this appointment.For basic feedback multiplexing modes, second group of physical layer channel of each frequency channels can be expanded based on a different long code.For strengthening the feedback multiplexing modes, second group of physical layer channel of at least two frequency channels subclass of a plurality of frequency channels can be expanded based on two different long codes in this at least one long code at least.In a design, for example shown in Fig. 7, first group of physical layer channel of each frequency channels can expand based on the long code of this appointment.Second group of physical layer channel of each frequency channels can be based upon this second group of physical layer channel of this frequency channels and a long code selecting (PN for example
ROC) expand.For each frequency channels, the expansion chip of first group of physical layer channel of this frequency channels can be combined to obtain the output chip of this frequency channels with the expansion chip that is mapped to second group of physical layer channel of this frequency channels.
Figure 11 shows a design supporting the processing procedure 1100 of a plurality of frequency channels with single radio frequency emission chain.A digital sample streams of the signal after carrying a plurality of Digital Up Converts on a plurality of frequency channels can be switched to simulation with a digital to analog converter, to obtain analog signal (square frame 1112).One in the signal after these a plurality of Digital Up Converts can be the center with DC, or upconverts to 0Hz.This digital to analog converter can be the broadband, and can have enough dynamic ranges to handle signal after all Digital Up Converts on these a plurality of frequency channels.Signal after these a plurality of Digital Up Converts can send on different transmitted power levels.Digital to analog converter may operate under the clock frequency, the frequency the highest possible or that support of the signal of this clock frequency after based on these a plurality of Digital Up Converts and being determined.Digital to analog converter also may operate under the V-CLK frequency, the highest frequency of the signal of this V-CLK frequency after based on a plurality of Digital Up Converts that are sent out and being determined.
This analog signal that comprises the signal after a plurality of Digital Up Converts on a plurality of frequency channels can be carried out filtering with an analog filter, to obtain filtered signal (piece 1114).This analog filter can have fixed-bandwidth, the highest probable frquency of the signal of this fixed-bandwidth after based on these a plurality of Digital Up Converts and being determined.This analog filter also can have bandwidth varying, the highest frequency of the signal of this bandwidth varying after based on these a plurality of Digital Up Converts that are sent out and being determined.Can should upconvert to radio frequency (piece 1116) by filtered signal with frequency mixer.This frequency mixer can be the broadband and be designed to cover this a plurality of frequency channels.Can be at the signal after a plurality of Digital Up Converts on a plurality of frequency channels corresponding to other signal of a plurality of CDMA signals on a plurality of CDMA Channel in a HRPD system or other communication system.
Signal after a plurality of Digital Up Converts on a plurality of frequency channels is different from a plurality of subcarriers in ofdm signal in can mode below.At first, the frequency of these a plurality of frequency channels can be selected (obedience minimum separation criteria) independently, and a plurality of subcarriers in OFDM are constrained to concrete frequency or position so that keep orthogonality; The second, by typically filtering or restricted band, and that a plurality of subcarriers among the OFDM are combined these a plurality of frequency channels is filtered then before combination; The 3rd, transmitter is the additional Cyclic Prefix of each OFDM symbol, and receiver removes this Cyclic Prefix, and Cyclic Prefix is not used to the signal after these a plurality of Digital Up Converts; The 4th, each frequency channels can carry data and control channel, and typically sends data in the many subcarriers in OFDM; The 5th, each frequency channels can be independent of other frequency channels and be launched and receive, and typically sends and receive all subcarriers for OFDM.
It should be appreciated by those skilled in the art that information and signal can use any multiple different technology and method to represent, for example, the data that specification is mentioned above, instruction, order, information, signal, position, symbol and chip can be represented as voltage, electric current, electromagnetic wave, magnetic field or particle, light field or particle or above-mentioned any combination.
Various illustrative logical block, module, circuit and the algorithm steps that those skilled in the art will further understand description related to the present invention can be used as electronic hardware, computer software or both and makes up and realize.For the interchangeability of hardware and software clearly is described, above-described various illustrative assemblies, square frame, module, circuit and step are dependent on their function usually.It still is that software depends on specific application and the design constraint that puts on this whole system that above-mentioned function is implemented as hardware.Know the function that those skilled in the art can realize this description in a different manner for each specific application, but such realization result should not be interpreted as having departed from scope of the present invention.
Combine with this paper disclosure various illustrative logical block, module and the circuit described can be implemented or carry out with general processor, digital signal processor (DSP), application-specific integrated circuit (ASIC) (ASIC), field programmable gate array (FPGA) or other programmable logic device, separation gate or the transistor logic, isolating hardware element or the above-mentioned any combination that are designed to carry out representation function herein.General processor can be a microprocessor, but interchangeable, and this processor can be any traditional processor, controller, microcontroller or state machine.Processor also may be implemented as the combination of computing equipment, and for example combination of the combination of digital signal processor and microprocessor, a plurality of microprocessors, one or more microprocessor are together with the combination of a digital signal processing core or the combination of any other this type of configuration.
Can be presented as directly that in conjunction with the method for this paper disclosure description or the step of algorithm hardware, software module or the two of being carried out by processor make up.Software module can be arranged in the storage medium form of random-access memory (ram), flash memory (flash memory), read-only memory (ROM), EPROM (Erasable Programmable Read Only Memory) (EPROM), EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM), register, hard disk, displacement disc, CD-ROM or any other known technology.Exemplary storage medium is coupled to processor so that this processor can be from the storage medium read message and to its writing information.Alternatively, this storage medium can be integrated in this processor.This processor and this storage medium can be arranged in an application-specific integrated circuit (ASIC), and this application-specific integrated circuit (ASIC) may reside in the user terminal.Alternatively, this processor and this storage medium can be used as discrete component and are positioned at user terminal.
Any technical staff of this area provide above explanation of the present disclosure so that can both implement or use the disclosure.For a person skilled in the art, all will be conspicuous to various modifications of the present disclosure, and under the prerequisite that does not break away from the scope of the present disclosure, the General Principle that defines can be applied to other distortion here.Therefore, the disclosure is not to want to be limited to example described herein and design, but will meet and principle disclosed herein and novel features the widest consistent scope.
Claims (35)
1, a kind of device comprises:
At least one processor, be used to each frequency channels in a plurality of frequency channels to generate the output chip, with output chip Digital Up Convert to a different frequency of each frequency channels and the sampling after obtaining the up-conversion of this frequency channels, and making up sampling after the up-conversion of described a plurality of frequency channels to obtain compound sampling, this compound sampling comprises the signal of described a plurality of frequency channels; And
Be coupled to the memory of described at least one processor.
2, device as claimed in claim 1, wherein, the gain that described at least one processor determines based on the transmitting power by each frequency channels generates the output chip of this frequency channels.
3, device as claimed in claim 1, wherein, described at least one processor carries out digital filtering and up-sampling to the output chip of each frequency channels, obtaining the filtered sampling of this frequency channels, and
The filtered sampling of each frequency channels of Digital Up Convert is with the sampling after the up-conversion that obtains this frequency channels.
4, device as claimed in claim 3, wherein, described at least one processor calculates the filtered sampling of each frequency channels of Digital Up Convert based on CORDIC (CORDIC).
5, device as claimed in claim 4, wherein, described at least one processor is carried out the repeatedly iteration that CORDIC is calculated to each filtered sampling in a plurality of pipeline stages, so that a specific phase place is rotated in this filtered sampling.
6, device as claimed in claim 1, wherein, described at least one processor is carried out predistortion to described compound sampling, with gain and the phase mismatch of compensating analog quadrature up-conversion to radio frequency (RF).
7, device as claimed in claim 1, wherein, described at least one processor is upsampled to optional second sampling rate with described compound sampling from first sampling rate.
8, device as claimed in claim 1, wherein, described at least one processor generates at least one long code, specify long code that first group of physical layer channel of described a plurality of frequency channels carried out based on one in described at least one long code and expand, and second group of physical layer channel of described a plurality of frequency channels carried out expansion based on described at least one long code.
9, device as claimed in claim 8, wherein, described at least one processor is carried out expansion based on described appointment long code to second group of physical layer channel of each frequency channels in described a plurality of frequency channels.
10, device as claimed in claim 8, wherein, described at least one processor is carried out expansion based on a different long code to second group of physical layer channel of each frequency channels in described a plurality of frequency channels.
11, device as claimed in claim 8, wherein, described at least one processor is carried out expansion based at least two different long codes in described at least one long code to second group of physical layer channel of at least two frequency channels subclass in described a plurality of frequency channels.
12, device as claimed in claim 8, wherein, described at least one processor is carried out expansion based on described appointment long code to first group of physical layer channel of each frequency channels, based on a long code of from described at least one long code, selecting second group of physical layer channel of each frequency channels carried out expansion, and for each frequency channels, make up the expansion chip and the expansion chip that is mapped to second group of physical layer channel of this frequency channels of first group of physical layer channel of this frequency channels, to obtain the output chip of this frequency channels.
13, device as claimed in claim 8, wherein, described first group of physical layer channel comprises at least one in data channel, pilot channel, inverted speed indication (RRI) channel and the Auxiliary Pilot Channel.
14, device as claimed in claim 8, wherein, described second group of physical layer channel comprises at least one in data rate control (DRC) channel, affirmation (ACK) channel and data source control (DSC) channel.
15, device as claimed in claim 1, wherein, described a plurality of frequency channels are corresponding to a plurality of code division multiple accesss (CDMA) channel in High Rate Packet Data (HRPD) system.
16, a kind of method comprises:
For each frequency channels in a plurality of frequency channels generates the output chip;
With output chip Digital Up Convert to a different frequency of each frequency channels, and obtain sampling after the up-conversion of this frequency channels; And
Make up sampling after the up-conversion of described a plurality of frequency channels to obtain compound sampling, this compound sampling comprises the signal of described a plurality of frequency channels.
17, as the method for claim 16, also comprise:
The output chip of each frequency channels is carried out digital filtering and up-sampling to obtain the filtered sampling of this frequency channels, and wherein, the sampling of Digital Up Convert after with the up-conversion that obtains this frequency channels carried out in the filtered sampling of each frequency channels.
18, as the method for claim 16, also comprise:
Described compound sampling is carried out predistortion, with gain and the phase mismatch of compensating analog quadrature up-conversion to radio frequency (RF).
19, as the method for claim 16, also comprise:
Described compound sampling is upsampled to optional second sampling rate from first sampling rate.
20, as the method for claim 16, wherein, the step of described generation output chip comprises:
Generate at least one long code,
Specify long code that first group of physical layer channel of described a plurality of frequency channels carried out based on one in described at least one long code and expand, and
Based on described at least one long code second group of physical layer channel of described a plurality of frequency channels carried out expansion.
21, a kind of device comprises:
Be used to each frequency channels in a plurality of frequency channels to generate the module of exporting chip;
Be used for output chip Digital Up Convert to the different frequency of each frequency channels and the module of the sampling after obtaining the up-conversion of this frequency channels; And
Be used to make up sampling after the up-conversion of described a plurality of frequency channels with the module of the compound sampling of the signal that obtains to comprise described a plurality of frequency channels.
22, as the device of claim 21, also comprise:
Be used for output chip to each frequency channels and carry out digital filtering and up-sampling module with the filtered sampling that obtains this frequency channels, wherein, the sampling of Digital Up Convert after with the up-conversion that obtains this frequency channels carried out in the filtered sampling of each frequency channels.
23, as the device of claim 21, also comprise:
Be used for to described compound sampling carry out predistortion with the compensating analog quadrature up-conversion to the gain of radio frequency (RF) and the module of phase mismatch.
24, as the device of claim 21, also comprise:
Be used for described compound sampling is upsampled to from first sampling rate module of optional second sampling rate.
25, as the device of claim 21, wherein, the module of described generation output chip comprises:
Be used to generate the module of at least one long code,
Be used for a module of specifying long code to first group of physical layer channel execution expansion of described a plurality of frequency channels based on described at least one long code, and
Be used for second group of physical layer channel of described a plurality of frequency channels being carried out the module of expansion based on described at least one long code.
26, a kind of computer program comprises:
Computer-readable medium comprises:
Make computer generate the code of the output chip of each frequency channels in a plurality of frequency channels;
Make computer with output chip Digital Up Convert to the different frequency of each frequency channels and the code of the sampling after obtaining the up-conversion of this frequency channels; And
Make sampling after the up-conversion of the described a plurality of frequency channels of computer combined with the code of the compound sampling of the signal that obtains to comprise described a plurality of frequency channels.
27, a kind of device comprises:
Analog filter is configured to the analog signal that comprises a plurality of Digital Up Convert signals on a plurality of frequency channels is carried out filtering, and filtered signal is provided; And
Frequency mixer is configured to described filtered signal is upconverted to radio frequency (RF).
28, as the device of claim 27, wherein, described analog filter has fixed-bandwidth, and this fixed-bandwidth is based on the highest probable frquency decision of described a plurality of Digital Up Convert signals.
29, as the device of claim 27, wherein, described analog filter has bandwidth varying, and this bandwidth varying is based on the highest frequency decision of described a plurality of Digital Up Convert signals.
30, as the device of claim 27, also comprise:
Digital to analog converter (DAC) is configured to digital sample streams is transformed into simulation and described analog signal is provided.
31, as the device of claim 30, wherein, described digital to analog converter operates on the clock frequency based on the highest probable frquency decision of described a plurality of Digital Up Convert signals.
32, as the device of claim 30, wherein, described digital to analog converter operates on the V-CLK frequency based on the highest frequency decision of described a plurality of Digital Up Convert signals.
33, as the device of claim 27, wherein, the described a plurality of Digital Up Convert signals on described a plurality of frequency channels are corresponding to a plurality of CDMA signals on a plurality of code division multiple accesss (CDMA) channel in High Rate Packet Data (HRPD) system.
34, a kind of device comprises:
Be used for the analog signal that comprises a plurality of Digital Up Convert signals on a plurality of frequency channels is carried out filtering to obtain the module of filtered signal; And
Be used for described filtered signal is upconverted to the module of radio frequency (RF).
35, as the device of claim 34, also comprise:
Be used for digital sample streams is transformed into simulation to obtain the module of described analog signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510644952.1A CN105376038A (en) | 2006-07-14 | 2007-07-14 | Device and method for emitting multiple cdma channels |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US83104406P | 2006-07-14 | 2006-07-14 | |
| US60/831,044 | 2006-07-14 | ||
| US11/777,250 | 2007-07-12 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510644952.1A Division CN105376038A (en) | 2006-07-14 | 2007-07-14 | Device and method for emitting multiple cdma channels |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101490996A true CN101490996A (en) | 2009-07-22 |
Family
ID=40892171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2007800265068A Pending CN101490996A (en) | 2006-07-14 | 2007-07-14 | Apparatus for transmitting multiple CDMA channels |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101490996A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102231635A (en) * | 2011-06-23 | 2011-11-02 | 上海中科高等研究院 | Direct frequency conversion receiver |
| CN102647194A (en) * | 2012-04-01 | 2012-08-22 | 东南大学 | 802.11p transmitter based on virtual instrument and transmitting method |
| CN104662794A (en) * | 2012-07-26 | 2015-05-27 | 瑞典爱立信有限公司 | Digital upconversion for multi-band multi-order power amplifiers |
| CN108390674A (en) * | 2014-09-25 | 2018-08-10 | 英特尔Ip公司 | D convertor circuit, device and method and digital-analog convertion method |
-
2007
- 2007-07-14 CN CNA2007800265068A patent/CN101490996A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102231635A (en) * | 2011-06-23 | 2011-11-02 | 上海中科高等研究院 | Direct frequency conversion receiver |
| CN102231635B (en) * | 2011-06-23 | 2014-10-22 | 中国科学院上海高等研究院 | Direct frequency conversion receiver |
| CN102647194A (en) * | 2012-04-01 | 2012-08-22 | 东南大学 | 802.11p transmitter based on virtual instrument and transmitting method |
| CN102647194B (en) * | 2012-04-01 | 2014-07-09 | 东南大学 | 802.11p transmitter based on virtual instrument and transmitting method |
| CN104662794A (en) * | 2012-07-26 | 2015-05-27 | 瑞典爱立信有限公司 | Digital upconversion for multi-band multi-order power amplifiers |
| US9571042B2 (en) | 2012-07-26 | 2017-02-14 | Telefonaktiebolaget L M Ericsson (Publ) | Digital upconversion for multi-band multi-order power amplifiers |
| CN104662794B (en) * | 2012-07-26 | 2018-09-18 | 瑞典爱立信有限公司 | Method, apparatus and system for numerically converting |
| US10637403B2 (en) | 2012-07-26 | 2020-04-28 | Telefonaktiebolaget Lm Ericsson (Publ) | Digital upconversion for multi-band multi-order power amplifiers |
| CN108390674A (en) * | 2014-09-25 | 2018-08-10 | 英特尔Ip公司 | D convertor circuit, device and method and digital-analog convertion method |
| CN108390674B (en) * | 2014-09-25 | 2021-10-15 | 苹果公司 | Digital-to-analog converter circuit, digital-to-analog converter device, digital-to-analog converter method and digital-to-analog converter method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105376038A (en) | Device and method for emitting multiple cdma channels | |
| US10128798B2 (en) | Adjusting envelope tracking power supply | |
| JP5564111B2 (en) | Semiconductor device | |
| JP5726805B2 (en) | Multiband radio frequency modulator | |
| US20070211821A1 (en) | Digital transmitter | |
| EP2541781A1 (en) | Rf transmitter architecture and method therefor | |
| JP2008509575A (en) | All-digital transmitter including digital bandpass sigma-delta modulator | |
| US9450798B2 (en) | Transmitter circuit, communication unit and method for amplifying a complex quadrature signal | |
| WO2007117761A2 (en) | Rf transmitter with interleaved iq modulation | |
| JP2017521888A (en) | Dynamic local oscillator (LO) scheme and switchable receive (RX) chain for carrier aggregation | |
| CN101490996A (en) | Apparatus for transmitting multiple CDMA channels | |
| EP1322042B1 (en) | Convolutional encoding using a modified multiplier | |
| CN112368986A (en) | Ultra-high data rate digital millimeter wave transmitter with high-efficiency spectral filtering | |
| TW200302010A (en) | Transmit frequency domain equalizer | |
| US6870435B2 (en) | Electromagnetic wave transmitter, receiver and transceiver systems, methods and articles of manufacture | |
| US20070018876A1 (en) | Method and apparatus for a transmission signal up-converting filter | |
| CN101379717A (en) | Digital-to-radio frequency conversion device, chip set, transmitter, user terminal and data processing method | |
| US20060098761A1 (en) | Multi-mode transmitter | |
| US5784419A (en) | Efficient digital filter and method using coefficient precombing | |
| US20050111576A1 (en) | Peak-to-average reduction technique for multi-carrier power amplifiers | |
| US7577183B2 (en) | Transmission apparatus and peak reduction method | |
| EP1311073A1 (en) | Modulation system for complex spreading codes | |
| WO2012037822A1 (en) | Digital predistortion system and digital predistortion processing method | |
| CN1322408A (en) | Transmission over bundled channels in CDMA mobile radio system | |
| Bertran et al. | Digital front-end and system overview in wireless communication |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| REG | Reference to a national code |
Ref country code: HK Ref legal event code: DE Ref document number: 1132602 Country of ref document: HK |
|
| REG | Reference to a national code |
Ref country code: HK Ref legal event code: WD Ref document number: 1132602 Country of ref document: HK |
|
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20090722 |