CN101488922A - Network-on-chip router having adaptive routing capability and implementing method thereof - Google Patents
Network-on-chip router having adaptive routing capability and implementing method thereof Download PDFInfo
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Abstract
The invention relates to the technical field of on-chip multiprocessor internuclear communication, which aims to provide an on-chip network router having adaptive routing ability and implementation method thereof, used for constructing an on-chip network communication system. The on-chip network router comprises an input controller, an input buffer, a route moderator, an output controller and an output stream controller that are sequentially connected; the input buffer comprises a data register set in turn and a data selector, and a data packet pointer is connected with the data selector. In the invention, the route process has certain adaptivity by using an advanced XY router, thereby being capable of dynamically selecting proper data ports according to the congestion degree of data ports, reducing congestion of data packets, and improving the transmission speed and thuoughput of network. The application of modularized design method can reduce the complexity of design, thereby improving the efficiency of module function verification. The design of ports between modules simplifies the module design, thereby being convenient for high-efficient interaction between the modules.
Description
Technical field
The present invention relates to the internuclear communication technical field of on-chip multi-processor, proposed a kind of network-on-chip router and its implementation that possesses adaptive routing capability, be used to make up the network-on-chip communication system.
Background technology
Along with the development of computer manufacturing and integrated circuit technique, the number of transistors on the unit silicon chip is doubled and redoubled, and also just meaning can integrated more processor core on the unit silicon area.Chip multi-core is promptly realized the architecture of a plurality of processor cores on single silicon chip, because the simplicity of its design and checking, the advantage on performance and energy consumption progressively is subjected to the favor of industrial quarters simultaneously.
Important problem is exactly the problem that communicates to connect between processor in chip multiprocessors.Traditional mode is to adopt the mode of shared bus, and promptly a plurality of processors are connected on the bus, when a plurality of processors need use the bus access internal memory, decide access right by bus arbiter.The shared bus mode realizes simply, and is full-fledged, and can come simplified design by using IP kernel, and therefore, the shared bus mode is used widely in traditional chip multi-core architecture.
But along with further developing of integrated manufacturing technology, the processor check figure of chip multi-core will further increase.Thus, the conventional bus mode will run into bottleneck: bus is a kind of interconnection structure of shared medium, and a certain moment only allows an equipment to use bus.During bus was occupied, every other request got clogged, up to the bus free time.Suppose to exist bus of thousands of up to a hundred processor contentions, will cause great delay.
Communication requirement when for above-mentioned reasons, the shared bus mode can't satisfy the on-chip processor number and increases.Use for reference interference networks, on sheet, realize solving communication between components problem on the sheet by the network routing node, Here it is network-on-chip.Network-on-chip (NoC-Network On Chip) technology is supported characteristics such as visit simultaneously, reliability height, expansibility be strong with it and is widely used in on-chip multi-processor and interconnects.Router is the main body of network-on-a-chip, generally builds network by router according to certain topological structure, then assembly on each sheet is connected to router and constitutes network-on-a-chip.
Though there is a lot of topological structures in present network-on-chip, two-dimensional plane mesh structure is owing to the simplicity on realizing is widely used.In this structure, each router has 5 ports, and wherein four ports lay respectively at east, south, and the west, northern four direction is used for linking to each other with other router, constitutes the mesh network structure of two dimension, and a remaining port (L) is used to connect local component.Such regular network structure is not difficult to realize on technology, also is easy to the comprehensive and checking in the design process simultaneously.Except that topology of networks and router, give full play to the performance of network-on-chip, improve communication bandwidth, reduce transmission delay, the design of routing algorithm is very important.In order to simplify hardware designs, routing algorithm should be enough simple, and want efficient.In the mesh network, reality is used to such an extent that be the XY routing algorithm more widely.In the mesh two-dimensional network, each routing node all has a two-dimensional address sign.Data are transmitted in network with the form of packet, comprise the destination address of packet in the packet header, i.e. the two-dimensional address of purpose router.Router is by resolving the information in the current packet header, the forwarding and the reception that come the specified data bag in conjunction with the two-dimensional address of router itself.
But the XY routing algorithm is a kind of static routing algorithm, and promptly behind the initial sum termination address of specified data bag, the path of bag transmission just is determined.In such routing decision, the disequilibrium of degree of Congestion is an inevitable problem in the data channel.Such situation appears such as meeting, the right to use of a plurality of packets in request port east arranged in the router, but the partial data bag also can by port north arrive the destination and this moment port north be in idle condition, situation just makes resource fully not to be utilized like this, packet is blocked, the performance that influence is whole.Improved XY routing algorithm with adaptive ability needn't be followed the preferential rule of directions X among the present invention, can be according to the logical congestion situations of current interconnection and vertical passage, Dynamic Selection arrives the suitable passage in destination, thereby reduces the obstruction of packet, improves transmission speed.
Packet in the network is mainly produced by the assembly that is connected on the router, and the destination address of the network interface binding data on the assembly packs the data to packet, and by local router packet is injected network.Packet transmits in network according to the XY algorithm, up to the destination, finishes communication process.
Summary of the invention
Main purpose of the present invention is to overcome the deficiencies in the prior art, proposes a kind of network-on-chip router and its implementation that possesses adaptive routing capability.
The technical scheme that technical solution problem of the present invention adopts is as follows:
The invention provides a kind of network-on-chip router that possesses adaptive routing capability, comprise the inlet flow controller 20, input buffer 22, route moderator 25, o controller 32 and the output stream controller 21 that connect successively; Described input buffer 22 comprises data register bank 24 and a data selector a35 successively, and packet pointer 23 links to each other with data selector a35;
Described route moderator 25 comprises packet register 26, packet header analyzer 27, improved XY router two 8, request of data and the transmitter 29 that connects successively, and packet register 26 also connects request of data and transmitter 29;
Described o controller 32 comprises that wheel changes selector 31 and data selector b45;
Described improved XY router two 8 comprises data selector c55 and data comparator 41.
As a kind of improvement, described improved XY router two 8 has 5 ports, and each port has two data passages, is respectively input channel and output channel.
It is a kind of based on the aforementioned implementation method that possesses the network-on-chip router of adaptive routing capability that the present invention also provides, and may further comprise the steps:
(1) when packets need enters, inlet flow controller 20 detects the potential change on the input request Req holding wire, and inlet flow controller 20 is by the data register bank 24 of State interface querying input buffer 22; If current input buffer 22 is full, then inlet flow controller 20 does not respond the request of data from the outside; If 22 free time of input buffer, then input buffer 22 is put answer signal by the Ack holding wire, finishes the reception of packet; The Ack signal of input buffer 22 is replied outside request signal by inlet flow controller 20, shows that packet receives;
(2) when having not processed packet in the data register bank 24, at first check the Req holding wire between itself and the route moderator 25; If this moment, the Req signal is a high level also, according to Handshake Protocol, shows that the routing procedure of a packet does not finish, and data register bank 24 needs to wait for; If the Req holding wire of this moment is a low level, current 25 free time of route moderator then are described, data register bank 24 set Req holding wires show and exist new data to handle;
(3) after route moderator 25 receives the Req signal, read packet pointer 23 packet pointed in the input buffer 22, and leave in the packet register 26; Send request of data Req via improved XY router two 8, request of data and transmitter 29 to the o controller 32 that will send then; Taking turns when o controller 32 changes when handling current request of data, if output channel free time this moment is then transmitted the packet of packet register 26, and sends out answer signal and gives route moderator 25; Route moderator 25 is received from sending answer signal to input buffer 22 behind the answer signal of o controller 32; Input buffer 22 upgrades packet pointer 23 then, makes it point to next untreated packet.
As a kind of improvement, in the described step (1), when receiving new packet, the untreated packet in current four data registers group 24 can move forward one by one, and new packet is deposited in the position of vacating in the buffer memory afterbody; After receiving, input buffer 22 can upgrade packet pointer 23, makes it point to the most close current buffer memory head and not processed packet.
As a kind of improvement, in the described step (3), the address of data comparator 41 comparing data bags and the address of router, be that packet directions X address is compared with the directions X address of router, the Y direction address of packet is compared with router Y direction address, result's output relatively is used for determining the port of request and the request of data number of corresponding port, determines last request channel by the request of data number of two passages relatively selecting again.
Compared with prior art, the invention has the beneficial effects as follows: by adopting improved XY router, use improved XY routing algorithm, make routing procedure possess certain adaptivity, can be according to the FPDP degree of Congestion, Dynamic Selection suitable data port, the obstruction of minimizing packet, the transmission speed and the throughput of raising network.Adopt modularized design method, can reduce the complexity of design, improve the efficient of functions of modules checking.Interface design between the module has been simplified modular design, and being convenient to can high efficiency interactive between the module.
Description of drawings
Fig. 1 is the structured flowchart of example router of the present invention;
Fig. 2 is data packet format figure;
Fig. 3 is the input buffer circuit diagram;
Fig. 4 is a route moderator structured flowchart;
Fig. 5 is improved XY router circuit figure;
Fig. 6 is the outlet selector structured flowchart.
Embodiment
The present invention proposes router design method on a kind of sheet that possesses adaptive routing capability, be used to make up the network-on-chip communication system.In design router process, adopted structure as shown in Figure 1.The present invention designs processes such as the reception of packet, buffer memory, parsing route, forwardings respectively.
The data packet format that adopts
Adopt following data packet format among the present invention, as shown in Figure 2, comprise the address of directions X, the address of Y direction, four parts of data and data type.Wherein, the data width of X and Y address has determined the size of the network that current router can be supported.For example, if the data width of X and Y is 4, the network of the maximum that current router can be supported is 16 * 16.Data and data type have been determined the content and the attribute of the data of communicating by letter between the end points.
Inlet flow and output stream controller
Stream controller described in the present invention comprises inlet flow controller 20 and output stream controller 21, and design wherein realizes mainly comprising the design of port and the realization of Handshake Protocol.Port in inlet flow and the output stream controller mainly comprises data request signal (Req) and data answering signal (Ack).In addition, inlet flow controller 20 has state and reads in signal (State), is used to read the current state of input-buffer.When new data-signal sent, transmitting terminal was put request signal; Receiving terminal reads new data-signal, writes the data register bank 24 rearmounted answer signals in the input buffer 22, represents that current Data Receiving finishes; After transmitting terminal received answer signal, the cancellation request signal had new data to need to send up to next time again.By, this simple Handshake Protocol can arrive the control data packet transmission rate, reduces to wrap the purpose of loss.
Input buffer
Input buffer 22 of the present invention comprises a packet pointer 23, four data registers group 24 and data selector a35, its structure such as Fig. 3.Register data width in the data register bank 22 is identical with the width of packet, points to the current packet that needs processing by realizing a data pointer; By being set, empty and full two identifiers represent the state that buffer memory is current.
The operating process that input buffer group 22 is concrete is as follows: when in four data registers group 24 being arranged the free time and have new packet to arrive, packet moves forward one by one, and that register of vacating data register bank 24 high order ends receives the packet that newly arrives.Simultaneously, packet pointer 23 can obtain upgrading, and points to the not processed packet of 24 groups of heads of the most close data register bank.When having untreated packet in the data register bank 24, the output request signal is effective all the time.When data register bank 24 was in full state, input buffer 22 was not just receiving new packet, and corresponding packet input channel just is in blocked state.After handling a packet, if also have this moment packet to be untreated, that packet pointer 23 just moves lattice to data register bank 24 left ends, points to new untreated packet.
The route moderator
Route moderator of the present invention comprises packet register 26, packet header analyzer 27, improved XY router two 8, request of data and transmitter 29, as shown in Figure 4.The XY route technology that possesses adaptation function that the present invention proposes, the routing direction of specified data bag sends the data forwarding request to corresponding o controller, realizes routing function.
In order to obtain the congestion condition of current data-out port, the present invention passes through in the current request of data quantity of o controller 32 records, and sends this information to route moderator 25.Route moderator 25 utilizes these information to realize adaptive routing algorithm.
Concrete implementation procedure is as follows:
After packet arrives packet register 26, directions X address and Y direction address that packet header analyzer 27 extracts in the packet.Improved XY router two 8 is by data comparator 55, the address of comparing data bag and the address of router, be that packet directions X address is compared with the directions X address of router, the Y direction address of packet is compared with router Y direction address, result's output relatively is used for definite port of asking, and the request of data number of corresponding port.The request of data number of two passages relatively selecting again, and select wherein to ask the less request port of number.
For example, in one 3 * 3 mesh network, there is a packet to be transferred to node (2,3) from node (1,2).Packet is entered by the local port of router (1,2).According to the XY routing algorithm, packet needs by way of (1,2)-(2,2)-(2,3), need the east mouth output by router, but the request of data number of the east mouth is 3 at this moment; And the request of data number of the North mouth of router is 2 at this moment; By the request of data number of east and northern two-port relatively, it is preferential to get few person, and promptly packet is by the North mouth of router, thereby by arrival destination, path (1,2)-(1,3)-(2,3).
Concrete implementation procedure is as follows: deposit pending packets such as current in the data register bank 24, the address information that packet header analyzer 27 reads in the packet header arrives improved XY router two 8.The structure of improved XY router two 8 as shown in Figure 5, mainly comprises data selector c55 and data comparator 41.Compare with the X address of router in the X address of packet, comparative result is as the foundation that the thing port is selected: if the X address of packet greater than the X address of router, the then selected output of request of data number in port east; The X address is less than router, and the request of data number in port west is selected; If both equate, then are output as 0.Simultaneously, result relatively finishes the selection to port request, and when the X address greater than router, the X address of packet, then the request in port east is effective; Otherwise the port west effectively.
The address process process of Y direction and the processing of above-mentioned directions X are similar.In like manner, router can be selected an active data request in two passages in north and south, and selects the wherein less passage of request of data number.Secondly, compare two data request numbers, in two remaining data requests, select an active data request again according to the output result by data comparator; If the input of two data request numbers all is zero, so just select request to local port.Finished the realization that analyzes routing procedure from packet header by top step.Be exactly the transmission and the forwarding of packet at last.
O controller
O controller of the present invention comprises that wheel changes selector 31 and data selector b45, and structure as shown in Figure 6.Wheel changes selector 31 when selecting pending signal, gives route moderator 25 with answer signal and request number signal feedback, is convenient to 25 decision-makings of route moderator.
Concrete implementation procedure is as follows: wheel changes selector 31 and at first writes down current request quantity, and gives arbitration router two 5 with this data forwarding; Simultaneously, the request of data to current existence adopts the mode of wheel commentaries on classics to handle.
For example, current request of data comprises the request from the east mouth, south mouth and the North mouth.The quantity of current request of data just is 3, changes selector 31 by wheel and preserves this numerical value and it is transmitted to route moderator 25.Wheel changes selector 31 to be handled each request according to the rotational order in east, south, west, north.Suppose that last one-period handles the request in port east, because do not come the request of data of port westerly, that this cycle just handles the request of data of south mouth again.By the order that wheel changes each request of data is handled, thereby guaranteed that each data channel all obtains fair dealing.
In sum, implementation procedure of the present invention can be briefly described as follows:
When packets need entered router, inlet flow controller 20 can detect the potential change on the input request Req holding wire, and inlet flow controller 20 is by the data register bank 24 of State interface querying input input buffer 22.If current input buffer 22 is full, then inlet flow controller 20 does not respond the request of data from the outside; If 22 free time of input buffer, then input buffer 22 is put answer signal by the Ack holding wire, finishes the reception of packet; The Ack signal of input buffer 22 is replied outside request signal by inlet flow controller 20, shows that packet receives.
When receiving new packet, the untreated packet in current four data registers group 24 can move forward one by one, and new packet is deposited in the position of vacating in the buffer memory afterbody.After receiving, data register bank 24 can be upgraded packet pointer 23, makes it point to the most close current buffer memory head and not processed packet.
When having not processed packet in the input buffer 22, input buffer 22 is at first checked the Req holding wire between itself and the route moderator 25; If this moment, the Req signal is a high level also, according to Handshake Protocol, shows that the routing procedure of a packet does not finish, and input buffer 22 needs to wait for.If the Req holding wire of this moment is a low level, current 25 free time of route moderator then are described, input buffer 22 set Req holding wires show and exist new data to handle.
After route moderator 25 receives the Req signal, read packet pointer 23 packet pointed in the input buffer 22, and leave in the packet register 26.Then, send request of data Req via improved XY router two 8, request of data and transmitter 29 to the o controller 32 that will send.Taking turns when o controller 32 changes when handling current request of data, if output channel free time this moment is then transmitted the packet in the packet register 26, and sends out answer signal and gives route moderator 25.Route moderator 25 receives from sending answer signal to input buffer 22 behind the answer signal of o controller 32.Then, input buffer 22 upgrades packet pointer 23, makes it point to next untreated packet.
By the operation of above each assembly and the host-host protocol efficiently between the assembly, realized reception, route and the repeating process of packet.The characteristic of maximum of the present invention has been to propose a kind of improved route technology with adaptive routing capability, can improve network resource utilization, accelerates the transmission speed of packet.
Claims (5)
1, a kind of network-on-chip router that possesses adaptive routing capability comprises the inlet flow controller (20), input buffer (22), route moderator (25), o controller (32) and the output stream controller (21) that connect successively, it is characterized in that:
Described input buffer (22) comprises a data register bank (24) and a data selector a (35) successively, and packet pointer (23) links to each other with data selector a (35);
Described route moderator (25) comprises packet register (26), packet header analyzer (27), improved XY router (28), request of data and the transmitter (29) that connects successively, and packet register (26) also connects request of data and transmitter (29);
(32 comprise that wheel changes selector (31) and data selector b (45) to described o controller;
Described improved XY router (28) comprises data selector c (55) and data comparator (41).
According to the described network-on-chip router that possesses adaptive routing capability of claim 1, it is characterized in that 2, described improved XY router (28) has 5 ports, each port has two data passages, is respectively input channel and output channel.
3, a kind of based on the described implementation method that possesses the network-on-chip router of adaptive routing capability of claim 1, may further comprise the steps:
(1) when packets need enters, inlet flow controller (20) detects the potential change on the input request Req holding wire, and inlet flow controller (20) is by the data register bank (24) of State interface querying input buffer (22); If current input buffer (22) is full, then inlet flow controller (20) does not respond the request of data from the outside; If input buffer (22) free time, then input buffer (22) is put answer signal by the Ack holding wire, finishes the reception of packet; The Ack signal of input buffer (22) is replied outside request signal by inlet flow controller (20), shows that packet receives;
When (2) having not processed packet in the data register bank (24), at first check the Req holding wire between itself and the route moderator (25); If this moment, the Req signal is a high level also, according to Handshake Protocol, shows that the routing procedure of a packet does not finish, and data register bank (24) needs to wait for; If the Req holding wire of this moment is a low level, current route moderator (25) free time then is described, data register bank (24) set Req holding wire shows and exists new data to handle;
(3) after route moderator (25) receives the Req signal, read packet pointer (23) packet pointed in the input buffer (22), and leave in the packet register (26); Send request of data Req via improved XY router (28), request of data and transmitter (29) to the o controller that will send (32) then; When o controller (32) wheel changes when handling current request of data,, and send out answer signal and give route moderator (25) if output channel free time this moment is then transmitted the packet of packet register (26); Route moderator (25) is received from sending answer signal to input buffer (22) behind the answer signal of o controller (32); Input buffer (22) upgrades packet pointer (23) then, makes it point to next untreated packet.
4, according to the described implementation method that possesses the network-on-chip router of adaptive routing capability of claim 3, it is characterized in that, in the described step (1), when receiving new packet, untreated packet in current four data registers group (24) can move forward one by one, and new packet is deposited in the position of vacating in the buffer memory afterbody; After receiving, input buffer (22) can upgrade packet pointer (23), makes it point to the most close current buffer memory head and not processed packet.
5, according to the described implementation method that possesses the network-on-chip router of adaptive routing capability of claim 3, it is characterized in that, in the described step (3), the address of data comparator (41) comparing data bag and the address of router, be that packet directions X address is compared with the directions X address of router, the Y direction address of packet is compared with router Y direction address, result's output relatively is used for determining the port of request and the request of data number of corresponding port, determines last request channel by the request of data number of two passages relatively selecting again.
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| CN105871742B (en) * | 2016-03-24 | 2018-12-21 | 合肥工业大学 | Adaptive router based on virtual output queue mechanism in a kind of network-on-chip |
| CN111382115A (en) * | 2018-12-28 | 2020-07-07 | 北京灵汐科技有限公司 | Path creating method and device for network on chip and electronic equipment |
| US11398981B2 (en) | 2018-12-28 | 2022-07-26 | Lynxi Technologies Co., Ltd. | Path creation method and device for network on chip and electronic apparatus |
| CN111382115B (en) * | 2018-12-28 | 2022-04-15 | 北京灵汐科技有限公司 | Path creating method and device for network on chip and electronic equipment |
| WO2020177249A1 (en) * | 2019-03-04 | 2020-09-10 | 上海熠知电子科技有限公司 | Virtual channel-based operation unit sharing method and system |
| CN110191023A (en) * | 2019-05-31 | 2019-08-30 | 北京金山云网络技术有限公司 | Newly-built connection number test method, device, electronic equipment, storage medium and system |
| CN110413562A (en) * | 2019-06-26 | 2019-11-05 | 北京全路通信信号研究设计院集团有限公司 | A kind of synchronization system and method with adaptation function |
| CN110413562B (en) * | 2019-06-26 | 2021-09-14 | 北京全路通信信号研究设计院集团有限公司 | Synchronization system and method with self-adaptive function |
| CN110351192A (en) * | 2019-08-15 | 2019-10-18 | 电子科技大学 | A kind of multi-level optional compound route control method of dynamic towards network-on-chip |
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| CN101488922B (en) | 2011-01-26 |
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