CN101482857A - Information transfer system and information transfer method - Google Patents
Information transfer system and information transfer method Download PDFInfo
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- CN101482857A CN101482857A CNA2008100013453A CN200810001345A CN101482857A CN 101482857 A CN101482857 A CN 101482857A CN A2008100013453 A CNA2008100013453 A CN A2008100013453A CN 200810001345 A CN200810001345 A CN 200810001345A CN 101482857 A CN101482857 A CN 101482857A
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Abstract
The present invention provides an information transmission system and an information transmission method thereof. The information transmission system comprises a management processor; a storing processor; an inner integrated circuit bus which is connected with the management processor and the storing processor and provides the information transmission between the management processor and the storing processor; and a general input/output interface which is connected with the management processor and the storing processor and provides the confirmation of information receiving between the management processor and the storing processor. Thus the management processor transmits information to the storing processor continuously until the successfully and correctly information receiving by the storing processor is obtained. The storing processor waits for the information from the management processor and transmits confirmation information to the management processor after successfully and correctly receiving the information.
Description
Technical field
The present invention relates to a kind of information transfer system and information transmitting methods, relate in particular to a kind of information transfer system and information transmitting methods that can be applicable in the magnetic sheet storage architecture.
Background technology
In the magnetic sheet storage system, the general common framework that is to use dual processor: a storage of processor is used to realize the storage protocol of magnetic sheet and the processing of information I/O.One management processor to peripheral element for example is used for, the management of nonvolatile memory (EEPROM) etc.In a lot of the application, customizing messages need be kept in the peripheral equipment, so that upgrade, and these customizing messages needed information when to be the storage protocol of magnetic sheet or information I/O usually handle.In the aforesaid described customizing messages, concrete example is world name (World Wide Name widely; WWN).WWN is the sign mark that is used in unique identification storage of processor in the storage networking, and it has two specific characters: on the one hand, it is relatively-stationary, and on the other hand, it needs to revise under certain conditions.In case system start-up is up to revising and restarting, with the WWN that uses this time.For ease of revising, usually WWN is kept in the peripheral equipment of storage of processor, for example nonvolatile memory (EEPROM).
Yet, in the framework of dual processor, use the above-mentioned WWN information of putting forward if desired, but there is not a kind of effective dual processor information transmission technique, then peripheral equipment can only be divided into two classes handles, one class is received on the storage of processor for the peripheral equipment that will preserve above-mentioned customizing messages, and another kind of other peripheral equipment is received on the management processor.And peripheral equipment is divided into the mode that two classes are handled, obviously run counter to the exclusive purpose of design that is used for the peripheral equipment management of management processor.
Therefore, management processor needs by passing interface at the beginning of system start-up, and efficient and correct storage of processor is operated gone up needed information and be passed to storage of processor.And, after storage of processor is finished reception information, need to reply management processor by passing interface.
Summary of the invention
The present invention discloses an information transfer system and information transmitting methods, uses in the magnetic sheet storage architecture.At the beginning of the information transfer system started, the needed information of the storage of processor in the magnetic sheet storage architecture will correctly be delivered to storage of processor by management processor.
The information transfer system of the present invention includes a management processor, a storage of processor, an internal integrated circuit (I2C) bus and general I/O (GPIO) interface.Between two processors of management processor and storage of processor, be connected with a GPIO interface by an I2C bus.Wherein the I2C bus is used for two information transmission between the processor, and the GPIO interface is used for the affirmation of message pick-up.In information transfer system start-up course of the present invention, management processor constantly sends information by the I2C bus to storage of processor, learns that by the GPIO interface storage of processor success correctly receives information, just continues the execution of back up to it.Simultaneously, in information transfer system start-up course of the present invention, storage of processor should only after success correctly receives information, just continue the logic of back by the information of I2C bus wait from management processor.Information in aforementioned can be world name (WorldWide Name widely; WWN), medium access control (Media Access Control; MAC) address, verify data or out of Memory.In addition, can comprise contents such as check code in the information, in order to guarantee the correctness of information.
Information transmitting methods of the present invention is applicable in the aforesaid information transfer system, its step is as follows: at first, management processor is written into MOS, this MOS meeting initialization management processor, make it become an I2C bus master controller, in addition, storage of processor is written into storage operating system, this storage operating system meeting initialization storage of processor, make it become an I2C bus slave, and will be used for a local parameter of the information of preserving and be initialized as an invalid value of information (INVALID_INFO_VALUE).Then, management processor is read an information from peripheral element (storer), and this information is write storage of processor by an I2C bus.Then, judge whether success and correctly received and transmit information in the past of storage of processor by a GPIO interface, if success as yet, then management processor continues information is write storage of processor, otherwise if success, then management processor continues the logic execution of its back.
From peripheral element (storer) sense information, and after information being write the step of storage of processor, storage of processor can judge whether the information that this part parameter preserved is effective at aforementioned management processor.In aforementioned, if invalid, the register of storage of processor inquiry I2C bus then, and information wherein read in the local parameter, and then judge whether the information that this part parameter preserved is effective.Otherwise if effectively, storage of processor is informed management processor by the GPIO interface, information success and correctly receiving, and the logic that continues the back is carried out.
So, the information transfer system of the present invention is in start-up course, and management processor is by the management peripheral element, and constantly sends the information stored in peripheral element to storage of processor, therefore, the present invention has met the exclusive purpose of design that is used for the peripheral element management of management processor.Simultaneously, after storage of processor is finished reception information, reply management processor, and reach the correctness that data transmit by passing interface.
Above general introduction and ensuing detailed description are exemplary in nature all, are in order to further specify claim of the present invention.And about other purpose of the present invention and advantage, will be set forth in follow-up explanation and accompanying drawing.
Description of drawings
Fig. 1 is a systematic square frame synoptic diagram of the present invention; And
Fig. 2 A and Fig. 2 B are information transmitting methods schematic flow sheet of the present invention.
Wherein, description of reference numerals is as follows:
10 management processors
12 storage of processor
14 internal integrate circuit bus (I2C)
16 general input/output interfaces (GPIO)
11 first flash memories
110 MOSs
13 second flash memories
130 storage operating systems
18 peripheral elements
Embodiment
Please refer to Fig. 1, Fig. 1 is a systematic square frame synoptic diagram of the present invention.The information transfer system of the present invention comprises a management processor 10 and a storage of processor 12, is connected with 14 and general input/output interfaces of an internal integrate circuit bus (I2C) (GPIO) 16 between management processor 10 and storage of processor 12 at least.In aforementioned, at the general input/output interface (GPIO) 16 that is connected between management processor 10 and the storage of processor 12, storage of processor 12 is the output terminal of general input/output interface (GPIO) 16, and management processor 10 is the input end of general input/output interface (GPIO) 16.In addition, at the internal integrate circuit bus (I2C) 14 that is connected between management processor 10 and the storage of processor 12, management processor 10 is the main control end of internal integrate circuit bus (I2C) 14, and storage of processor 12 is the controlled end of internal integrate circuit bus (I2C) 14.
Refer again to Fig. 1, the information transfer system of the present invention also includes one first flash memory 11 and one second flash memory 13.Wherein, first flash memory, 11 connection management processors 10 are used to preserve a MOS 110.Second flash memory 13 connects storage of processor 12, is used to preserve a storage operating system 130.Simultaneously, when the information transfer system of the present invention starts, MOS 110 and storage operating system 130 can be loaded into respectively in the internal storage (RAM) of management processor 10 and storage of processor 12, and independently bring into operation in management processor 10 and storage of processor 12.
Refer again to Fig. 1, the information transfer system of the present invention also includes a peripheral element 18, and peripheral element 18 can be connected to management processor 10 by a transmission interface (not shown), and wherein transmission interface can be regional bus or internal integrate circuit bus (I2C).Aforesaid peripheral element 18 is a nonvolatile memory (EEPROM), is used for preserving the needed information of these storage of processor 12 operations.And this is kept at the information in the peripheral element 18, need pass to storage of processor 12 from management processor 10 at the beginning of the information transfer system of the present invention starts.
Refer again to Fig. 1, in the information transfer system of the present invention, internal integrate circuit bus (I2C) 14 is used for the information transmission between management processor 10 and the storage of processor 12, and general input/output interface (GPIO) 16 is used for the affirmation of message pick-up.In information transfer system start-up course of the present invention, management processor 10 is obtained the required information of storage of processor 12 operations from peripheral element 18, and constantly send this information to storage of processor 12 by internal integrate circuit bus (I2C) 14, learn that by general input/output interface (GPIO) 16 storage of processor 12 success correctly receives information up to management processor 10, just stop to send this information, and continue the logic execution of back.
In addition, in information transfer system start-up course of the present invention, storage of processor 12 should be passed through the information that internal integrate circuit bus (I2C) 14 is waited for from management processor 10, only after success correctly receives information, just stop to receive this information, and continue the logic execution of back.Information in aforementioned can be world name (World Wide Name widely; WWN), medium access control (Media Access Control; MAC) address, verify data or out of Memory.In addition, can comprise check code in the information, in order to guarantee the correctness of information.
Please refer to Fig. 2 A and Fig. 2 B, be information transmitting methods schematic flow sheet of the present invention.Fig. 2 A has disclosed the operating process of management processor of the present invention, and Fig. 2 B has then disclosed the operating process of storage of processor of the present invention.Information transmitting methods of the present invention is applicable to the aforesaid information transfer system, when the aforesaid information transfer system tentatively starts, general input/output interface (GPIO) 16 should be for judging the state of (de-asserted), and storage of processor 12 then has been scheduled to a controlled end address of internal integrate circuit bus (I2C) 14.
Cooperate Fig. 1, refer again to Fig. 2 A and Fig. 2 B, its step is as follows: at first, management processor 10 is written into MOS 110, these MOS 110 meeting initialization management processors 10, make it become an I2C bus master controller, see step S10, in addition, storage of processor 12 is written into storage operating system 130, these storage operating system 130 meeting initialization storage of processor 12, make it become an I2C bus slave, see step S11, and will be used for a local parameter of the information of preserving and be initialized as an invalid value of information, see step S13.
Then, management processor 10 is read an information from peripheral element 18 (storer), and this information is write storage of processor 12 by internal integrate circuit bus (I2C) 14, sees step S12.Then, judge whether success and correctly received the information in the past that transmits of storage of processor 12 by general input/output interface (GPIO) 16, see step S14, if not success as yet, then management processor 10 continues information is write storage of processor 12, sees step S12, otherwise, if success, then management processor 10 continues the logic execution of its back, sees step S16.
Behind step S13, storage of processor 12 can judge whether the information that this part parameter preserved is effective, sees step S15.In aforementioned, if the information that local parameter is preserved is invalid, then storage of processor 12 is inquired about the register (not shown) of internal integrate circuit bus (I2C) 14, and the information of inciting somebody to action wherein reads in the local parameter (not shown), see step S17, and then judge whether the information that this part parameter preserved is effective, sees step S15.Otherwise, if the information that local parameter is preserved is that effectively then storage of processor 12 is informed management processor 10 by general input/output interface (GPIO) 16, information the success and correctly receive, see step S18, and continue the logic execution of back, see step S19.
In sum, the information transfer system of the present invention has comprised management processor, storage of processor and peripheral element.Between two processors of management processor and storage of processor, be connected with general input/output interface (GPIO) by internal integrate circuit bus (I2C), wherein internal integrate circuit bus (I2C) is used for two information transmission between the processor, and general input/output interface (GPIO) is used for the affirmation of message pick-up.So, in information transfer system start-up course of the present invention, management processor constantly sends information to storage of processor, learns that up to it storage of processor success correctly receives information, just continues the execution of back.And storage of processor should be waited for the information from management processor, only after success correctly receives information, just continues the logic of back.
Press, the above, only for the preferred specific embodiment of the present invention, but feature of the present invention is not limited thereto, the those skilled in the art in the field of the invention, can think easily and variation or modification, all can be encompassed in the claim scope of the present invention.
Claims (15)
1. an information transfer system is characterized in that, includes:
One management processor;
One storage of processor;
One internal integrate circuit bus is connected in this management processor and this storage of processor, and this internal integrate circuit bus provides the transmission of information between this management processor and this storage of processor; And
One general input/output interface is connected in this management processor and this storage of processor, and this general input/output interface provides the affirmation of message pick-up between this management processor and this storage of processor.
2. the information transfer system as claimed in claim 1 is characterized in that, also comprises a peripheral element, and this peripheral element is connected in this management processor by a transmission interface, and this peripheral element is preserved and wanted the information transmitted.
3. the information transfer system as claimed in claim 2 is characterized in that, this peripheral element is a nonvolatile memory.
4. the information transfer system as claimed in claim 3 is characterized in that, this transmission interface is a regional bus or an internal integrate circuit bus.
5. the information transfer system as claimed in claim 2 is characterized in that, also comprises one first flash memory, and this first flash memory connection management processor is used to preserve a MOS.
6. the information transfer system as claimed in claim 5 is characterized in that, also comprises one second flash memory, and this second flash memory connects storage of processor, is used to preserve a storage operating system.
7. information transmitting methods is characterized in that step comprises:
A. initialization one management processor makes it become an I2C bus master controller;
B. initialization one storage of processor makes it become an I2C bus slave, and a local parameter of this storage of processor of initialization;
C. this management processor is write this storage of processor with an information by an internal integrate circuit bus; And
D. this management processor judges by a general input/output interface whether this storage of processor successfully receives this information.
8. information transmitting methods as claimed in claim 7 is characterized in that, before a step, also comprises a MOS is written into step in this management processor.
9. information transmitting methods as claimed in claim 8 is characterized in that, before the b step, also comprises a storage operating system is written into step in this storage of processor.
10. information transmitting methods as claimed in claim 9 is characterized in that, in the c step, this management processor is read this information from a peripheral element, and this information is write this storage of processor by this I2C bus.
11. whether effectively information transmitting methods as claimed in claim 10 is characterized in that, after the c step, also comprise information that this storage of processor judges that this part parameter preserved c1 step.
12. information transmitting methods as claimed in claim 11, it is characterized in that, after the c1 step, if the information of should the part parameter being preserved is invalid, then this storage of processor is inquired about a register of this internal integrate circuit bus, and the fresh information in this register read in this part parameter, and then get back to the c1 step and judge.
13. information transmitting methods as claimed in claim 11, it is characterized in that, after the c1 step, if the information of should the part parameter being preserved is effective, then this storage of processor is informed this management processor by this general input/output interface, this information successfully receives, and continues the logic execution of back.
14. information transmitting methods as claimed in claim 10, it is characterized in that, in the d step, if this storage of processor does not receive this information as yet, then this management processor continues this information is write this storage of processor, otherwise if successfully receive this information, then this management processor continues the logic execution of its back.
15. information transmitting methods as claimed in claim 14 is characterized in that, this information is world's name, medium access control address, verify data or out of Memory widely, and this information also comprises a check code.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100013453A CN101482857A (en) | 2008-01-09 | 2008-01-09 | Information transfer system and information transfer method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100013453A CN101482857A (en) | 2008-01-09 | 2008-01-09 | Information transfer system and information transfer method |
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| CN101482857A true CN101482857A (en) | 2009-07-15 |
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| CNA2008100013453A Pending CN101482857A (en) | 2008-01-09 | 2008-01-09 | Information transfer system and information transfer method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102262572A (en) * | 2011-07-19 | 2011-11-30 | 浙江大学 | Inter integrated circuit (IIC) bus interface controller with cyclic redundancy checking (CRC) function |
| CN105843549A (en) * | 2014-11-13 | 2016-08-10 | 旺宏电子股份有限公司 | Memory device and method for implementing an error detection protocol |
-
2008
- 2008-01-09 CN CNA2008100013453A patent/CN101482857A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102262572A (en) * | 2011-07-19 | 2011-11-30 | 浙江大学 | Inter integrated circuit (IIC) bus interface controller with cyclic redundancy checking (CRC) function |
| CN102262572B (en) * | 2011-07-19 | 2013-05-08 | 浙江大学 | Inter integrated circuit (IIC) bus interface controller with cyclic redundancy checking (CRC) function |
| CN105843549A (en) * | 2014-11-13 | 2016-08-10 | 旺宏电子股份有限公司 | Memory device and method for implementing an error detection protocol |
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Open date: 20090715 |