CN101478515B - Amplitude offset key system demodulator and wireless radio frequency identification system - Google Patents

Amplitude offset key system demodulator and wireless radio frequency identification system Download PDF

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CN101478515B
CN101478515B CN 200910005510 CN200910005510A CN101478515B CN 101478515 B CN101478515 B CN 101478515B CN 200910005510 CN200910005510 CN 200910005510 CN 200910005510 A CN200910005510 A CN 200910005510A CN 101478515 B CN101478515 B CN 101478515B
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CN101478515A (en
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李原江
游岳华
陈怡然
李宇轩
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AUO Corp
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Abstract

本发明公开了一种振幅偏移键制解调器及无线射频辨识系统。该振幅偏移键制解调器包括信号输入端子组、输入整流电路、电流镜电路、输出级电路及低通滤波电路。输入整流电路电性耦接至信号输入端子组以对一交流输入信号进行全波整流操作，其由两个以上电性耦接的晶体管组成且每一晶体管采用其栅极不与源极及漏极相耦接的连接方式。电流镜电路电性耦接至输入整流电路并根据流经输入整流电路的一输入电流而产生一镜像电流。输出级电路电性耦接至电流镜电路以根据镜像电流产生一输出电流。低通滤波电路耦接至输出级电路以对输出电流进行低通滤波操作而产生一解调封包信号。

Figure 200910005510

The invention discloses an amplitude shift key demodulator and a radio frequency identification system. The amplitude shift key demodulator includes a signal input terminal group, an input rectification circuit, a current mirror circuit, an output stage circuit and a low-pass filter circuit. The input rectification circuit is electrically coupled to the signal input terminal group to perform a full-wave rectification operation on an AC input signal, which is composed of more than two electrically coupled transistors, and each transistor uses its gate not connected to the source and drain. pole phase coupling connection. The current mirror circuit is electrically coupled to the input rectification circuit and generates a mirror current according to an input current flowing through the input rectification circuit. The output stage circuit is electrically coupled to the current mirror circuit to generate an output current according to the mirror current. The low-pass filter circuit is coupled to the output stage circuit to perform low-pass filter operation on the output current to generate a demodulated packet signal.

Figure 200910005510

Description

Amplitude offset key system demodulator and radio frequency identification system
Technical field
The invention relates to wireless communication field, and particularly relevant for a kind of amplitude offset key system demodulator and adopt the radio frequency identification system of this kind amplitude offset key system demodulator.
Background technology
Flourish along with the fast development of wireless communication needs and broadband wireless network, (Radio Frequency Identification, RFID) system becomes a very popular topic to radio frequency identification in recent years.Radio frequency identification system is to the shortcoming of traditional contact system; Utilize the radio wave mode to transmit numerical data; Therefore but inductor does not need to contact just Data transmission with receiver, reduces the device loss that is caused because of contact and has promoted the convenience that uses.In addition, if can do to combine with present display industry simultaneously, directly be integrated on the display, its application certainly will be extensive with more.
Therefore, on the one hand, how to design the demodulator of a kind of permission than the input signal of short arc, it can be fit to the less system of its input signal of wireless related application (for example radio frequency identification system); On the other hand, how to design a kind of radio frequency identification system, it can be integrated in employing, and (Low Temperature Poly-Silicon LTPS) on the display of this high threshold voltage processing procedure, is present problem demanding prompt solution as the low temperature compound crystal silicon.
Summary of the invention
A purpose of the present invention is providing a kind of amplitude offset key system demodulator exactly, thereby it allows to be fit to the less system of its input signal of wireless related application than the input signal of short arc.
A purpose more of the present invention provides a kind of radio frequency identification system, and it can be integrated on the display.
One embodiment of the invention proposes a kind of amplitude offset key system demodulator, is suitable for demodulation one ac input signal and produces a demodulation package signal; This amplitude offset key system demodulator comprises a signal input terminal group, an input rectification circuit, a current mirroring circuit, an output-stage circuit and a low-pass filter circuit.The signal input terminal group comprises a first input end and one second input, this ac input signal of signal input terminal group of received.Input rectification circuit is electrically coupled to the signal input terminal group this ac input signal is carried out full-wave rectification operation; Wherein, the input rectification circuit transistor and each transistor that comprise two above phase electric property couplings adopts its grid not to be present in the input rectification circuit with the connected mode that source electrode and drain electrode couple mutually.Current mirroring circuit is electrically coupled to input rectification circuit, and produces an image current according to an input current of the input rectification circuit of flowing through.Output-stage circuit is electrically coupled to current mirroring circuit receiving image current, and output-stage circuit also produces an output current according to image current.Low-pass filter circuit is electrically coupled to output-stage circuit to receive output current, and low-pass filter circuit makes output current through producing this demodulation package signal after the low-pass filtering operation.
In an embodiment of the present invention, above-mentioned input rectification circuit comprises one the one N transistor npn npn, one the 2nd N transistor npn npn, one the one P transistor npn npn and one the 2nd P transistor npn npn.The one N transistor npn npn has grid, first source/drain electrode and second source/drain electrode, and the grid of a N transistor npn npn receives one first control voltage, and first source/drain electrode of a N transistor npn npn is electrically coupled to above-mentioned first input end.The 2nd N transistor npn npn has grid, first source/drain electrode and second source/drain electrode, and the grid of the 2nd N transistor npn npn receives the first control voltage, and first source/drain electrode of the 2nd N transistor npn npn is electrically coupled to the second above-mentioned input.The one P transistor npn npn has grid, first source/drain electrode and second source/drain electrode, and the grid of a P transistor npn npn receives one second control voltage, and first source/drain electrode of a P transistor npn npn is electrically coupled to above-mentioned first input end.The 2nd P transistor npn npn has grid, first source/drain electrode and second source/drain electrode, and the grid of the 2nd P transistor npn npn receives the second control voltage, and first source/drain electrode of the 2nd P transistor npn npn is electrically coupled to the second above-mentioned input.
In an embodiment of the present invention, above-mentioned amplitude offset key system demodulator also comprises a bias circuit, and this bias circuit comprises one first current source, one the 3rd N transistor npn npn, one second current source and one the 3rd P transistor npn npn.One end of first current source is electrically coupled to one first operating voltage, and the other end is electrically coupled to the grid of a N transistor npn npn.The 3rd N transistor npn npn has grid, first source/drain electrode and second source/drain electrode; The grid of the 3rd N transistor npn npn and second source/drain electrode are electrically coupled to the grid of a N transistor npn npn, and first source/drain electrode of the 3rd N transistor npn npn is electrically coupled to one first bias voltage.One end of second current source is electrically coupled to one second operating voltage, and the other end is electrically coupled to the grid of a P transistor npn npn.The 3rd P transistor npn npn has grid, first source/drain electrode and second source/drain electrode; The grid of the 3rd P transistor npn npn and second source/drain electrode are electrically coupled to the grid of a P transistor npn npn, and first source/drain electrode of the 3rd P transistor npn npn is electrically coupled to first bias voltage.
In an embodiment of the present invention, above-mentioned current mirroring circuit comprises one the 4th P transistor npn npn, one the 4th N transistor npn npn, one the 5th P transistor npn npn and one the 5th N transistor npn npn.The 4th P transistor npn npn has grid, first source/drain electrode and second source/drain electrode; The grid of the 4th P transistor npn npn and second source/drain electrode are electrically coupled to second source/drain electrode of first and second N transistor npn npn, and first source/drain electrode of the 4th P transistor npn npn is electrically coupled to one first operating voltage.The 4th N transistor npn npn has grid, first source/drain electrode and second source/drain electrode; The grid of the 4th N transistor npn npn and second source/drain electrode are electrically coupled to second source/drain electrode of first and second P transistor npn npn, and first source/drain electrode of the 4th N transistor npn npn is electrically coupled to one second operating voltage.The 5th P transistor npn npn has grid, first source/drain electrode and second source/drain electrode; The grid of the 5th P transistor npn npn is electrically coupled to the grid of the 4th P transistor npn npn; First source/drain electrode of the 5th P transistor npn npn is electrically coupled to first operating voltage, and second source/drain electrode of the 5th P transistor npn npn is electrically coupled to output-stage circuit so that image current to be provided.The 5th N transistor npn npn has grid, first source/drain electrode and second source/drain electrode; The grid of the 5th N transistor npn npn is electrically coupled to the grid of the 4th N transistor npn npn; First source/drain electrode of the 5th N transistor npn npn is electrically coupled to second operating voltage, and second source/drain electrode of the 5th N transistor npn npn is electrically coupled to output-stage circuit.
In an embodiment of the present invention, above-mentioned output-stage circuit comprises one the 6th P transistor npn npn, one the 7th P transistor npn npn, one the 8th P transistor npn npn and one the 9th P transistor npn npn.The 6th P transistor npn npn has grid, first source/drain electrode and second source/drain electrode, and first source/drain electrode of the 6th P transistor npn npn is electrically coupled to first operating voltage.The 7th P transistor npn npn has grid, first source/drain electrode and second source/drain electrode; First source/drain electrode of the 7th P transistor npn npn is electrically coupled to first operating voltage; The grid of the 7th P transistor npn npn is electrically coupled to the grid of the 6th P transistor npn npn, and second source/drain electrode of the 7th P transistor npn npn is electrically coupled to second source/drain electrode of the 5th P transistor npn npn.The 8th P transistor npn npn has grid, first source/drain electrode and second source/drain electrode; The grid of the 8th P transistor npn npn is electrically coupled to one second bias voltage; First source/drain electrode of the 8th P transistor npn npn is electrically coupled to second source/drain electrode of the 6th P transistor npn npn, and second source/drain electrode of the 8th P transistor npn npn is electrically coupled to second source/drain electrode of the grid and the 5th N transistor npn npn of the 6th P transistor npn npn.The 9th P transistor npn npn has grid, first source/drain electrode and second source/drain electrode; The grid of the 9th P transistor npn npn is electrically coupled to second bias voltage; First source/drain electrode of the 9th P transistor npn npn is electrically coupled to second source/drain electrode of the 7th P transistor npn npn, and second source/drain electrode of the 9th P transistor npn npn is electrically coupled to low-pass filter circuit so that output current to be provided.
The present invention also proposes a kind of radio frequency identification system, comprising: a wireless receiving module, an above-mentioned amplitude offset key system demodulator and a processing module.Wireless receiving module receives a radio frequency signal, and converts radio frequency signal into a corresponding ac input signal; Amplitude offset key system demodulator is electrically coupled to wireless receiving module to receive ac input signal and then to produce a demodulation package signal; Processing module is electrically coupled to amplitude offset key system demodulator with receiving demodulation package signal, and processing module is carried out corresponding operation according to demodulation package signal.
In an embodiment of the present invention, above-mentioned radio frequency identification system more comprises a display module, and this display module shows the content that is comprised in the demodulation package signal according to the control of processing module.
The amplitude offset key system demodulator that the embodiment of the invention proposes; Its input rectification circuit adopts the transistor of two above phase electric property couplings to carry out the rectification operation, and each transistor adopts its grid not to be present in the input rectification circuit with the connected mode that source electrode and drain electrode couple mutually; So can not adopt the diode framework to carry out the rectification operation, bring pressure drop thereby can reduce diode.Therefore, the amplitude offset key system demodulator that the embodiment of the invention proposes allows the input signal than short arc, thereby can be fit to the less system of its input signal of wireless related application (for example, radio frequency identification system); In addition, this kind input rectification circuit is because of adopting way of full-wave rectification, and the demodulation package signal of output has less ripple problem (Ripple Issue).Further; Because the amplitude offset key system demodulator that the embodiment of the invention proposes can reduce diode and bring pressure drop; In the processing procedure of low temperature compound crystal silicon; This circuit can bring effect preferably, and the signal of avoiding importing into is because of decaying through diode drop, so adopt the radio frequency identification system of this kind amplitude offset key system demodulator can be integrated on the display of employing as this high threshold voltage processing procedure of low temperature compound crystal silicon.
Description of drawings
Fig. 1 is the structure calcspar of a kind of radio frequency identification system of embodiment of the invention proposition;
Fig. 2 is the circuit structure diagram of a kind of amplitude offset key system demodulator of embodiment of the invention proposition.
Wherein, Reference numeral:
10: wireless receiving module 20: amplitude offset key system demodulator
30: processing module 40: display module
21: signal input terminal group 22: input rectification circuit
23: bias circuit 24: current mirroring circuit
25: output-stage circuit 26: low-pass filter circuit
Xc: ac input signal V E0: demodulation package signal
V G1, V G2: bias voltage V C1, V C2: control voltage
VDD, VSS: operating voltage I E0: output current
I B1, I B2: current source
M 1, M 3, M B1, M 5, M 7: the N transistor npn npn
M 2, M 4, M B2, M 6, M 8~ M 12: the P transistor npn npn
R: resistance C: electric capacity
Embodiment
Referring to Fig. 1 and Fig. 2, a kind of radio frequency identification system 100 that one embodiment of the invention proposes, it comprises: wireless receiving module 10, amplitude offset key system demodulator 20, processing module 30 and display module 40.Wireless receiving module 10 receives a radio frequency signal (not shown) and converts radio frequency signal into corresponding ac input signal Xc (as shown in Figure 2); Amplitude offset key system demodulator 20 is electrically coupled to wireless receiving module 10 with reception ac input signal Xc, and demodulation ac input signal Xc is to produce demodulation package signal V E0(as shown in Figure 2); Processing module 30 is electrically coupled to amplitude offset key system demodulator 20 with receiving demodulation package signal V E0, processing module 30 is according to demodulation package signal V E0And carry out corresponding operation; Display module 40 shows demodulation package signal V according to the control of processing module 30 E0In the content that comprised.
To combine Fig. 2 to specifically describe a kind of circuit structure configuration of amplitude offset key system demodulator 20 below; As shown in Figure 2, amplitude offset key system demodulator 20 comprises: signal input terminal group 21, input rectification circuit 22, bias circuit 23, current mirroring circuit 24, output-stage circuit 25 and low-pass filter circuit 26.
Wherein, signal input terminal group 21 comprises just (+) input and negative (-) input and be used to receive ac input signal Xc.
Transistor and each transistor that input rectification circuit 22 comprises two above phase electric property couplings adopt its grid not to be present in the input rectification circuit 22 with the connected mode that source electrode and drain electrode couple mutually, and input rectification circuit 22 produces input current (not shown) a to current mirroring circuit 24 according to the ac input signal Xc of signal input terminal group 21 inputs.Particularly, in the present embodiment, input rectification circuit 22 comprises N transistor npn npn M 1, M 3And P transistor npn npn M 2, M 4N transistor npn npn M 1Have grid, source electrode and drain electrode; N transistor npn npn M 1Grid receive control voltage V C1, its source electrode is electrically coupled to the positive input terminal of signal input terminal group 21.N transistor npn npn M 3Have grid, source and drain electrode; N transistor npn npn M 3Grid receive control voltage V C1, its source electrode is electrically coupled to the negative input end of signal input terminal end 21.P transistor npn npn M 2Have grid, source electrode and drain electrode; P transistor npn npn M 2Grid receive control voltage V C2, its source electrode is electrically coupled to the positive input terminal of signal input terminal group 21.P transistor npn npn M 4Have grid, source electrode and drain electrode; P transistor npn npn M 4Grid receive control voltage V C2, its source electrode is electrically coupled to the negative input end of signal input terminal group 21.
Bias circuit 23 is in order to provide control voltage V to input rectification circuit 22 C1And V C2Particularly, in the present embodiment, bias circuit 23 comprises current source I B2, N transistor npn npn M B1, current source I B1And P transistor npn npn M B2Current source I B2An end be electrically coupled to operating voltage VDD, the other end is electrically coupled to N transistor npn npn M 1Grid.N transistor npn npn M B1Have grid, source electrode and drain electrode, and be present in the bias circuit 23 with diode connected mode (that is grid couples with drain electrode or source electrode mutually); N transistor npn npn M B1Grid be electrically coupled to the grid of N transistor npn npn M1 with drain electrode, its source electrode is electrically coupled to bias voltage V G1Current source I B1An end be electrically coupled to operating voltage VSS, the other end is electrically coupled to P transistor npn npn M 2Grid.P transistor npn npn M B2Have grid, source electrode and drain electrode, and be present in the bias circuit 23 with the diode connected mode; P transistor npn npn M B2Grid and drain electrode be electrically coupled to P transistor npn npn M 2Grid, its source electrode is electrically coupled to bias voltage V G1
Current mirroring circuit 24 is electrically coupled to input rectification circuit 22, and produces an image current (not shown) according to the input current of the input rectification circuit 22 of flowing through.Particularly, in the present embodiment, current mirroring circuit 24 comprises: P transistor npn npn M 6, N transistor npn npn M 5, P transistor npn npn M 8And N transistor npn npn M 7P transistor npn npn M 6Have grid, source electrode and drain electrode; P transistor npn npn M 6Grid and drain electrode be electrically coupled to N transistor npn npn M1 and M 3Drain electrode, its source electrode is electrically coupled to operating voltage VDD.N transistor npn npn M 5Have grid, source electrode and drain electrode; N transistor npn npn M 5Grid and drain electrode be electrically coupled to P transistor npn npn M 2And M 4Drain electrode, its source electrode is electrically coupled to operating voltage VSS.P transistor npn npn M 8Have grid, source electrode and drain electrode; P transistor npn npn M 8Grid be electrically coupled to P transistor npn npn M 6Grid, its source electrode is electrically coupled to operating voltage VDD, its drain electrode is electrically coupled to output-stage circuit 25 so that image current to be provided.N transistor npn npn M 7Have grid, source electrode and drain electrode; N transistor npn npn M 7Grid be electrically coupled to N transistor npn npn M 5Grid, its source electrode is electrically coupled to operating voltage VSS, its drain electrode is electrically coupled to output-stage circuit 25.
Output-stage circuit 25 is electrically coupled to current mirroring circuit 24 with the reception image current, and produces an output current I according to image current E0Particularly, in the present embodiment, output-stage circuit 25 comprises P transistor npn npn M 9, M 10, M 11And M 12P transistor npn npn M 9Have grid, source electrode and drain electrode; P transistor npn npn M 9Source electrode be electrically coupled to operating voltage VDD.P transistor npn npn M 10Have grid, source electrode and drain electrode; The source electrode of P transistor npn npn M10 is electrically coupled to operating voltage VDD, and its grid is electrically coupled to P transistor npn npn M 9Grid, and its drain electrode is electrically coupled to P transistor npn npn M 8Drain electrode.P transistor npn npn M 11Have grid, source electrode and drain electrode; P transistor npn npn M 11Grid be electrically coupled to bias voltage V G2, its source electrode is electrically coupled to P transistor npn npn M 9Drain electrode, and its drain electrode is electrically coupled to P transistor npn npn M 9Grid and N transistor npn npn M 7Drain electrode.P transistor npn npn M 12Have grid, source electrode and drain electrode; P transistor npn npn M 12Grid be electrically coupled to bias voltage V G2, its source electrode is electrically coupled to P transistor npn npn M 10Drain electrode, and its drain electrode is electrically coupled to low-pass filter circuit 26 so that output current I to be provided E0
Low-pass filter circuit 26 is electrically coupled to output-stage circuit 25 to receive output current I E0, this low-pass filter circuit 26 makes output current I E0Through producing demodulation package signal V after the low-pass filtering operation E0In the present embodiment, low-pass filter circuit 26 comprises the resistance R and the capacitor C of coupled in parallel.
In sum; The amplitude offset key system demodulator that the embodiment of the invention proposes; Its input rectification circuit 22 adopts the transistor of two above phase electric property couplings to carry out the rectification operation, and each transistor adopts its grid not to be present in the input rectification circuit 22 with the connected mode that source electrode and drain electrode couple mutually; So can not adopt the diode framework to carry out the rectification operation, bring pressure drop thereby can reduce diode.Therefore, the input signal that the amplitude offset key system demodulator 20 that the embodiment of the invention proposes allows than short arc, thus can be fit to the less system of its input signal of wireless related application (for example, radio frequency identification system 100).In addition, input rectification circuit 22 is because of adopting way of full-wave rectification, and the demodulation package signal of output has less ripple problem (Ripple Issue).In addition, adjust the transistorized control voltage of input rectification circuit 22, can also overcome the threshold values variable effect that is caused because of the processing procedure drift by bias circuit 23.Further; Because the amplitude offset key system demodulator that the embodiment of the invention proposes can reduce diode and bring pressure drop; In the processing procedure of low temperature compound crystal silicon; This circuit can bring effect preferably, and the signal of avoiding importing into is because of decaying through diode drop, so adopt the radio frequency identification system of this kind amplitude offset key system demodulator can be integrated on the display of employing as this high threshold voltage processing procedure of low temperature compound crystal silicon.
Need to prove that the source electrode of each N transistor npn npn and P transistor npn npn can be according to the different circuits design demand and switch with drain electrode in the embodiment of the invention, the effect of its same attainable cost invention.In addition; Those skilled in the art can do suitable circuit structure change to input rectification circuit 22, bias circuit 23, current mirroring circuit 24, output-stage circuit 25 and the low-pass filter circuit 26 of the embodiment of the invention according to actual needs, as long as it does not depart from spirit of the present invention and all can.
Though the present invention with preferred embodiment openly as above; But it is not in order to limit the present invention; Any those skilled in the art; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and modification, so protection scope of the present invention is as the criterion when looking the accompanying Claim book person of defining.

Claims (12)

1.一种振幅偏移键制解调器，适于解调一交流输入信号而产生一解调封包信号，其特征在于，该振幅偏移键制解调器包括： 1. An amplitude shift keying demodulator is suitable for demodulating an AC input signal to generate a demodulated packet signal, characterized in that the amplitude shift keying demodulator includes: 一信号输入端子组，包括一第一输入端与一第二输入端，该信号输入端子组接收该交流输入信号； A signal input terminal group, including a first input terminal and a second input terminal, the signal input terminal group receives the AC input signal; 一输入整流电路，包括： An input rectification circuit, including: 一第一N型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第一N型晶体管的栅极接收一第一控制电压，且该第一N型晶体管的第一源/漏极电性耦接至该第一输入端； A first N-type transistor has a gate, a first source/drain and a second source/drain, the gate of the first N-type transistor receives a first control voltage, and the first N-type transistor of the first N-type transistor a source/drain electrically coupled to the first input terminal; 一第二N型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第二N型晶体管的栅极接收该第一控制电压，且该第二N型晶体管的第一源/漏极电性耦接至该第二输入端； A second N-type transistor has a gate, a first source/drain and a second source/drain, the gate of the second N-type transistor receives the first control voltage, and the second N-type transistor of the second N-type transistor A source/drain is electrically coupled to the second input terminal; 一第一P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第一P型晶体管的栅极接收一第二控制电压，且该第一P型晶体管的第一源/漏极电性耦接至该第一输入端；以及 A first P-type transistor has a gate, a first source/drain and a second source/drain, the gate of the first P-type transistor receives a second control voltage, and the first P-type transistor a source/drain electrically coupled to the first input terminal; and 一第二P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第二P型晶体管的栅极接收该第二控制电压，且该第二P型晶体管的第一源/漏极电性耦接至该第二输入端； A second P-type transistor has a gate, a first source/drain and a second source/drain, the gate of the second P-type transistor receives the second control voltage, and the first P-type transistor of the second P-type transistor A source/drain is electrically coupled to the second input terminal; 一电流镜电路，电性耦接至该输入整流电路，并根据流经该输入整流电路的一输入电流而产生一镜像电流； a current mirror circuit, electrically coupled to the input rectification circuit, and generates a mirror current according to an input current flowing through the input rectification circuit; 一输出级电路，电性耦接至该电流镜电路以接收该镜像电流，该输出级电路并根据该镜像电流而产生一输出电流；以及 an output stage circuit electrically coupled to the current mirror circuit to receive the mirror current, and the output stage circuit generates an output current according to the mirror current; and 一低通滤波电路，电性耦接至该输出级电路以接收该输出电流，该低通滤波电路使该输出电流经过低通滤波操作后产生该解调封包信号。 A low-pass filter circuit is electrically coupled to the output stage circuit to receive the output current. The low-pass filter circuit makes the output current undergo a low-pass filter operation to generate the demodulated packet signal. 2.如权利要求1所述的振幅偏移键制解调器，其特征在于，还包括一偏压电路，该偏压电路包括： 2. The amplitude shift keying demodulator according to claim 1, further comprising a bias circuit, the bias circuit comprising: 一第一电流源，一端电性耦接于一第一工作电压，另一端电性耦接于该第一N型晶体管的栅极； A first current source, one end is electrically coupled to a first operating voltage, and the other end is electrically coupled to the gate of the first N-type transistor; 一第三N型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第三N 型晶体管的栅极与第二源/漏极电性耦接于该第一N型晶体管的栅极，该第三N型晶体管的第一源/漏极电性耦接于一第一偏压电压； A third N-type transistor has a gate, a first source/drain and a second source/drain, the gate of the third N-type transistor and the second source/drain are electrically coupled to the first N the gate of the N-type transistor, the first source/drain of the third N-type transistor is electrically coupled to a first bias voltage; 一第二电流源，一端电性耦接于一第二工作电压，另一端电性耦接于该第一P型晶体管的栅极；以及 a second current source, one end is electrically coupled to a second operating voltage, and the other end is electrically coupled to the gate of the first P-type transistor; and 一第三P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第三P型晶体管的栅极与第二源/漏极电性耦接于该第一P型晶体管的栅极，该第三P型晶体管的第一源/漏极电性耦接于该第一偏压电压。 A third P-type transistor has a gate, a first source/drain and a second source/drain, the gate and the second source/drain of the third P-type transistor are electrically coupled to the first P The gate of the third P-type transistor, the first source/drain of the third P-type transistor is electrically coupled to the first bias voltage. 3.如权利要求1所述的振幅偏移键制解调器，其特征在于，该电流镜电路包括： 3. Amplitude shift key demodulator as claimed in claim 1, is characterized in that, this current mirror circuit comprises: 一第四P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第四P型晶体管的栅极与第二源/漏极电性耦接至该第一与第二N型晶体管的第二源/漏极，该第四P型晶体管的第一源/漏极电性耦接于一第一工作电压； A fourth P-type transistor has a gate, a first source/drain and a second source/drain, the gate and the second source/drain of the fourth P-type transistor are electrically coupled to the first and the second source/drain of the second N-type transistor, the first source/drain of the fourth P-type transistor is electrically coupled to a first operating voltage; 一第四N型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第四N型晶体管的栅极与第二源/漏极电性耦接至该第一与第二P型晶体管的第二源/漏极，该第四N型晶体管的第一源/漏极电性耦接于一第二工作电压； A fourth N-type transistor has a gate, a first source/drain and a second source/drain, the gate and the second source/drain of the fourth N-type transistor are electrically coupled to the first and the second source/drain of the second P-type transistor, the first source/drain of the fourth N-type transistor is electrically coupled to a second operating voltage; 一第五P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第五P型晶体管的栅极电性耦接至该第四P型晶体管的栅极，该第五P型晶体管的第一源/漏极电性耦接于该第一工作电压，该第五P型晶体管的第二源/漏极电性耦接至该输出级电路以提供该镜像电流；以及 A fifth P-type transistor has a gate, a first source/drain and a second source/drain, the gate of the fifth P-type transistor is electrically coupled to the gate of the fourth P-type transistor, the gate of the fifth P-type transistor is electrically coupled to the gate of the fourth P-type transistor, The first source/drain of the fifth P-type transistor is electrically coupled to the first operating voltage, and the second source/drain of the fifth P-type transistor is electrically coupled to the output stage circuit to provide the mirror current ;as well as 一第五N型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第五N型晶体管的栅极电性耦接至该第四N型晶体管的栅极，该第五N型晶体管的第一源/漏极电性耦接于该第二工作电压，该第五N型晶体管的第二源/漏极电性耦接至该输出级电路。 A fifth N-type transistor having a gate, a first source/drain and a second source/drain, the gate of the fifth N-type transistor is electrically coupled to the gate of the fourth N-type transistor, the gate of the fifth N-type transistor is electrically coupled to the gate of the fourth N-type transistor, The first source/drain of the fifth N-type transistor is electrically coupled to the second working voltage, and the second source/drain of the fifth N-type transistor is electrically coupled to the output stage circuit. 4.如权利要求3所述的振幅偏移键制解调器，其特征在于，该输出级电路包括： 4. Amplitude shift key demodulator as claimed in claim 3, is characterized in that, this output stage circuit comprises: 一第六P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第六P型晶体管的第一源/漏极电性耦接至该第一工作电压； A sixth P-type transistor having a gate, a first source/drain and a second source/drain, the first source/drain of the sixth P-type transistor is electrically coupled to the first operating voltage; 一第七P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第七P型晶体管的第一源/漏极电性耦接至该第一工作电压，该第七P型晶体管的栅极电性耦接至该第六P型晶体管的栅极，且该第七P型晶体管的第二源/漏极 电性耦接至该第五P型晶体管的第二源/漏极； A seventh P-type transistor having a gate, a first source/drain and a second source/drain, the first source/drain of the seventh P-type transistor is electrically coupled to the first operating voltage, the The gate of the seventh P-type transistor is electrically coupled to the gate of the sixth P-type transistor, and the second source/drain of the seventh P-type transistor is electrically coupled to the first gate of the fifth P-type transistor. Two source/drain; 一第八P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第八P型晶体管的栅极电性耦接至一第二偏压电压，该第八P型晶体管的第一源/漏极电性耦接至该第六P型晶体管的第二源/漏极，且该第八P型晶体管的第二源/漏极电性耦接至该第六P型晶体管的栅极与该第五N型晶体管的第二源/漏极；以及 An eighth P-type transistor having a gate, a first source/drain and a second source/drain, the gate of the eighth P-type transistor is electrically coupled to a second bias voltage, the eighth P-type transistor The first source/drain of the sixth P-type transistor is electrically coupled to the second source/drain of the sixth P-type transistor, and the second source/drain of the eighth P-type transistor is electrically coupled to the sixth the gate of the P-type transistor and the second source/drain of the fifth N-type transistor; and 一第九P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第九P型晶体管的栅极电性耦接至该第二偏压电压，该第九P型晶体管的第一源/漏极电性耦接至该第七P型晶体管的第二源/漏极，且该第九P型晶体管的第二源/漏极电性耦接至该低通滤波电路以提供该输出电流。 A ninth P-type transistor having a gate, a first source/drain and a second source/drain, the gate of the ninth P-type transistor is electrically coupled to the second bias voltage, the ninth P The first source/drain of the P-type transistor is electrically coupled to the second source/drain of the seventh P-type transistor, and the second source/drain of the ninth P-type transistor is electrically coupled to the low-pass filter circuit to provide this output current. 5.一种使用如权利要求1所述的振幅偏移键制解调器的无线射频辨识系统，其特征在于，包括： 5. A radio frequency identification system using the amplitude shift key modem as claimed in claim 1, characterized in that it comprises: 一无线接收模块，接收一无线射频信号，并将该无线射频信号转换为相对应的一交流输入信号； A wireless receiving module, which receives a wireless radio frequency signal and converts the wireless radio frequency signal into a corresponding AC input signal; 一如权利要求1所述的振幅偏移键制解调器，电性耦接至该无线接收模块以接收该交流输入信号；以及 An amplitude shift keying modem as claimed in claim 1, electrically coupled to the wireless receiving module to receive the AC input signal; and 一处理模块，电性耦接至该振幅偏移键制解调器以接收该解调封包信号，该处理模块根据该解调封包信号而执行相对应的操作。 A processing module is electrically coupled to the amplitude shift keying demodulator to receive the demodulated packet signal, and the processing module performs corresponding operations according to the demodulated packet signal. 6.如权利要求5所述的无线射频辨识系统，其特征在于，还包括一显示模块，该显示模块根据该处理模块的控制而显示该解调封包信号中所包含的内容。 6. The radio frequency identification system according to claim 5, further comprising a display module, the display module displays the content contained in the demodulated packet signal according to the control of the processing module. 7.一种振幅偏移键制解调器，适于解调一交流输入信号而产生一解调封包信号，其特征在于，该振幅偏移键制调便器包括： 7. An amplitude shift key demodulator, suitable for demodulating an AC input signal to generate a demodulated packet signal, characterized in that the amplitude shift key toilet includes: 一信号输入端子组，包括一第一输入端与一第二输入端，该信号输入端子组接收该交流输入信号； A signal input terminal group, including a first input terminal and a second input terminal, the signal input terminal group receives the AC input signal; 一输入整流电路，电性耦接至该信号输入端子组以对该交流输入信号进行一全波整流操作，其中，该输入整流电路包含两个以上相电性耦接的晶体管，且每一该些晶体管采用其栅极不与源极及漏极相耦接的连接方式存在于该输入整流电路中； An input rectification circuit electrically coupled to the signal input terminal group to perform a full-wave rectification operation on the AC input signal, wherein the input rectification circuit includes more than two transistors electrically coupled in phase, and each of the transistors are present in the input rectifier circuit with their gates not coupled to the source and drain; 一电流镜电路，电性耦接至该输入整流电路，并根据流经该输入整流电路 的一输入电流而产生一镜像电流； a current mirror circuit, electrically coupled to the input rectifier circuit, and generates a mirror current according to an input current flowing through the input rectifier circuit; 一输出级电路，电性耦接至该电流镜电路以接收该镜像电流，该输出级电路并根据该镜像电流而产生一输出电流；以及 an output stage circuit electrically coupled to the current mirror circuit to receive the mirror current, and the output stage circuit generates an output current according to the mirror current; and 一低通滤波电路，电性耦接至该输出级电路以接收该输出电流，该低通滤波电路使该输出电流经过低通滤波操作后产生该解调封包信号； A low-pass filter circuit, electrically coupled to the output stage circuit to receive the output current, the low-pass filter circuit makes the output current undergo a low-pass filter operation to generate the demodulated packet signal; 其中，该输入整流电路包括： Wherein, the input rectification circuit includes: 一第一N型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第一N型晶体管的栅极接收一第一控制电压，且该第一N型晶体管的第一源/漏极电性耦接至该第一输入端； A first N-type transistor has a gate, a first source/drain and a second source/drain, the gate of the first N-type transistor receives a first control voltage, and the first N-type transistor of the first N-type transistor a source/drain electrically coupled to the first input terminal; 一第二N型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第二N型晶体管的栅极接收该第一控制电压，且该第二N型晶体管的第一源/漏极电性耦接至该第二输入端； A second N-type transistor has a gate, a first source/drain and a second source/drain, the gate of the second N-type transistor receives the first control voltage, and the second N-type transistor of the second N-type transistor A source/drain is electrically coupled to the second input terminal; 一第一P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第一P型晶体管的栅极接收一第二控制电压，且该第一P型晶体管的第一源/漏极电性耦接至该第一输入端；以及 A first P-type transistor has a gate, a first source/drain and a second source/drain, the gate of the first P-type transistor receives a second control voltage, and the first P-type transistor a source/drain electrically coupled to the first input terminal; and 一第二P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第二P型晶体管的栅极接收该第二控制电压，且该第二P型晶体管的第一源/漏极电性耦接至该第二输入端。 A second P-type transistor has a gate, a first source/drain and a second source/drain, the gate of the second P-type transistor receives the second control voltage, and the first P-type transistor of the second P-type transistor A source/drain is electrically coupled to the second input end. 8.如权利要求7所述的振幅偏移键制解调器，其特征在于，还包括一偏压电路，该偏压电路包括： 8. The amplitude shift keying demodulator as claimed in claim 7, further comprising a bias circuit, the bias circuit comprising: 一第一电流源，一端电性耦接于一第一工作电压，另一端电性耦接于该第一N型晶体管的栅极； A first current source, one end is electrically coupled to a first operating voltage, and the other end is electrically coupled to the gate of the first N-type transistor; 一第三N型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第三N型晶体管的栅极与第二源/漏极电性耦接于该第一N型晶体管的栅极，该第三N型晶体管的第一源/漏极电性耦接于一第一偏压电压； A third N-type transistor having a gate, a first source/drain and a second source/drain, the gate and the second source/drain of the third N-type transistor are electrically coupled to the first N the gate of the N-type transistor, the first source/drain of the third N-type transistor is electrically coupled to a first bias voltage; 一第二电流源，一端电性耦接于一第二工作电压，另一端电性耦接于该第一P型晶体管的栅极；以及 a second current source, one end is electrically coupled to a second operating voltage, and the other end is electrically coupled to the gate of the first P-type transistor; and 一第三P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第三P型晶体管的栅极与第二源/漏极电性耦接于该第一P型晶体管的栅极，该第三P型晶体管的第一源/漏极电性耦接于该第一偏压电压。  A third P-type transistor has a gate, a first source/drain and a second source/drain, the gate and the second source/drain of the third P-type transistor are electrically coupled to the first P The gate of the third P-type transistor, the first source/drain of the third P-type transistor is electrically coupled to the first bias voltage. the 9.如权利要求7所述的振幅偏移键制解调器，其特征在于，该电流镜电路包括： 9. Amplitude shift keying demodulator as claimed in claim 7, is characterized in that, this current mirror circuit comprises: 一第四P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第四P型晶体管的栅极与第二源/漏极电性耦接至该第一与第二N型晶体管的第二源/漏极，该第四P型晶体管的第一源/漏极电性耦接于一第一工作电压； A fourth P-type transistor has a gate, a first source/drain and a second source/drain, the gate and the second source/drain of the fourth P-type transistor are electrically coupled to the first and the second source/drain of the second N-type transistor, the first source/drain of the fourth P-type transistor is electrically coupled to a first operating voltage; 一第四N型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第四N型晶体管的栅极与第二源/漏极电性耦接至该第一与第二P型晶体管的第二源/漏极，该第四N型晶体管的第一源/漏极电性耦接于一第二工作电压； A fourth N-type transistor has a gate, a first source/drain and a second source/drain, the gate and the second source/drain of the fourth N-type transistor are electrically coupled to the first and the second source/drain of the second P-type transistor, the first source/drain of the fourth N-type transistor is electrically coupled to a second operating voltage; 一第五P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第五P型晶体管的栅极电性耦接至该第四P型晶体管的栅极，该第五P型晶体管的第一源/漏极电性耦接于该第一工作电压，该第五P型晶体管的第二源/漏极电性耦接至该输出级电路以提供该镜像电流；以及 A fifth P-type transistor has a gate, a first source/drain and a second source/drain, the gate of the fifth P-type transistor is electrically coupled to the gate of the fourth P-type transistor, the gate of the fifth P-type transistor is electrically coupled to the gate of the fourth P-type transistor, The first source/drain of the fifth P-type transistor is electrically coupled to the first operating voltage, and the second source/drain of the fifth P-type transistor is electrically coupled to the output stage circuit to provide the mirror current ;as well as 一第五N型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第五N型晶体管的栅极电性耦接至该第四N型晶体管的栅极，该第五N型晶体管的第一源/漏极电性耦接于该第二工作电压，该第五N型晶体管的第二源/漏极电性耦接至该输出级电路。 A fifth N-type transistor having a gate, a first source/drain and a second source/drain, the gate of the fifth N-type transistor is electrically coupled to the gate of the fourth N-type transistor, the gate of the fifth N-type transistor is electrically coupled to the gate of the fourth N-type transistor, The first source/drain of the fifth N-type transistor is electrically coupled to the second working voltage, and the second source/drain of the fifth N-type transistor is electrically coupled to the output stage circuit. 10.如权利要求9所述的振幅偏移键制解调器，其特征在于，该输出级电路包括： 10. Amplitude shift keying demodulator as claimed in claim 9, is characterized in that, this output stage circuit comprises: 一第六P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第六P型晶体管的第一源/漏极电性耦接至该第一工作电压； A sixth P-type transistor having a gate, a first source/drain and a second source/drain, the first source/drain of the sixth P-type transistor is electrically coupled to the first operating voltage; 一第七P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第七P型晶体管的第一源/漏极电性耦接至该第一工作电压，该第七P型晶体管的栅极电性耦接至该第六P型晶体管的栅极，且该第七P型晶体管的第二源/漏极电性耦接至该第五P型晶体管的第二源/漏极； A seventh P-type transistor having a gate, a first source/drain and a second source/drain, the first source/drain of the seventh P-type transistor is electrically coupled to the first operating voltage, the The gate of the seventh P-type transistor is electrically coupled to the gate of the sixth P-type transistor, and the second source/drain of the seventh P-type transistor is electrically coupled to the first electrode of the fifth P-type transistor. Two source/drain; 一第八P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第八P型晶体管的栅极电性耦接至一第二偏压电压，该第八P型晶体管的第一源/漏极电性耦接至该第六P型晶体管的第二源/漏极，且该第八P型晶体管的第二源/漏极电性耦接至该第六P型晶体管的栅极与该第五N型晶体管的第二源/漏极；以及 An eighth P-type transistor having a gate, a first source/drain and a second source/drain, the gate of the eighth P-type transistor is electrically coupled to a second bias voltage, the eighth P-type transistor The first source/drain of the sixth P-type transistor is electrically coupled to the second source/drain of the sixth P-type transistor, and the second source/drain of the eighth P-type transistor is electrically coupled to the sixth the gate of the P-type transistor and the second source/drain of the fifth N-type transistor; and 一第九P型晶体管，具有栅极、第一源/漏极与第二源/漏极，该第九P 型晶体管的栅极电性耦接至该第二偏压电压，该第九P型晶体管的第一源/漏极电性耦接至该第七P型晶体管的第二源/漏极，且该第九P型晶体管的第二源/漏极电性耦接至该低通滤波电路以提供该输出电流。 A ninth P-type transistor having a gate, a first source/drain and a second source/drain, the gate of the ninth P-type transistor is electrically coupled to the second bias voltage, the ninth P The first source/drain of the P-type transistor is electrically coupled to the second source/drain of the seventh P-type transistor, and the second source/drain of the ninth P-type transistor is electrically coupled to the low-pass filter circuit to provide this output current. 11.一种使用如权利要求7所述的振幅偏移键制解调器的无线射频辨识系统，其特征在于，包括： 11. A radio frequency identification system using the amplitude shift keying demodulator according to claim 7, characterized in that it comprises: 一无线接收模块，接收一无线射频信号，并将该无线射频信号转换为相对应的一交流输入信号； A wireless receiving module, which receives a wireless radio frequency signal and converts the wireless radio frequency signal into a corresponding AC input signal; 一如权利要求7所述的振幅偏移键制解调器，电性耦接至该无线接收模块以接收该交流输入信号；以及 An amplitude shift keying modem as claimed in claim 7, electrically coupled to the wireless receiving module to receive the AC input signal; and 一处理模块，电性耦接至该振幅偏移键制解调器以接收该解调封包信号，该处理模块根据该解调封包信号而执行相对应的操作。 A processing module is electrically coupled to the amplitude shift keying demodulator to receive the demodulated packet signal, and the processing module performs corresponding operations according to the demodulated packet signal. 12.如权利要求11所述的无线射频辨识系统，其特征在于，还包括一显示模块，该显示模块根据该处理模块的控制而显示该解调封包信号中所包含的内容。  12. The radio frequency identification system according to claim 11, further comprising a display module, the display module displays the content contained in the demodulated packet signal according to the control of the processing module. the
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4359693A (en) * 1980-09-15 1982-11-16 National Semiconductor Corporation Full wave amplitude modulation detector circuit
CN2549645Y (en) * 2002-06-07 2003-05-07 清华大学 Full-wave rectification circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4359693A (en) * 1980-09-15 1982-11-16 National Semiconductor Corporation Full wave amplitude modulation detector circuit
CN2549645Y (en) * 2002-06-07 2003-05-07 清华大学 Full-wave rectification circuit

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