CN101471657B - Whole digital PPL and control method thereof - Google Patents
Whole digital PPL and control method thereof Download PDFInfo
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- CN101471657B CN101471657B CN2007101943898A CN200710194389A CN101471657B CN 101471657 B CN101471657 B CN 101471657B CN 2007101943898 A CN2007101943898 A CN 2007101943898A CN 200710194389 A CN200710194389 A CN 200710194389A CN 101471657 B CN101471657 B CN 101471657B
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Abstract
A fully digital phase-locked loop comprises a numerical control oscillator, a phase detector and a loop filter, wherein, the numerical control oscillator is used for generating a variable signal and controlled by tuning words of the oscillator. The tuning words of oscillator consist of a first tuning word and a second tuning word. The adjustable frequency range of the second tuning word to the numerical control oscillator is larger than that of the first tuning word to the numerical control oscillator; the phase detector is used for measuring a phase difference between a variable signal and a reference signal; and the loop filter is used for receiving the phase difference and generating the tuning words of the oscillator, and comprises a plurality of stages of low-pass filters and an adjusting circuit, wherein, the low-pass filters receive the phase difference, and the adjusting circuit detects the output of two filtering waves of two of the low-pass filters and adjusts the second tuning word according to the output of the two filtering waves.
Description
Technical field
The present invention relates to a full digital phase locking loop with and phase-lock technique, especially relate to a kind of full digital phase locking loop that can lock phase fast with and method.
Background technology
Full digital phase locking loop is one of important technology of wireless telecommunications in recent years development because it is compared to analog pll circuit, can be relatively easy to be implemented in advanced process system single chip (systemon chip, SOC) in.But, design the full digital phase locking loop of quick lock phase and low phase noise (phase noise), be a challenge.
Fig. 1 is a known full digital phase locking loop, the sketch map that (phase domain) angle is seen from the phase place field.The explanation of Fig. 1 can number 7,145 referring to United States Patent (USP), and 399 patent specification below is merely rough explanation.
Variable signal f
vAnd reference signal f
RefPhase difference ψ
ECan calculate by phase detectors (phasedetector) 115.As shown in the figure, phase detectors 115 have three inputs, and one of them input is by reference signal f
RefProvide through 105 of fixed phase integrating instruments (reference phase accumulator), can be regarded as is reference signal f
RefPhase value.Another input is to calculate variable signal f
vProvide via oscillation phase integrating instrument (oscillator phase accumulator) 140 and 145 of samplers (sampler), can be regarded as is variable signal f
vPhase value.And last input is reference signal f
RefWith variable signal f
vBetween small phase difference (fractional phase error) correct.The sum total of these three inputs can form phase difference ψ
E
Loop filter (loop filter) 120 is then to phase difference ψ
ECarry out filtering with and/or amplitude adjustment.Loop filter 120 produces an oscillator control digit, and (oscillator tuning word OTW), changes numerically-controlled oscillator (digitally controlled oscillator, DCO) 125 output, just variable signal f
v
In current full digital phase locking loop; The framework that adopts transformation loop frequency range (gear shift) and adopt the second kenel high-order loop filter (type-II and higher order loop filter) is arranged; Just in time switch the loop gain (loop gain) that is provided in the one second kenel high-order loop filter, hope to reach the purpose of quick lock phase and low phase noise.Just disclosed a similar full digital phase locking loop like patent application publication number 2003/0234693.
Yet, how to operate or design an appropriate full digital phase locking loop, remain the target that the designer pursues.
Summary of the invention
The embodiment of the invention provides a kind of full digital phase locking loop, includes a numerically-controlled oscillator, phase detectors and a loop filter.This numerically-controlled oscillator is controlled by an oscillator control digit in order to produce a variable signal.This oscillator control digit includes one first control digit and one second control digit.This second control digit is put in order scope greater than this first control digit to a frequency adjustable of this numerically-controlled oscillator to the whole scope of a frequency adjustable of this numerically-controlled oscillator.These phase detectors are in order to measure the phase difference between this variable signal and the reference signal.This loop filter receives this phase difference, to produce this oscillator control digit.This loop filter includes several grades of low pass filters and an adjustment circuit.Said low pass filter receives this phase difference.The two filtering output of two low pass filters in the said low pass filter of this adjustment electric circuit inspection, and according to this this second control digit of two filtering output adjustment.
The embodiment of the invention provides a kind of phase-locked loop control method.Earlier a phase difference is carried out the several LPF,, control a numerically-controlled oscillator to produce an oscillator control digit.This oscillator control digit has one first control digit and one second control digit.The minimum frequency variable quantity that this first control digit can produce for this numerically-controlled oscillator, the minimum frequency variable quantity that can produce for this numerically-controlled oscillator less than this second control digit.Detect two filtering of LPF output behind the LPF and before one.Judge whether this two filtering output meets a condition.When this two filtering output meets this condition, adjust this second control digit.
Description of drawings
Fig. 1 is a known full digital phase locking loop.
Fig. 2 is the loop filter according to the present invention implemented.
Fig. 3 is the decision circuitry according to the present invention implemented.
Fig. 4 shows the partial circuit in the numerically-controlled oscillator.
Fig. 5 is another loop filter according to the present invention implemented.
Fig. 6 is the flow chart according to the present invention implemented.
The reference numeral explanation
Fixed phase integrating instrument 105
Phase detectors 115
Loop filter 120
Numerically-controlled oscillator 125
Oscillation phase integrating instrument 140
Sampler 145
Multiplier 604,606
Adder 612,614,618
Comparator 702,704
Embodiment
Fig. 2 is for according to the loop filter 600 that the present invention implemented, and is used for receiving phase difference ψ
E, and control a numerically-controlled oscillator according to this.When loop filter 600 replaces the loop filter 120 among Fig. 1, just can produce one according to full digital phase locking loop that the present invention implemented.
The output of the loop filter 600 of Fig. 2 (oscillator control digit) has three parts: process voltage temperature (process-voltage-temperature; PVT) control digit, acquisition (acquisition, ACQ) control digit and tracking (tracking) control digit.For instance; The oscillator control digit that loop filter 600 is exported has 22 OTW [0:21], and wherein, the highest eight position OTW [14:21] have constituted the PVT control digit; Then eight position OTW [6:13] have constituted the acquisition control digit, and minimum six position OTW [0:5] have then constituted the tracking control digit.PVT control digit with high byte is maximum for the adjustable scope of numerically-controlled oscillator, but its resolution is the thickest also, generally is to be used for process, voltage and the temperature of correcting chip for the influence of full digital phase locking loop.Tracking control digit with low byte is minimum for the adjustable scope of numerically-controlled oscillator, but its resolution is the thinnest also, generally is to be used for following the trail of carrier signal (carrier signal) to use.Acquisition control digit with intermediary bytes all is the centre among the three for the adjustable scope of numerically-controlled oscillator and resolution, generally is used for generally determining wireless channel (channel).
The loop filter 600 of Fig. 2 has serial connection several grades of low pass filter 602a-602c together, receiving phase difference ψ
EIn the example of Fig. 2, each grade low pass filter all is an IIR (infinite impulse response, an IIR) filter.Each low pass filter also can be a finite impulse response (FIR) (finite impulse response, FIR) filter.The filtering output of afterbody low pass filter 602c can be delivered to a multiplier 604, to be multiplied by a loop gain α.Loop gain α also can pass through each low pass filter, comes seriatim to filtering output adjustment.Still the phase difference ψ of filtered ripple device
EAlso can be multiplied by a part of gain beta (with multiplier 606), get into integrating instrument 608 then.The sum total of the aggregate-value of the output of multiplier 604 and integrating instrument 608 has produced tracking control digit (TRACK TW).In brief, low pass filter 602a-602c and multiplier 604 provide one second kenel high-order loop filter, and just its time response is slow, because phase difference ψ
EChange just can have influence on the tracking control digit after must experiencing the filtration of a plurality of low pass filters.608 of multiplier 606 and integrating instruments provide a relatively path of Fast Time reaction, make ψ
EChange can influence the tracking control digit apace.
The loop filter 600 of Fig. 2 also has two adjustment circuit 610a and 610b.Each adjustment circuit 610a/b all have two decision circuitry (6104a/b, 6106a/b), an integrating instrument 6102a/b and an adder 6108a/b.Though the adjustment circuit 610a of Fig. 2 is the same with the functional block diagram of 610b, circuit wherein but maybe be different each other, and the identical functions square can be realized with different circuits.
On the function, adjustment circuit 610a directly detects the filtering output of low pass filter 602a and 602b.Once two filtering output meets one when pre-conditioned, adjustment circuit 610a just can go to change the PVT control digit through adder 612, just adjusts the output frequency of numerically-controlled oscillator significantly, just the output frequency of variable signal fv.
On the function, adjustment circuit 610b directly detects the filtering output of low pass filter 602b, but through adder 618 and multiplier 604, detects the filtering output of afterbody low pass filter 602c indirectly.Once that two filtering output meets is one pre-conditioned when (maybe with adjustment circuit 610a pre-conditioned identical or different); Adjustment circuit 610b just can go to change the ACQ control digit through adder 614, just the output frequency of moderate range ground adjustment numerically-controlled oscillator.
Fig. 3 is for according to the decision circuitry 700 that the present invention implemented, go among Fig. 2 any one decision circuitry (6104a/b, 6106a/b).(upper bond UPB) does comparison to comparator 702, and (lower bond LWB) does comparison with a preset lower limit and comparator 704 is the input of decision circuitry 700 with a preset upper limit the input of decision circuitry 700. Comparator 702 and 704 result output be not 1 be exactly-1, two result's output with (by adder 706 execution), can be used as the output of whole decision circuitry 700.The equivalent function of the decision circuitry 700 among Fig. 3 is described below.If the input of decision circuitry 700 is higher than UPB, then the output valve of decision circuitry 700 is 1; The input of decision circuitry 700 is lower than LWB, and then the output valve of decision circuitry 700 is-1; If the input of decision circuitry 700 is between UPB and LWB, then the output valve of decision circuitry 700 is 0; If it is too violent that the output of decision circuitry 700 changes, can input signal be multiplied by a coefficient lambda, change to slow down output.
Generally phase difference seldom lock (phase difference ψ just
EVery little) state under, the filtering of low pass filter 602b output should be stable haply between UPBa and LWBa, and the filtering of low pass filter 602c output should be stable haply between UPBb and LWBb.At this moment, the output of decision circuitry 6104b and 6106b all can be 0, and the output of integrating instrument 6102b will can not change (0 the numerical value because add up), so adjustment circuit 610b can not have any influence to the ACQ control digit.
And when phase difference variable is big; For example just begun to follow the trail of under the state of carrier signal (carrier signal); The filtering output of low pass filter 602b may be than the scope that has comparatively fast departed between UPBa and the LWBa; The filtering of low pass filter 602c output then possibly just can depart from the scope between UPBb and the LWBb after a while, because the phase-locked loop W-response is quite slow, above-mentioned both depart from trend and can present unanimity.The delay of this time is because the filtering of low pass filter 602c output has been experienced a LPF action compared with the filtering output of low pass filter 602b more, so the reacting condition time is just a little slow.For instance, the filtering of low pass filter 602b output exceeds UPBa suddenly, and the filtering of low pass filter 602c output at this moment is at this moment still between UPBb and LWBb.At this moment, the output of decision circuitry 6104b will become 1, and the output of decision circuitry 6106b will be 0, and integrating instrument 6102b will begin periodically its output to be added 1 according to its input clock (clock).Under this state, adjustment circuit 610b has periodically heightened 1 with the ACQ control digit, orders about the ACQ control digit and becomes big.As existing described, the filtering output of low pass filter 602c is to follow the filtering of low pass filter 602b output basically, has only changed slow a bit.Once the filtering of low pass filter 602c output exceeds after the UPBb; The output of decision circuitry 6104b and 6106b will be 1; Mutually offset and be equal to the action that adds up that has stopped integrating instrument 6102b, also stopped the action of before periodically the ACQ control digit being heightened.At this moment, adjustment circuit 610b stops to influence the ACQ control digit.Similar above analysis is also exported under the situation that begins to reduce applicable to the filtering of low pass filter 602b and 602c, and adjustment circuit 610b may periodically lower after ACQ control digit a period of time, just stopped to influence the ACQ control digit.
From a technical standpoint, whether too many UPBa and LWBa are used for judging filtering output two standards of low pass filter 602b for adjustment circuit 610b.Once the filtering of low pass filter 602b output is too many by judgement, adjustment circuit 610b just directly takes up the output frequency of coarse adjustment one numerically-controlled oscillator.UPBb and LWBb then provide one of the adjustment circuit frequency rough adjustment that 610b is provided to stop mechanism, are equal to the amount that has determined the frequency adjustment.
With reference to above analysis for adjustment circuit 610b, the adjustment circuit 610a of Fig. 2 can be by those skilled in the art, and view just can be understood, so much more no longer its details is stated.From a technical standpoint, when judging the filtering of low pass filter 602a, exports when too many adjustment circuit 610a, and adjustment circuit 610a just directly takes up significantly to adjust the output frequency of a numerically-controlled oscillator.Through the filtering output of direct detection low pass filter 602b, adjustment circuit 610a can stop to adjust the output frequency of this numerically-controlled oscillator, is equal to the amount that has determined the frequency adjustment.
Each should be set at what as for the UPB of each decision circuitry (6104a, 6106a, 6104b, 6106b) and LWB, can look experience and side circuit and design and decide.
Though loop filter among Fig. 2 600 representes that with functional block diagram it can be implemented with hardware mode, also can implement with software mode.
Fig. 4 shows the partial circuit in the numerically-controlled oscillator 800.Numerically-controlled oscillator 800 has an inductance and a plurality of electric capacity, and its frequency of oscillation haply can be by f that formula determines
DCO=1/squr (L*C
Total).Wherein, Ctotal is the sum total of all capacitances.Electric capacity in the numerically-controlled oscillator 800 is divided into four groups of (banks): PVT groups, ACQ group, tracking group and subtrace group haply.The electric capacity supplied in the PVT group is Δ C
0 P... Δ C
7 P, its size is arranged (binary-weighted) with binary mode, and whether it is selected by control signal d
0 P... d
7 PDetermine and d
0 P... d
7 PIntegral body is to be handled and produce through some interfaces (interface) by the PVT control digit basically.So in other words, the electric capacity in the PVT group is controlled by the PVT control digit.The same reason, the electric capacity in the ACQ group is controlled by the ACQ control digit.Different with PVT group and ACQ group is that the electric capacity supplied in the tracking group is Δ C
0 T... Δ C
63 T, in order to reach low phase noise, its capacitance size is the same (unit-weighted) all, and is designed into position of minimum capacitance as far as possible.d
0 TI... d
63 TIIntegral body is to handle and produce through decoding and some interfaces by following the trail of control digit basically.If the electric capacity in the tracking group, the phase noise that is not sufficient to provide can add the subtrace group; Its capacitance size is identical with capacitance in the tracking group, through the use of ∑ sigma-delta modulator, thinner electric capacity resolution is provided; Can reach required phase noise, its control signal d
0 TF... d
7 TFCan produce by the ∑ sigma-delta modulator.In brief, tracking group and subtrace group are controlled by the tracking control digit.Described as before; PVT control digit coarse adjustment one numerically-controlled oscillator; Transfer in the ACQ control digit; And follow the trail of the control digit fine tuning, so the I supply electric capacity in the PVT group can be greater than the I supply electric capacity in the ACQ group, and the I supply electric capacity in the ACQ group can be greater than any electric capacity in tracking group and the subtrace group.
Please refer to Fig. 2; Among two the low pass filter 602a and 602b that adjustment circuit 610a is detected; Low pass filter 602a is a preceding low pass filter; And low pass filter 602b is a back low pass filter, because low pass filter 602b after low pass filter 602a, handles the filtering output of low pass filter 602a.Similarly, among two low pass filter 602b that adjustment circuit 610b is detected and the 602c, low pass filter 602b is a low pass filter before, and low pass filter 602c is a back low pass filter.Can find to be that low pass filter 602b is the back low pass filter that adjustment circuit 610a is detected, also be the preceding low pass filter that adjustment circuit 610b is detected.But the filtering output that adjustment circuit 610a and 610b detect same low pass filter is not to be necessary.Fig. 5 wherein, adjusts the filtering output that circuit 610a and 610b just do not detect same low pass filter for according to another loop filter 800 that the present invention implemented.
Please in the lump with reference to figure 2 and Fig. 6, wherein Fig. 6 is the flow process Figure 90 0 according to the present invention implemented.When a full digital phase locking loop with loop filter 600 of Fig. 2 begins to follow the trail of a reference signal, slightly follow the trail of earlier (step 902), just follow the trail of fast after a period of time (step 904).
When step 902; Adjustment circuit 610a and 610b are in activation (enable) state; Do not change and loop gain α and fractionated gain β are all fixing; Therefore, the ACQ control digit is not just followed the trail of the slightly influence of carry (carry bit) of control digit, may be influenced significantly by adjustment circuit 610b yet; Similarly, the PVT control digit just by the slightly influence of the carry of ACQ control digit institute, may not influenced by adjustment circuit 610a significantly yet.
When coarse adjustment arrives to a certain degree, or after going through certain hour, the value stabilization of integrating instrument 6102a and 6102b is constant in the adjustment circuit, promptly gets into step 904.At this moment, forbidden energy (disable) adjustment circuit 610a and 610b, and loop gain α and fractionated gain β can transfer greatly, as time goes by, interim again diminishes.That is to say, get into step 904 after, used loop gain α and fractionated gain β in the time of can in a period of time, still adopting step 902; Afterwards, lock has been accomplished almost mutually, in order to reduce the noise that loop oneself is contributed, can adopt smaller another loop gain α and another part gain beta.And so reduce the action of loop gain α and fractionated gain β, and not limiting the execution number of times, need look design requirement and lock phase velocity to consider and decide, more than suggestion can be carried out once.
One can be used the more loop filter of high-order according to the full digital phase locking loop that the present invention implemented, and reduces the phase noise of phase-locked loop itself, and adjusts the frequency of the variable signal of its output fast and roughly, reaches the demand of quick lock phase.And lock phase and low phase noise fast all is the demand that industrial circle is eagerly looked forward to.
Though the present invention discloses as above with preferred embodiment; But it is not in order to qualification the present invention, those skilled in the art, under the premise without departing from the spirit and scope of the present invention; When can doing some changes and modification, so protection scope of the present invention should be as the criterion with the application's claim.
Claims (13)
1. full digital phase locking loop includes:
One numerically-controlled oscillator; In order to produce a variable signal; This numerically-controlled oscillator is controlled by an oscillator control digit; This oscillator control digit includes one first control digit and one second control digit, and this second control digit is put in order scope greater than this first control digit to a frequency adjustable of this numerically-controlled oscillator to the whole scope of a frequency adjustable of this numerically-controlled oscillator;
One phase detectors are in order to measure the phase difference between this variable signal and the reference signal; And
One loop filter receives this phase difference, and to produce this oscillator control digit, this loop filter includes:
Several grades of low pass filters receive this phase difference, and wherein this low pass filter further comprises a pre-filter and a postfilter; And
One adjustment circuit, detect said pre-filter one before a back filtering output of filtering output and said postfilter, and according to should before filtering output and should this second control digit of back filtering output adjustment.
2. full digital phase locking loop as claimed in claim 1, wherein, this numerically-controlled oscillator includes:
A plurality of first electric capacity, its capacitance is all identical, controlled by this first control digit; And
A plurality of second electric capacity, the capacitance of each second electric capacity are controlled by this second control digit all greater than the capacitance of single first electric capacity.
3. full digital phase locking loop as claimed in claim 1, wherein, this adjustment circuit includes:
One first decision circuitry detects this back filtering output of this postfilter, and exports one first variable quantity according to this;
One second decision circuitry directly detects should preceding filtering exporting of this pre-filter, and exports one second variable quantity according to this; And
One integrating instrument in order to add up the poor of this first and second variable quantity, is adjusted this second control digit according to this.
4. full digital phase locking loop as claimed in claim 1; Wherein, This oscillator control digit also has one the 3rd control digit, and the 3rd control digit is put in order scope greater than this second control digit to this frequency adjustable of this numerically-controlled oscillator to the whole scope of a frequency adjustable of this numerically-controlled oscillator; This adjustment circuit is one first adjustment circuit, and this full digital phase locking loop also includes:
One second adjustment circuit directly detects the two filtering output of two low pass filters in these several grades of low pass filters, and when this two filtering output meets a condition, adjusts the 3rd control digit according to this.
5. full digital phase locking loop as claimed in claim 4 wherein, is exported by this first adjustment preceding filtering of being somebody's turn to do that circuit detected, and is the latter of this second adjustment this two filtering output that circuit detected.
6. full digital phase locking loop as claimed in claim 4 wherein, is exported the latter of non-second adjustment this two filtering output that circuit detected by this first adjustment preceding filtering of being somebody's turn to do that circuit detected.
7. full digital phase locking loop as claimed in claim 1, wherein, this loop filter also includes a multiplier, is a loop gain, in order to adjust this oscillator control digit.
8. full digital phase locking loop as claimed in claim 1, wherein, each grade low pass filter is an infinite impulse response filter, or is a finite impulse response filter.
9. phase-locked loop control method includes:
One phase difference is carried out the several LPF; To produce an oscillator control digit; Control a numerically-controlled oscillator; This oscillator control digit has one first control digit and one second control digit, the minimum frequency variable quantity that this first control digit can produce for this numerically-controlled oscillator, the minimum frequency variable quantity that can produce for this numerically-controlled oscillator less than this second control digit;
Detecting a preceding LPF of twice LPF in this several LPF and two filter filters of a back low pass filtered filter exports;
Judge whether this two filtering output meets a condition; And
When this two filtering output meets this condition, adjust this second control digit.
10. phase-locked loop as claimed in claim 9 control method; Wherein, This oscillator control digit also has one the 3rd control digit; And the minimum frequency variable quantity that this second control digit can produce for this numerically-controlled oscillator, less than the minimum frequency variable quantity that the 3rd control digit can produce for this numerically-controlled oscillator, this phase-locked loop control method also includes:
Directly detect another the preceding LPF of other twice LPF in this several LPF and the two filtering output of another back LPF; And
When the two filtering output of this another preceding LPF and this another back LPF meets a condition, adjust the 3rd control digit.
11. phase-locked loop as claimed in claim 9 control method also includes:
One loop gain is provided, to adjust this first control digit.
12. phase-locked loop as claimed in claim 11 control method, wherein, this loop gain is one first loop gain, and this phase-locked loop control method also includes:
Stop to judge whether this two filtering output meets this condition; And
After stopping judgement, one second loop gain is provided, less than this first loop gain, to adjust last filtering output.
13. phase-locked loop as claimed in claim 9 control method, wherein, the step of this second control digit of this adjustment includes:
When the filtering output of this preceding LPF surpasses one first default value, order about this second control digit and change towards one first trend;
When the filtering output of this preceding LPF is lower than one second default value, order about this second control digit and change towards one second trend, wherein this second trend is in contrast to this first trend;
When the filtering output of this back LPF surpasses one the 3rd default value, order about this second control digit and change towards this second trend;
When the filtering output of this back LPF is lower than one the 4th default value, orders about this second control digit and change towards this first trend; And
The constant Preset Time that surpasses of value stabilization when an integrating instrument promptly stops this adjustment.
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| CN2007101943898A CN101471657B (en) | 2007-12-26 | 2007-12-26 | Whole digital PPL and control method thereof |
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| CN2007101943898A CN101471657B (en) | 2007-12-26 | 2007-12-26 | Whole digital PPL and control method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030234693A1 (en) * | 2002-06-19 | 2003-12-25 | Staszewski Robert B. | Type-II all-digital phase-locked loop (PLL) |
| CN1666418A (en) * | 2002-06-28 | 2005-09-07 | 先进微装置公司 | Phase-locked loop with automatic frequency tuning |
| US7046098B2 (en) * | 2001-11-27 | 2006-05-16 | Texas Instruments Incorporated | All-digital frequency synthesis with capacitive re-introduction of dithered tuning information |
| CN1983820A (en) * | 2005-12-17 | 2007-06-20 | Atmel德国有限公司 | PLL frequency generator |
-
2007
- 2007-12-26 CN CN2007101943898A patent/CN101471657B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7046098B2 (en) * | 2001-11-27 | 2006-05-16 | Texas Instruments Incorporated | All-digital frequency synthesis with capacitive re-introduction of dithered tuning information |
| US20030234693A1 (en) * | 2002-06-19 | 2003-12-25 | Staszewski Robert B. | Type-II all-digital phase-locked loop (PLL) |
| CN1666418A (en) * | 2002-06-28 | 2005-09-07 | 先进微装置公司 | Phase-locked loop with automatic frequency tuning |
| CN1983820A (en) * | 2005-12-17 | 2007-06-20 | Atmel德国有限公司 | PLL frequency generator |
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