CN101459150A - Multilayered wiring structure and process for forming multilayered wiring structure - Google Patents
Multilayered wiring structure and process for forming multilayered wiring structure Download PDFInfo
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- CN101459150A CN101459150A CN 200710094487 CN200710094487A CN101459150A CN 101459150 A CN101459150 A CN 101459150A CN 200710094487 CN200710094487 CN 200710094487 CN 200710094487 A CN200710094487 A CN 200710094487A CN 101459150 A CN101459150 A CN 101459150A
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- metal wiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Disclosed are a multilayer wiring structure and a forming method thereof, wherein the forming method includes steps of at least forming a metal wiring layer with a first area metal wiring layer and a second area metal wiring layer which are not connected, forming an upper layer wiring structure of the metal wiring layer, and connecting the first area metal wiring layer with the metal wiring layer in the upper layer wiring structure. The multilayer wiring structure and the forming method thereof distribute the stress to the lower layer wiring structure from the upper layer wiring structure, increase the support force between the wiring structures and avoid collapse of the wiring structures.
Description
Technical field
The present invention relates to the method for Miltilayer wiring structure and formation Miltilayer wiring structure.
Background technology
As everyone knows, encapsulation technology is exactly a kind of technology with the chip packing in fact, and this packing is necessary for chip.Because chip must be isolated from the outside, to prevent owing to airborne impurity causes electric property to descend to the corrosion of chip circuit.On the other hand, the chip after the encapsulation also is more convenient for installing and transportation.Because the quality of encapsulation technology also directly has influence on design and the manufacturing of the performance of chip self performance and the PCB that is attached thereto (printed circuit board), so it is vital.Encapsulation also can be described as installs the shell that semiconductor integrated circuit chip is used, and it not only plays a part to lay, fix, seal, protect chip and increased thermal conductivity energy, but also is the bridge of linking up the chip internal world and external circuit.In simple terms, encapsulation is wired to the contact on the chip on the pin of package casing exactly, and these pins connect by the lead on the printed circuit board (PCB) and other devices again.Therefore, encapsulation technology is unusual the key link in the IC industry.
And in encapsulation technology, a more important design that link is exactly pad (pad).Pad is the coupling part of the pin and the chip circuit of package casing.The quality of pad quality also directly affects the quality of encapsulation.At present, along with development of semiconductor, chip internal has had the muti-layered metallic line structure, and general pad is the top layer that is made in the muti-layered metallic line structure, and this muti-layered metallic line structure does not have active device as next, and such structure is just more stable.And sometimes in order to save multi-layer metal wiring structure Design area, often active device also is made under the pad.For example the patent No. is that the patent of ZL02150695.7 discloses a kind of pad that is formed on the printed circuit board (PCB) with circuitous pattern.
At present, along with the performance requirement of device is more and more higher, for example, for Miltilayer wiring structure, especially it has the Miltilayer wiring structure of active device down, and is very high for the requirement of wiring delay.And in order to reduce wire delay problems, can carry out Low-k to the insulating medium layer between the wire structures usually to mix, and the Low-k doping can make the insulating medium layer between the wire structures become fragile, and causes wire structures to subside, and cause device to be scrapped.
Summary of the invention
The invention provides the method for a kind of Miltilayer wiring structure and formation Miltilayer wiring structure, solve the prior art wire structures and occur subsiding, and the problem that causes device to be scrapped.
For addressing the above problem, the invention provides a kind of method that forms Miltilayer wiring structure, comprise: form the metal wiring layer that one deck has first area metal wiring layer and second area metal wiring layer at least, described second area metal wiring layer does not link to each other with the first area metal wiring layer; Form the upper strata wire structures of described metal wiring layer; Described first area metal wiring layer is linked to each other with metal wiring layer in the wire structures of upper strata.
The spacing of described second area metal wiring layer and first area metal wiring layer is determined by the spacing requirement between the metal in the design rule.
Described first area metal wiring layer linked to each other with metal wiring layer in the wire structures of upper strata comprise the following steps: on described metal wiring layer, to form insulating medium layer; Undercutting forms through hole in described insulating medium layer; Filled conductive material in through hole.
Described undercutting forms through hole and adopts the Deep Reaction ion(ic) etching.
The packing material of described through hole is a copper.
Correspondingly, the present invention also provides a kind of Miltilayer wiring structure, at least comprise that one deck has the metal wiring layer of first area metal wiring layer and second area metal wiring layer, described first area metal wiring layer is used for linking to each other with the metal wiring layer of upper strata wire structures, and described second area metal wiring layer does not link to each other with the first area metal wiring layer.
The spacing of described second area metal wiring layer and first area metal wiring layer is determined by the spacing requirement between the metal in the design rule.
Described first area metal wiring layer links to each other by through hole with metal wiring layer in the wire structures of upper strata.
The packing material of described through hole is a copper.
Compared with prior art, the method of above-mentioned disclosed Miltilayer wiring structure and formation Miltilayer wiring structure has the following advantages: the method for above-mentioned disclosed Miltilayer wiring structure and formation Miltilayer wiring structure is by being formed for supporting the second area metal wiring layer of upper strata wire structures on wire structures, disperseed the pressure of upper strata wire structures to the lower-layer wiring structure, increase support force between the wire structures, avoided wire structures to occur subsiding.
Description of drawings
Fig. 1 is a kind of execution mode flow chart of the present invention's method of forming Miltilayer wiring structure;
Fig. 2 is a kind of execution mode schematic diagram of Miltilayer wiring structure of the present invention;
Fig. 3 is that the present invention forms the method for designing flow chart that forms the metal wiring layer Butut among the embodiment of Miltilayer wiring structure;
Fig. 4 is the metal wiring layer Butut schematic diagram of method correspondence shown in Figure 3;
Fig. 5 A to Fig. 5 F is the process schematic representation of corresponding method shown in Figure 1.
Embodiment
The method of Miltilayer wiring structure disclosed in this invention and formation Miltilayer wiring structure is by being formed for supporting the second area metal wiring layer of upper strata wire structures on wire structures, disperseed the pressure of upper strata wire structures to the lower-layer wiring structure, increase support force between the wire structures, avoided wire structures to occur subsiding.
With reference to shown in Figure 1, a kind of execution mode that the present invention forms the method for Miltilayer wiring structure comprises the following steps:
Step s1 provides semiconductor wafer;
Step s2 forms first insulating medium layer on described semiconductor wafer;
Step s3 forms first metal wiring layer in first insulating medium layer, described first metal wiring layer comprises first area metal wiring layer and second area metal wiring layer;
Step s4 forms second insulating medium layer on described first metal wiring layer;
Step s5 forms through hole in second insulating medium layer;
Step s6 forms second metal wiring layer on second insulating medium layer.
The spacing of described second area metal wiring layer and first area metal wiring layer is determined by the spacing requirement between the metal in the design rule.
Described formation through hole adopts the Deep Reaction ion(ic) etching.
The packing material of described through hole is a copper.
With reference to shown in Figure 2, a kind of execution mode of Miltilayer wiring structure of the present invention comprises:
Second metal wiring layer 30 in the top layer wire structures; First metal wiring layer under the top layer in one deck wire structures (figure does not indicate), described first metal wiring layer comprises first area metal wiring layer 10 and second area metal wiring layer 11; Has insulating medium layer 22 between described second metal wiring layer 30 and first metal wiring layer; Described second metal wiring layer 30 is communicated with first area metal wiring layer 10 by through hole 20; Described first area metal wiring layer 10 and second area metal wiring layer 11 are arranged in insulating medium layer 21, and wherein said second area metal wiring layer 11 adopts and first area metal wiring layer 10 identical materials.
Described second area metal wiring layer 11 is determined by the spacing requirement of metal layer material described in the design rule with the spacing of first area metal wiring layer 10.
To be described in detail the method that makes above-mentioned Miltilayer wiring structure and form Miltilayer wiring structure clearer for the process that making is had a semiconductor wafer of Miltilayer wiring structure below.
For forming above-mentioned first metal wiring layer, need provide the Butut of the metal wiring layer with counter structure earlier with first area metal wiring layer and second area metal wiring layer.
With reference to shown in Figure 3, the method for designing of described metal wiring layer Butut comprises the following steps:
Step s10 provides the metal wiring layer Butut;
Step s20, described metal wiring layer Butut is divided into first area Butut and second area Butut, described first area Butut does not link to each other mutually with the second area Butut, the corresponding first area of described first area Butut metal wiring layer, the corresponding second area metal wiring layer of second area Butut.
The spacing of described second area Butut and first area Butut is determined by the spacing requirement between the metal in the design rule.
Succinct for what narrate below, with one deck wire structures under the top layer wire structures of Miltilayer wiring structure and the top layer is example, for example, have 8 layers of wire structures, each layer wire structures all has the metal wiring layer of one deck correspondence, and then the first metal wiring layer M7 with one deck wire structures correspondence under the second metal wiring layer M8 of top layer wire structures correspondence and the top layer explains.
Continue with reference to shown in Figure 3,, form the Butut of the first metal wiring layer M7 earlier, then described Butut is cut apart, obtain the figure of first area Butut and second area Butut according to above-mentioned layout design method.The formed first metal wiring layer Butut please refer to shown in Figure 4, the Butut of the described first metal wiring layer M7 comprises two parts, a part is two shown in Fig. 4 and the isolated figure of layout graph of other first metal wiring layers M7, the i.e. figure of second area cloth Fig. 2.And another part is the figure of first area cloth Fig. 1.As can see from Figure 4, the figure of first area cloth Fig. 1 all is interconnected, the first area metal wiring layer of the corresponding first metal wiring layer M7 of the figure of first area cloth Fig. 1, described first area metal wiring layer is as the connecting line layer that links to each other with the second metal wiring layer M8 on upper strata.And the figure of second area cloth Fig. 2 all is mutually independently, and do not link to each other mutually with the figure of first area cloth Fig. 1, the second area metal wiring layer of the corresponding first metal wiring layer M7 of the figure of second area cloth Fig. 2, described second area metal wiring layer uses as above-mentioned support component.The spacing of described second area cloth Fig. 2 and first area cloth Fig. 1 is determined by the spacing requirement between the M7 in the design rule, the minimum spacing of supposing M7 in the design rule is 0.1um, the spacing of then described second area cloth Fig. 2 and first area cloth Fig. 1 can 〉=0.1um, for example 0.1um, 0.2um, 0.3um, 0.4um, 0.5um etc., described example is not in order to limit only for making explanation clearer.
And had after the Butut that forms according to above-mentioned layout design method, just can make photomask, and form corresponding Miltilayer wiring structure according to the method for above-mentioned formation Miltilayer wiring structure with this layout graph.
Shown in Fig. 1 and Fig. 5 A, provide semiconductor wafer 100.Described semiconductor wafer 100 has had function element usually.Herein for above-mentioned example correspondence, suppose that this semiconductor wafer 100 is for having had the Miltilayer wiring structure of other metal wiring layers except that the second metal wiring layer M8 and the first metal wiring layer M7.
Shown in Fig. 1 and Fig. 5 B, on described semiconductor wafer 100, form first insulating medium layer 101.What described first insulating medium layer was generally commonly used is the fluorine silex glass.Form the method that the fluorine silex glass can adopt the plasma strengthening chemical vapour deposition (CVD).For example, form the fluorine silex glass by feeding silane (SiH4), silicon fluoride (SiF4), oxygen (O2) and argon gas (Ar) on semiconductor wafer 100 surfaces, the flow-rate ratio of described silane, silicon fluoride, oxygen, argon gas changes according to the difference of processing procedure.Wherein said argon gas is as protective gas.Described reaction temperature is 270-350 ℃, for example 270 ℃, 280 ℃, 290 ℃, 300 ℃, 310 ℃, 320 ℃, 330 ℃, 340 ℃, 350 ℃.The time of reaction is depended on the thickness of fluorine silex glass, generally is no more than 60 seconds.Further, after forming the fluorine silex glass, also can carry out cleaning procedure, clean for the fluorine silex glass, improve processing quality by feeding fluorine.
Shown in Fig. 1 and Fig. 5 C, in first insulating medium layer 101, form first metal wiring layer, comprise first area metal wiring layer 102 and second area metal wiring layer 110.The method that forms first metal wiring layer in described first insulating medium layer 101 comprises following process: form and the identical wire laying slot of the first metal wiring layer shape in first insulating medium layer 101, insert first metal in described wire laying slot.
Wherein, the method that forms wire laying slot in first insulating medium layer 101 comprises following process: be coated with photoresist on first insulating medium layer 101, by the photomask according to above-mentioned formation described resist exposure, development being formed the photoresist pattern, is that mask etching first insulating medium layer 101 forms wire laying slot with described photoresist pattern.
Can adopt methods such as metal sputtering method (for example Ta/TaN sputter), electro-plating method (normally electro-coppering) or metallochemistry vapour deposition when in described wire laying slot, inserting first metal.
And, in conjunction with Fig. 5 C and shown in Figure 4, Fig. 4 can also be considered as the vertical view of structure shown in Fig. 5 C, and Fig. 5 C is the cutaway view of structure shown in Figure 4, gap correspondence among Fig. 4 between the figure of the figure of second area cloth Fig. 2 and first area cloth Fig. 1 promptly be first insulating medium layer 101, the corresponding first area of the figure of first area cloth Fig. 1 metal wiring layer 102, the corresponding second area metal wiring layer 110 of the figure of second area cloth Fig. 2.
Shown in Fig. 1 and Fig. 5 D, on described first metal wiring layer, form second insulating medium layer 103.Described second insulating medium layer 103 also adopts the fluorine silex glass.The method that forms described fluorine silex glass is same as described above, has just repeated no more here.
Shown in Fig. 1 and Fig. 5 E, in second insulating medium layer 103, form through hole 104.Described through hole 104 is communicated with second metal wiring layer 105 and first area metal wiring layer 102.The described process that forms through hole 104 in second insulating medium layer 103 is as follows: undercutting through hole in described second insulating medium layer 103, filled conductive material in through hole.
Wherein, the undercutting through hole can adopt the Deep Reaction ion(ic) etching to form the through hole of high-aspect-ratio in second insulating medium layer 103.What described Deep Reaction ion(ic) etching was adopted is high-density plasma, present induction type inductively coupled plasma (ICP, Inductively Coupled Plasma) etch system has become the preferable selection of Deep Reaction ion(ic) etching because high-density plasma and operational stability can be provided.
The packing material of described through hole is electric conducting materials such as copper, and copper is because resistivity is low as preferred electric conducting material.Describedly fill the employing electric plating method for through hole.Method with electro-coppering is exemplified below: described semiconductor wafer with through hole is soaked in the electroplate liquid of copper ions, substrate is connected to negative electrode, electroplate liquid is connected to anode, between negative electrode and anode, switch on then, make the copper ion in the electroplate liquid deposit to the filling of finishing copper in the through hole by electric field action.
Shown in Fig. 1 and Fig. 5 F, on second insulating medium layer 103, form second metal wiring layer 105.Described second metal wiring layer 105 promptly refers to M8 herein.The method that forms described second metal wiring layer 105 can adopt methods such as metal sputtering method (for example Ta/TaN sputter), electro-plating method (normally electro-coppering) or metallochemistry vapour deposition.
The final Miltilayer wiring structure that forms promptly shown in Fig. 5 F, comprises second metal wiring layer 105 in the top layer wire structures; First metal wiring layer under the top layer in one deck wire structures, described first metal wiring layer comprises first area metal wiring layer 102 and second area metal wiring layer 110; Second insulating medium layer 103 of isolating in order to insulation between one deck wire structures under top layer wire structures and the top layer, and the through hole 104 that the first area metal wiring layer 102 of one deck wire structures under second metal wiring layer 105 of top layer wire structures and the top layer is communicated with; First insulating medium layer 101 that one deck wire structures and other wiring layer structures are isolated under the top layer.Described Miltilayer wiring structure has been owing to there has been the support of second area metal wiring layer 110, thereby disperseed the pressure of described top layer wire structures to one deck wire structures under the described top layer, avoided the top layer wire structures to occur subsiding.
Certainly, the metal wiring layer with described first area metal wiring layer and second area metal wiring layer is not limited to the metal wiring layer in one deck wire structures under the above-mentioned top layer of giving an example, and also can be the metal wiring layer in other wire structures.
In sum, the method of above-mentioned disclosed Miltilayer wiring structure and formation Miltilayer wiring structure is by being formed for supporting the second area metal wiring layer of upper strata wire structures on wire structures, disperseed the pressure of upper strata wire structures to the lower-layer wiring structure, increase support force between the wire structures, avoided wire structures to occur subsiding.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (9)
1. a method that forms Miltilayer wiring structure is characterized in that, comprising:
At least form the metal wiring layer that one deck has first area metal wiring layer and second area metal wiring layer, described second area metal wiring layer does not link to each other with the first area metal wiring layer;
Form the upper strata wire structures of described metal wiring layer;
Described first area metal wiring layer is linked to each other with metal wiring layer in the wire structures of upper strata.
2. the method for formation Miltilayer wiring structure as claimed in claim 1 is characterized in that, the spacing of described second area metal wiring layer and first area metal wiring layer is determined by the spacing requirement between the metal in the design rule.
3. the method for formation Miltilayer wiring structure as claimed in claim 2 is characterized in that, described first area metal wiring layer is linked to each other with metal wiring layer in the wire structures of upper strata to be comprised the following steps: to form insulating medium layer on described metal wiring layer; Undercutting forms through hole in described insulating medium layer; Filled conductive material in through hole.
4. the method for formation Miltilayer wiring structure as claimed in claim 3 is characterized in that, described undercutting forms through hole and adopts the Deep Reaction ion(ic) etching.
5. the method for formation Miltilayer wiring structure as claimed in claim 3 is characterized in that, the packing material of described through hole is a copper.
6. Miltilayer wiring structure, it is characterized in that, at least comprise that one deck has the metal wiring layer of first area metal wiring layer and second area metal wiring layer, described first area metal wiring layer is used for linking to each other with the metal wiring layer of upper strata wire structures, and described second area metal wiring layer does not link to each other with the first area metal wiring layer.
7. Miltilayer wiring structure as claimed in claim 6 is characterized in that, the spacing of described second area metal wiring layer and first area metal wiring layer is determined by the spacing requirement between the metal in the design rule.
8. Miltilayer wiring structure as claimed in claim 7 is characterized in that, described first area metal wiring layer links to each other by through hole with metal wiring layer in the wire structures of upper strata.
9. Miltilayer wiring structure as claimed in claim 8 is characterized in that, the packing material of described through hole is a copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710094487 CN101459150A (en) | 2007-12-13 | 2007-12-13 | Multilayered wiring structure and process for forming multilayered wiring structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710094487 CN101459150A (en) | 2007-12-13 | 2007-12-13 | Multilayered wiring structure and process for forming multilayered wiring structure |
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| Publication Number | Publication Date |
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| CN101459150A true CN101459150A (en) | 2009-06-17 |
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| CN 200710094487 Pending CN101459150A (en) | 2007-12-13 | 2007-12-13 | Multilayered wiring structure and process for forming multilayered wiring structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114121793A (en) * | 2021-11-26 | 2022-03-01 | 长电集成电路(绍兴)有限公司 | Multilayer metal wiring layer, preparation method thereof and packaging structure |
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2007
- 2007-12-13 CN CN 200710094487 patent/CN101459150A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114121793A (en) * | 2021-11-26 | 2022-03-01 | 长电集成电路(绍兴)有限公司 | Multilayer metal wiring layer, preparation method thereof and packaging structure |
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Open date: 20090617 |