CN101459122B - Through hole forming method - Google Patents
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- CN101459122B CN101459122B CN2007100944997A CN200710094499A CN101459122B CN 101459122 B CN101459122 B CN 101459122B CN 2007100944997 A CN2007100944997 A CN 2007100944997A CN 200710094499 A CN200710094499 A CN 200710094499A CN 101459122 B CN101459122 B CN 101459122B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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Abstract
A method of forming through holes comprises steps of forming a contact layer on a semiconductor substrate with a shaped doped diffusion region inside, forming a dielectric layer on the contact layer, patterning the dielectric layer to form a contact hole on the exposed partial contact layer, removing the surface of the exposed partial contact layer and keeping the thickness of the residual partial contact layer to meet product requirements, and then filling the contact hole to form a through hole. The method of forming through holes can reduce contact resistance with simple operation.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of through hole formation method.
Background technology
In manufacture of semiconductor, connect effectively in order to make semiconductor device and external circuit, between semiconductor device and metal connecting line, form ohmic contact usually.In desirable ohmic contact, the contact resistance of ohmic contact (Rc) should be low as much as possible.In addition, for electric current as much as possible is transferred to various electric capacity charging the circuit from device, contact resistance accounts for the ratio of device resistance also must be as much as possible little.
In the actual production, the contact resistance of semiconductor device is mainly reflected in interior through hole filling back of before-metal medium layer (PMD) and the junction between device substrate.In the conventional art,, between described through hole and device substrate, form contact layer usually for reducing the contact resistance of device; That is, the step of formation through hole generally includes: form contact layer on the semiconductor-based end, formed doped diffusion region at described the semiconductor-based end; On described contact layer, form dielectric layer; Graphical described dielectric layer is with the described contact layer of expose portion, to form through hole.
Yet actual production is found, as shown in Figure 1, fills and uses the through hole that said method forms, and after forming metal connecting line, to having N type doped semiconductor device, its contact resistance 11 is than the contact resistance 12 of P type doped semiconductor device, and resistance obviously increases.The resistance that how to reduce described contact resistance becomes those skilled in the art's problem demanding prompt solution.
The notification number of announcing on May 11st, 2005 can reduce the contact resistance of semiconductor device for the Chinese patent of " CN 1201393C " provides a kind of through hole formation method.As shown in Figure 2, the step that forms described through hole comprises: form conductive layer 3 on Semiconductor substrate 1; The cobalt silicide film 4 that forms on the top layer of conductive layer 3; On silicon semiconductor substrate 1, form interlayer dielectric 5; The etching interlayer dielectric 5 selectively, to form through hole 6; And fill described through hole 6; In described through hole 6, form the cobalt film; Carry out annealing operation, be thicker than the thickness that is positioned at other regional cobalt silicide film 4 to form cobalt silicide film 7, to make the cobalt silicide film 4 that is positioned at through hole 6 bottoms and 7 thickness; Remove unreacted cobalt film.That is, said method be thicker than by the thickness that makes the cobalt silicide film that is positioned at via bottoms be positioned at other regional cobalt silicide film thickness to reduce contact resistance.
But, for reducing contact resistance, when using said method formation through hole, need comprise the step of twice formation cobalt silicide film, be thicker than the thickness that is positioned at other regional cobalt silicide film so that be positioned at the thickness of the cobalt silicide film of via bottoms; Trivial operations.
Summary of the invention
The invention provides a kind of through hole formation method, can reduce contact resistance, and simple to operate.
A kind of through hole formation method provided by the invention comprises:
On the semiconductor-based end, form contact layer, formed doped diffusion region at described the semiconductor-based end;
On described contact layer, form dielectric layer;
Graphical described dielectric layer is to form the contact hole of expose portion contact layer;
Remove the top layer of the described part contact layer that exposes, remaining described part contact layer has the thickness that satisfies product requirement;
Fill described contact hole, to form through hole.
Alternatively, described contact layer comprises CoSi, NiSi or TiSi.
Alternatively, the step of formation dielectric layer comprises on described contact layer:
On described contact layer, form etching stop layer;
On described etching stop layer, form dielectric layer.
Alternatively, graphical described dielectric layer comprises with the step of the described contact layer of expose portion:
Graphical described dielectric layer, and expose portion etching stop layer;
Remove described partial etching and stop layer, with the described contact layer of expose portion.
Alternatively, described etching stop layer is silicon nitride or silicon oxynitride; Using plasma technology when alternatively, carrying out the operation of removing the described contact layer of part; Alternatively, comprise reacting gas when carrying out the operation of removing the described contact layer of part, described reacting gas comprises Ar; Alternatively, described reacting gas also comprises O
2Or O
3Alternatively, the range of flow of Ar is 10～300sccm; Alternatively, O
2Range of flow be 10～100sccm; Alternatively, O
3Range of flow be 10～100sccm; Alternatively, when carrying out the operation of removing the described contact layer of part, the reaction power scope is 100～500W; Alternatively, when carrying out the operation of removing the described contact layer of part, the reaction pressure scope is 10～100mT.
A kind of through hole formation method provided by the invention comprises:
Form contact layer on the semiconductor-based end, formed doped diffusion region at described the semiconductor-based end, described contact layer has the thickness that is higher than product requirement;
On described contact layer, form dielectric layer;
Graphical described dielectric layer is to form the contact hole of expose portion contact layer;
Remove the top layer of the described part contact layer that exposes, remaining described part contact layer has the thickness that satisfies product requirement;
Fill described contact hole, to form through hole.
Alternatively, described contact layer is CoSi, NiSi or TiSi.
Alternatively, the step of formation dielectric layer comprises on described contact layer:
On described contact layer, form etching stop layer;
On described etching stop layer, form dielectric layer.
Alternatively, graphical described dielectric layer comprises with the step of the described contact layer of expose portion:
Graphical described dielectric layer is with the expose portion etching stop layer;
Remove described partial etching and stop layer, with the described contact layer of expose portion.
Alternatively, described etching stop layer is silicon nitride or silicon oxynitride; Using plasma technology when alternatively, carrying out the operation of removing the described contact layer of part; Alternatively, comprise reacting gas when carrying out the operation of removing the described contact layer of part, described reacting gas comprises Ar; Alternatively, described reacting gas also comprises O
2Or O
3Alternatively, the range of flow of Ar is 10～300sccm; Alternatively, O
2Range of flow be 10～100sccm; Alternatively, O
3Range of flow be 10～100sccm; Alternatively, when carrying out the operation of removing the described contact layer of part, the reaction power scope is 100～500W; Alternatively, when carrying out the operation of removing the described contact layer of part, the reaction pressure scope is 10～100mT.
Compared with prior art, technique scheme has the following advantages:
The through hole formation method that technique scheme provides, by removing the described contact layer of part, after removing the heat treatment operation of introducing when experience is the described contact layer of formation, the high resistant of the doping particle formation in the described contact layer that forms and the dopant diffusion layer that diffuses to its top layer can reduce contact resistance mutually;
The through hole formation method that technique scheme provides, by being pre-formed the contact layer that thickness is higher than product requirement, remove the described contact layer of part again, satisfy the through hole of product requirement with the thickness that obtains contact layer, can on the basis that does not change metal connection structure, reduce contact resistance.
Description of drawings
Fig. 1 is contact resistance resistance testing result schematic diagram bigger than normal in the explanation prior art;
Fig. 2 reduces the structural representation of the through hole that method that contact resistance adopts forms for explanation is applied as in the prior art;
Fig. 3 is the schematic flow sheet of the through hole formation method of explanation first embodiment of the invention;
Fig. 4 is the structural representation after the semiconductor-based end forms contact layer of explanation first embodiment of the invention;
Fig. 5 is the structural representation after forming dielectric layer on the described contact layer of explanation first embodiment of the invention;
Fig. 6 for the explanation first embodiment of the invention graphical described dielectric layer after structural representation;
Fig. 7 for the explanation first embodiment of the invention the formation through hole after structural representation;
Fig. 8 is the testing result schematic diagram of the contact resistance of the N type doped semiconductor device of explanation first embodiment of the invention;
Fig. 9 is the testing result schematic diagram of the contact resistance of the P type doped semiconductor device of explanation first embodiment of the invention;
Figure 10 is the schematic flow sheet of the through hole formation method of explanation second embodiment of the invention;
Figure 11 is the structural representation after the semiconductor-based end forms contact layer of explanation second embodiment of the invention;
Figure 12 is the structural representation after forming dielectric layer on the described contact layer of explanation second embodiment of the invention;
Figure 13 for the explanation second embodiment of the invention graphical described dielectric layer after structural representation;
Figure 14 for the explanation second embodiment of the invention the formation through hole after structural representation.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensive instruction for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer according to following explanation and claims advantages and features of the invention.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
As shown in Figure 3, as the first embodiment of the present invention, the concrete steps of using method formation through hole provided by the invention comprise:
Step 301: in conjunction with Fig. 3 and Fig. 4, on the semiconductor-based end 100, form contact layer 140, formed doped diffusion region 120 at described the semiconductor-based end 100.
Semiconductor substrate (substrate) go up the definition device active region and finish shallow trench isolation from, form grid structure (be among the figure and illustrate) then and doped diffusion region 120 backs form the semiconductor-based end 100.Described Semiconductor substrate comprises but is not limited to comprise the silicon materials of semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).Described grid structure comprises the side wall and the gate oxide of grid, all around gate.Described grid structure also can comprise the barrier layer that covers described grid and side wall.
Described dopant diffusion layer 120 can utilize traditional ion implantation technology to obtain, and described ion implantation technology comprises the ion implant operation finishes the annealing process of back execution; The impurity that mixes in the described dopant diffusion layer 120 includes but not limited to boron (B), fluoridizes inferior boron (BF
2), arsenic (As), phosphorus (P) but or a kind of in other dopant material.
Described contact layer 140 comprises CoSi, NiSi or TiSi; In order to metal connecting line and the contact resistance between the semiconductor-based end that reduces follow-up formation.The step that forms described contact layer 140 comprises: form contact metal layer on the described semiconductor-based end 100; To carrying out annealing operation in the described semiconductor-based end 100 with contact metal layer.
The step of carrying out above-mentioned annealing operation comprises: to carrying out first annealing process in the described semiconductor-based end 100 with contact metal layer, form contact basic unit; Described first contact layer is carried out second annealing process, form contact layer.Particularly, the described first annealing process temperature range is 250～350 degrees centigrade, and the described first annealing process duration scope is 10～30 seconds; The described second annealing process temperature range is 350～500 degrees centigrade, and the described second annealing process duration scope is 10～30 seconds.
Step 302:, on described contact layer 140, form dielectric layer 160 in conjunction with Fig. 3 and Fig. 5.Can adopt PECVD (plasma enhanced CVD), SACVD (inferior normal pressure chemical vapor deposition) or LPCVD technologies such as (low-pressure chemical vapor phase depositions) to form described dielectric layer 160.Described dielectric layer 160 materials are including but not limited to unadulterated silicon dioxide (SiO
2), phosphorosilicate glass (phosphosilicate glass, PSG), Pyrex (borosilicate, BSG), boron-phosphorosilicate glass (borophosphosilicate, BPSG), fluorine silex glass (FSG) or have a kind of or its combination in the advanced low-k materials.Described have advanced low-k materials include but not limited to black diamond (Black Diamond, BD) or coral etc.
Can comprise in the step that forms dielectric layer on the described contact layer: on described contact layer, form etching stop layer; On described etching stop layer, form dielectric layer.Described etching stop layer is silicon nitride or silicon oxynitride.
Step 303: in conjunction with Fig. 3 and Fig. 6, graphical described dielectric layer 160 is to form the contact hole 180 of expose portion contact layer 140.
Can adopt etching technics when carrying out described graphical operation, as wet etching technology or plasma etch process.
Graphical described dielectric layer 160 can comprise with the step of the contact hole 180 that forms expose portion contact layer 140: graphical described dielectric layer 160, and expose portion etching stop layer; Remove described partial etching and stop layer, with the described contact layer 140 of expose portion.Described etching stop layer is silicon nitride or silicon oxynitride.
In the practice, the graphical described etching stop layer of part can be the main etching operation of described etching stop layer; As example, be 100nm if need to carry out the thickness of described patterned passivation layer, the described etching stop layer of graphical 80nm earlier is that the described etching stop layer of 20nm is finished graphical operation to remaining thickness again.Can strengthen and remove the effect that described partial etching stops layer.
In the traditional handicraft, promptly form contact hole behind the completing steps 303.Then, fill described contact hole, and continue to carry out subsequent step, to form through hole; And then the experience subsequent operation forms metal connecting line.
Yet, the semiconductor device behind the formation metal connecting line is carried out finding after the Performance Detection to having the device of N type doped semiconductor substrate, the resistance of its contact resistance increases.And for semiconductor device is connected effectively with external circuit, the contact resistance that forms between semiconductor device and the metal connecting line (Rc) should be low as much as possible, and contact resistance account for the ratio of device resistance also must be as much as possible little.The resistance that how to reduce described contact resistance becomes the subject matter that the present invention solves.
The present inventor thinks after analyzing, the reason that the resistance of contact resistance increases is: when forming described contact layer on the semiconductor-based end, need to introduce heat treatment operation, and the described semiconductor-based end, comprise dopant diffusion layer, be to comprise implanting impurity ion at described the semiconductor-based end, when experiencing described heat treatment operation, described implanting impurity ion will spread, the described implanting impurity ion that diffusion takes place enters described contact layer, and in described contact layer, further diffuse to its top layer, in described heat treatment operation, the implanting impurity ion that diffuses to described contact layer top layer reacts with described contact layer and has formed high resistant mutually.
How removing described high resistant becomes the direction of the resistance that reduces described contact resistance mutually.
Step 304: in conjunction with Fig. 3 and Fig. 7, remove the top layer of the described part contact layer 140 that exposes, remaining described part contact layer 140 has the thickness that satisfies product requirement.
Particularly, be that 50 ± 2nm is an example with the thickness of the described contact layer 140 of product requirement, if the thickness of the described contact layer 140 that forms on the semiconductor-based end is 51nm, then the thickness of the described part contact layer 140 of the exposure of Qu Chuing should be less than or equal to 3nm.In the practice, control the thickness on removed described top layer by the control removal lasting time of operation.As example, remove thickness and be the top layer of described part contact layer 140 of the exposure of 3nm, the time that described removal operation continues can be 10 seconds.
The top layer of the described part contact layer 140 that remove to expose, the implanting impurity ion that diffuses to described contact layer 140 top layers in order to removal and described contact layer 140 react formation high resistant mutually.
Using plasma technology when carrying out the operation of removing the described contact layer of part.Comprise reacting gas when carrying out the operation of removing the described contact layer of part, described reacting gas comprises Ar; The range of flow of Ar is 10～300sccm, as 50sccm, 100sccm, 150sccm or 200sccm; Described reacting gas also comprises O
2Or O
3O
2Range of flow be 10～100sccm, as 20sccm, 50sccm or 80sccm; O
3Range of flow be 10～100sccm, as 20sccm, 50sccm or 80sccm; When carrying out the operation of removing the described contact layer of part, the reaction power scope is 100～500W, as 200W, 300W or 400W; When carrying out the operation of removing the described contact layer of part, the reaction pressure scope is 10～100mT, as 20mT, 50mT or 80mT.
As example, for the 90nm process node, the flow of Ar is 100sccm, O
2Flow be that 40sccm, reaction power are that 300W, reaction pressure are 50Mt, and the operation duration of removing the described contact layer of part, the relativity of the contact resistance 11 of the N type doped semiconductor device that the contact resistance 13 of the N type doped semiconductor device that records and application traditional handicraft obtain as shown in Figure 8 when being 15 seconds.Can adopt Agilent 4700 to carry out the detection of described contact resistance.Abscissa in the detection curve that obtains is the resistance of contact resistance, and unit is ohm; Ordinate is the percentage that surpasses the contact resistance of corresponding resistance in the data that record, and promptly the detection curve of Huo Deing is the distribution function that records contact resistance.
As shown in Figure 8, behind the described contact layer of removal part, the end value of contact resistance is reduced to about 12.5 Europe by about 15.5 Europe, and the detection range of described contact resistance is decreased to about 12.5～16.0 Europe by about 15.5～35.0 Europe.
In addition, use the same terms, the relativity of the contact resistance 12 of the P type doped semiconductor device that the contact resistance 14 of the P type doped semiconductor device that records and application traditional handicraft obtain as shown in Figure 9.As shown in Figure 9, behind the described contact layer of removal part, the end value of contact resistance is reduced to about 12.0 Europe by about 13.5 Europe, and the detection range of described contact resistance is decreased to about 12.0～13.5 Europe by about 13.5～15.0 Europe.
When promptly using technical scheme provided by the invention and forming through hole, by removing the described contact layer of part, after removing the heat treatment operation of introducing when experience is the described contact layer of formation, the high resistant of the doping particle formation in the described contact layer that forms and the dopant diffusion layer that diffuses to its top layer can reduce contact resistance mutually.
Step 305: fill described contact hole 180, to form through hole.
The material of filling described contact hole 180 can comprise W or Cu.Can adopt PVD (physical vapour deposition (PVD)) or MOCVD (metallochemistry vapour deposition) technology to fill described contact hole 180.
As shown in figure 10, as the second embodiment of the present invention, the concrete steps of using method formation through hole provided by the invention comprise:
Step 1001: in conjunction with Figure 10 and Figure 11, form contact layer 240 on the semiconductor-based end 200, formed doped diffusion region 220 at described the semiconductor-based end 200, described contact layer 240 has the thickness that is higher than product requirement.
Semiconductor substrate (substrate) go up the definition device active region and finish shallow trench isolation from, form grid structure (be among the figure and illustrate) then and doped diffusion region 220 backs form the semiconductor-based end 200.Described Semiconductor substrate comprises but is not limited to comprise the silicon materials of semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).Described grid structure comprises the side wall and the gate oxide of grid, all around gate.Described grid structure also can comprise the barrier layer that covers described grid and side wall.
Described dopant diffusion layer 220 can utilize traditional ion implantation technology to obtain, and described ion implantation technology comprises the ion implant operation finishes the annealing process of back execution; The impurity that mixes in the described dopant diffusion layer 220 includes but not limited to boron (B), fluoridizes inferior boron (BF
2), arsenic (As), phosphorus (P) but or a kind of in other dopant material.
Described contact layer 240 comprises CoSi, NiSi or TiSi; In order to metal connecting line and the contact resistance between the semiconductor-based end that reduces follow-up formation.The step that forms described contact layer 240 comprises: form contact metal layer on the described semiconductor-based end 200; To carrying out annealing operation in the described semiconductor-based end 200 with contact metal layer.
The step of carrying out above-mentioned annealing operation comprises: to carrying out first annealing process in the described semiconductor-based end 200 with contact metal layer, form contact basic unit; Described first contact layer is carried out second annealing process, form contact layer.Particularly, the described first annealing process temperature range is 250～350 degrees centigrade, and as 300 degrees centigrade, the described first annealing process duration scope was 10～30 seconds, as 15 seconds or 20 seconds; The described second annealing process temperature range is 350～500 degrees centigrade, and as 400 degrees centigrade or 450 degrees centigrade, the described second annealing process duration scope was 10～30 seconds, as 15 seconds or 20 seconds.
Particularly, be that 50 ± 2nm is an example with the thickness of the described contact layer 140 of product requirement, the thickness of the described contact layer 140 that forms on the semiconductor-based end should be greater than 52nm.
Step 1002:, on described contact layer 240, form dielectric layer 260 in conjunction with Figure 10 and Figure 12.
Can adopt PECVD (plasma enhanced CVD), SACVD (inferior normal pressure chemical vapor deposition) or LPCVD technologies such as (low-pressure chemical vapor phase depositions) to form described dielectric layer 260.Described dielectric layer 260 materials are including but not limited to unadulterated silicon dioxide (SiO
2), phosphorosilicate glass (phosphosilicate glass, PSG), Pyrex (borosilicate, BSG), boron-phosphorosilicate glass (borophosphosilicate, BPSG), fluorine silex glass (FSG) or have a kind of or its combination in the advanced low-k materials.Described have advanced low-k materials include but not limited to black diamond (Black Diamond, BD) or coral etc.
Can comprise in the step that forms dielectric layer on the described contact layer: on described contact layer, form etching stop layer; On described etching stop layer, form dielectric layer.Described etching stop layer is silicon nitride or silicon oxynitride.
Step 1003: in conjunction with Figure 10 and Figure 13, graphical described dielectric layer 260 is to form the contact hole 280 of expose portion contact layer 240.
Graphical described dielectric layer 260 can comprise with the step of the described contact layer 240 of expose portion: graphical described dielectric layer 260, and expose portion etching stop layer; Remove described partial etching and stop layer, with the described contact layer of expose portion.Described etching stop layer is silicon nitride or silicon oxynitride.
Step 1004: in conjunction with Figure 10 and Figure 14, remove the top layer of the described part contact layer 240 that exposes, remaining described part contact layer 240 has the thickness that satisfies product requirement.
Particularly, be that 50 ± 2nm is an example with the thickness of the described contact layer 140 of product requirement, if the thickness of the described contact layer 140 that forms on the semiconductor-based end is 55nm, then the thickness of the described part contact layer 140 of the exposure of Qu Chuing should be more than or equal to 3nm.In the practice, control the thickness on removed described top layer by the control removal lasting time of operation.As example, remove thickness and be the top layer of described part contact layer 140 of the exposure of 3nm, the time that described removal operation continues can be 10 seconds.
Remove the described contact layer 240 of part, the implanting impurity ion that diffuses to described contact layer 240 top layers in order to removal and described contact layer 240 react formation high resistant mutually.
Using plasma technology when carrying out the operation of removing the described contact layer of part.Comprise reacting gas when carrying out the operation of removing the described contact layer of part, described reacting gas comprises Ar; The range of flow of Ar is 10～300sccm, as 50sccm, 100sccm, 150sccm or 200sccm; Described reacting gas also comprises O
2Or O
3O
2Range of flow be 10～100sccm, as 20sccm, 50sccm or 80sccm; O
3Range of flow be 10～100sccm, as 20sccm, 50sccm or 80sccm; When carrying out the operation of removing the described contact layer of part, the reaction power scope is 100～500W, as 200W, 300W or 400W; When carrying out the operation of removing the described contact layer of part, the reaction pressure scope is 10～100mT, as 20mT, 50mT or 80mT.
Step 1005: fill described contact hole 180, to form through hole.
The material of filling described contact hole 180 can comprise W or Cu.Can adopt PVD (physical vapour deposition (PVD)) or MOCVD (metallochemistry vapour deposition) technology to fill described contact hole 180.
The method that using technique scheme provides forms through hole, by being pre-formed the contact layer that thickness is higher than product requirement, remove the described contact layer of part again, satisfy the through hole of product requirement with the thickness that obtains contact layer, can on the basis that does not change metal connection structure, reduce contact resistance.
In the presents, term " equals " to mean comparison both sides' difference in the technology allowed band.
What need emphasize is that not elsewhere specified step all can use conventional methods acquisition, and concrete technological parameter is determined according to product requirement and process conditions.
Although the present invention has been described and has enough described embodiment in detail although describe by the embodiment at this, the applicant does not wish by any way the scope of claims is limited on this details.Other to those skilled in the art advantage and improvement are conspicuous.Therefore, relative broad range the invention is not restricted to represent and the specific detail of describing, equipment and the method and the illustrative example of expression.Therefore, can depart from these details and do not break away from the spirit and scope of the total inventive concept of applicant.
Claims (26)
1. a through-hole of semi-conductor device formation method is characterized in that, comprising:
On the semiconductor-based end, form contact layer, formed doped diffusion region at described the semiconductor-based end;
On described contact layer, form dielectric layer;
Graphical described dielectric layer is to form the contact hole of expose portion contact layer;
Remove the top layer of the described part contact layer that exposes, remaining described part contact layer has the thickness that satisfies product requirement;
Fill described contact hole, to form through hole.
2. through-hole of semi-conductor device formation method according to claim 1 is characterized in that: described contact layer comprises CoSi, NiSi or TiSi.
3. through-hole of semi-conductor device formation method according to claim 1 is characterized in that: the step that forms dielectric layer on described contact layer comprises:
On described contact layer, form etching stop layer;
On described etching stop layer, form dielectric layer.
4. through-hole of semi-conductor device formation method according to claim 3 is characterized in that: graphical described dielectric layer comprises with the step of the described contact layer of expose portion:
Graphical described dielectric layer, and expose portion etching stop layer;
Remove described partial etching and stop layer, with the described contact layer of expose portion.
5. through-hole of semi-conductor device formation method according to claim 3 is characterized in that: described etching stop layer is silicon nitride or silicon oxynitride.
6. through-hole of semi-conductor device formation method according to claim 1 is characterized in that: using plasma technology when carrying out the operation of removing the described contact layer of part.
7. through-hole of semi-conductor device formation method according to claim 1 is characterized in that: comprise reacting gas when carrying out the operation of removing the described contact layer of part, described reacting gas comprises Ar.
8. through-hole of semi-conductor device formation method according to claim 7 is characterized in that: described reacting gas also comprises O
2Or O
3
9. through-hole of semi-conductor device formation method according to claim 7 is characterized in that: the range of flow of Ar is 10～300sccm.
10. through-hole of semi-conductor device formation method according to claim 8 is characterized in that: O
2Range of flow be 10～100sccm.
11. through-hole of semi-conductor device formation method according to claim 8 is characterized in that: O
3Range of flow be 10～100sccm.
12. through-hole of semi-conductor device formation method according to claim 1 is characterized in that: when carrying out the operation of removing the described contact layer of part, the reaction power scope is 100～500W.
13. through-hole of semi-conductor device formation method according to claim 1 is characterized in that: when carrying out the operation of removing the described contact layer of part, the reaction pressure scope is 10～100mT.
14. a through-hole of semi-conductor device formation method is characterized in that, comprising:
Form contact layer on the semiconductor-based end, formed doped diffusion region at described the semiconductor-based end, described contact layer has the thickness that is higher than product requirement;
On described contact layer, form dielectric layer;
Graphical described dielectric layer is to form the contact hole of expose portion contact layer;
Remove the top layer of the described part contact layer that exposes, remaining described part contact layer has the thickness that satisfies product requirement;
Fill described contact hole, to form through hole.
15. through-hole of semi-conductor device formation method according to claim 14 is characterized in that: described contact layer is CoSi, NiSi or TiSi.
16. through-hole of semi-conductor device formation method according to claim 14 is characterized in that: the step that forms dielectric layer on described contact layer comprises:
On described contact layer, form etching stop layer;
On described etching stop layer, form dielectric layer.
17. through-hole of semi-conductor device formation method according to claim 16 is characterized in that: graphical described dielectric layer comprises with the step of the described contact layer of expose portion:
Graphical described dielectric layer is with the expose portion etching stop layer;
Remove described partial etching and stop layer, with the described contact layer of expose portion.
18. through-hole of semi-conductor device formation method according to claim 14 is characterized in that: described etching stop layer is silicon nitride or silicon oxynitride.
19. through-hole of semi-conductor device formation method according to claim 14 is characterized in that: using plasma technology when carrying out the operation of removing the described contact layer of part.
20. through-hole of semi-conductor device formation method according to claim 14 is characterized in that: comprise reacting gas when carrying out the operation of removing the described contact layer of part, described reacting gas comprises Ar.
21. through-hole of semi-conductor device formation method according to claim 20 is characterized in that: described reacting gas also comprises O
2Or O
3
22. through-hole of semi-conductor device formation method according to claim 20 is characterized in that: the range of flow of Ar is 10～300sccm.
23. through-hole of semi-conductor device formation method according to claim 21 is characterized in that: O
2Range of flow be 10～100sccm.
24. through-hole of semi-conductor device formation method according to claim 21 is characterized in that: O
3Range of flow be 10～100sccm.
25. through-hole of semi-conductor device formation method according to claim 14 is characterized in that: when carrying out the operation of removing the described contact layer of part, the reaction power scope is 100～500W.
26. through-hole of semi-conductor device formation method according to claim 14 is characterized in that: when carrying out the operation of removing the described contact layer of part, the reaction pressure scope is 10～100mT.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1182958A (en) * | 1996-11-15 | 1998-05-27 | 三星电子株式会社 | Tungsten nitride (WNx) layer manufacturing method and metal wiring manufacturing method using the same |
| CN1411060A (en) * | 2001-09-27 | 2003-04-16 | 三菱电机株式会社 | Semiconductor device and mfg. method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1182958A (en) * | 1996-11-15 | 1998-05-27 | 三星电子株式会社 | Tungsten nitride (WNx) layer manufacturing method and metal wiring manufacturing method using the same |
| CN1411060A (en) * | 2001-09-27 | 2003-04-16 | 三菱电机株式会社 | Semiconductor device and mfg. method thereof |
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